ICS858012AKT [ICSI]
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER; 低偏移， 1对2 ，差分至2.5V ， 3.3V LVPECL扇出缓冲器
| 型号： | ICS858012AKT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER |
| 文件： | 总15页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS858012 is a high speed 1-to-2 Differential- • Two differential LVPECL outputs
ICS
HiPerClockS™
to-2.5V, 3.3V LVPECL Fanout Buffer and is a
• One differential LVPECL clock input
member of the HiPerClockS™ family of high
performance clock solutions from ICS. The
ICS858012 is optimized for high speed and very
• IN, nIN pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
low output skew, making it suitable for use in demanding
applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The internally terminated
differential input andVREF_AC pin allow other differential signal
families such as LVPECL, LVDS, LVHSTL and HCSL to be
easily interfaced to the input with minimal use of external
components. The ICS858012 is packaged in a small 3mm x
3mm 16-pin VFQFN package which makes it ideal for use in
space-constrained applications.
• Output frequency: 2GHz (typical)
• Output skew: <15ps (typical)
• Part-to-part skew: TBD
• Additive phase jitter, RMS: TBD
• Propagation delay: 350ps (typical)
• Operating voltage supply range:
VCC = 2.375V to 3.63V, VEE = 0V
• -40°C to 85°C ambient operating temperature
• Availabe in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
16 15 14 13
IN
VT
1
2
3
4
12 Q0
11 nQ0
10 nQ1
VREF_AC
Q0
nQ0
IN
VT
nIN
9
Q1
5
6
7
8
nIN
Q1
nQ1
VREF_AC
ICS858012
16-LeadVFQFN
3mm x 3mm x 0.95 package body
K Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
858012AK
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REV.A NOVEMBER 28, 2005
1
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
IN
Type
Description
1
2
Input
Input
Non-inverting LVPECL differential clock input.
Termination input.
VT
Reference voltage for AC-coupled applications.
VREF_AC = to VCC - 1.38V.
3
VREF_AC
Output
4
nIN
VCC
Input
Power
Power
Output
Output
Inverting differential LVPECL clock input.
Positive supply pins.
5, 8, 13, 16
6, 7, 14, 15
9, 10
VEE
Negative supply pin.
Q1, nQ1
nQ0, Q0
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
11, 12
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REV.A NOVEMBER 28, 2005
2
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-0.5V toVCC + 0.5 V
Inputs, VI
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Input Current, IN, nIN
VT Current, IVT
50mA
100mA
0.5mA
Input Sink/Source, IREF_AC
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature, TSTG -65°C to 150°C
PackageThermal Impedance, θJA 51.5°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.63
V
Max., VCC, No Load
30
mA
TABLE 2B. DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V
Symbol Parameter Test Conditions
Minimum
Typical
Maximum Units
RIN
Differential Input Resistance (IN, nIN)
40
1.2
0
50
60
VCC
Ω
V
V
V
V
V
V
VIH
Input High Voltage
(IN, nIN)
(IN, nIN)
VIL
Input Low Voltage
VIH - 0.15
1.7
VIN
Input Voltage Swing; NOTE 1
0.1
0.3
VDIFF_IN
IN to VT
VREF_AC
Differential Input Voltage Swing
1.28
Output Reference Voltage
VCC - 1.525 VCC - 1.4 VCC - 1.325
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram
TABLE 2C. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V
Symbol Parameter
Conditions
Minimum
VCC - 1.145
VCC - 1.945
550
Typical
Maximum Units
VOH
VOL
Output High Voltage; NOTE 1
VCC - 0.895
VCC - 1.695
V
V
Output Low Voltage; NOTE 1
Output Voltage Swing
VOUT
800
mV
VDIFF_OUT Differential Output Voltage Swing
NOTE 1: Outputs terminated with 100Ω across differential output pair.
1100
1600
mV
858012AK
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REV.A NOVEMBER 28, 2005
3
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
TABLE 3. AC CHARACTERISTICS, VCC = 0V; VEE = -3.63V TO -2.375V OR VCC = 2.375 TO 3.63V; VEE = 0V
Symbol Parameter
fMAX Output Frequency
fIN
Condition
Minimum Typical Maximum Units
2
GHz
GHz
Input Frequency
2.5
Propagation Delay; (Differential);
NOTE 1
tPD
350
ps
tsk(o)
Output Skew; NOTE 2, 4
<15
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
TBD
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
TBD
152
fs
tR/tF
Output Rise/Fall Time
20% to 80%
ps
All parameters characterized at ≤ 1GHz unless otherwise noted.
RL = 100Ω after each output pair.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
858012AK
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REV.A NOVEMBER 28, 2005
4
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nIN
LVPECL
VEE
VIN
VIH
Cross Points
VIL
IN
nQx
VEE
-0.375V to -1.63V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nIN
IN
VDIF_IN
VIN
VIN, VOUT
VDIFF_IN, VDIFF_OUT
nQ0, nQ1
800mV
(typical)
1.6V
(typical)
Q0, Q1
tPD
PROPAGATION DELAY
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
80%
tF
80%
VSWING
20%
Clock
20%
Outputs
tR
OUTPUT RISE/FALL TIME
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REV.A NOVEMBER 28, 2005
5
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
LVPECL INPUT WITH BUILT-IN 50Ω TERMINATION INTERFACE (2.5V)
The IN/nIN with built-in 50Ω terminations accepts LVDS,
LVPECL, LVHSTL, CML, SSTL and other differential signals.
Both VSWING and VOH must meet the VPP and VCMR input require-
by the most common driver types. The input interfaces sug-
gested here are examples only.If the driver is from another ven-
dor, use their termination recommendation. Please consult with
ments. Figures 1A to 1E show interface examples for the the vendor of the driver component to confirm the driver termi-
HiPerClockS IN/nIN input with built-in 50Ω terminations driven
nation requirements.
2.5V
2.5V
3.3V or 2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
Built-In
50 Ohm
2.5V LVPECL
LVDS
R1
18
Built-In
50 Ohm
FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER
BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER
2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
VT
Zo = 50 Ohm
Zo = 50 Ohm
nIN
nIN
Receiver
Receiver
With
With
CML - Built-in 50 Ohm Pull-up
CML - Open Collector
Built-In
Built-In
50 Ohm
50 Ohm
FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH BUILT-IN 50Ω PULLUP
BUILT-IN 50Ω DRIVEN BY AN OPEN COLLECTOR
CML DRIVER
2.5V
2.5V
Zo = 50 Ohm
R1
R2
25
IN
VT
Zo = 50 Ohm
nIN
25
Receiver With Built-In 50Ω
SSTL
FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER
858012AK
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REV.A NOVEMBER 28, 2005
6
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
LVPECL INPUT WITH BUILT-IN 50Ω TERMINATION INTERFACE (3.3V)
The IN /nIN with built-in 50Ω terminations accepts LVDS,
LVPECL, LVHSTL, CML, SSTL and other differential signals.
Both VSWING and VOH must meet the VPP and VCMR input require-
ments. Figures 2A to 2E show interface examples for the
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another ven-
dor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termi-
HiPerClockS IN/nIN input with built-in 50Ω terminations driven nation requirements.
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
Built-In
50 Ohm
LVPECL
LVDS
R1
50
Built-In
50 Ohm
FIGURE 2A. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 2B. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER
BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
VT
Zo = 50 Ohm
Zo = 50 Ohm
nIN
nIN
Receiver
Receiver
With
With
CML- Built-in 50 Ohm Pull-Up
CML- Open Collector
Built-In
Built-In
50 Ohm
50 Ohm
FIGURE 2D. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 2C. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH BUILT-IN 50Ω PULLUP
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH OPEN COLLECTOR
3.3V
3.3V
R1
25
Zo = 50 Ohm
Zo = 50 Ohm
IN
VT
nIN
Receiver
With
SSTL
R2
25
Built-In
50 Ohm
FIGURE 2E. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER
858012AK
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REV.A NOVEMBER 28, 2005
7
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
2.5V DIFFERENTIAL INPUT WITH BUILT-IN 50Ω TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and compliment of the
unused input as shown in Figure 3.
2.5V
2.5V
R1
680
IN
VT
nIN
Receiver
with
Built-In
50 Ohm
R2
680
FIGURE 3. UNUSED INPUT HANDLING
3.3V DIFFERENTIAL INPUT WITH BUILT-IN 50Ω TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and compliment of the
unused input as shown in Figure 4.
3.3V
3.3V
R1
1K
IN
VT
nIN
Receiver
with
Built-In
50 Ohm
R2
1K
FIGURE 4. UNUSED INPUT HANDLING
858012AK
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REV.A NOVEMBER 28, 2005
8
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- 50Ω transmission lines. Matched impedance techniques should
tion for LVPECL outputs.The two different layouts mentioned be used to maximize operating frequency and minimize signal
are recommended only as guidelines.
distortion. Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
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REV.A NOVEMBER 28, 2005
9
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 6A and Figure 6B show examples of termination for 2.5V ground level. The R3 in Figure 6B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 6C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 6A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 6B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 6C. 2.5V LVPECL TERMINATION EXAMPLE
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REV.A NOVEMBER 28, 2005
10
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS858012.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS858012 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 30mA = 108.9mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.63V, with all outputs switching) = 108.9mW + 60.4mW = 169.3mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θ
JA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W per Table 4 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.169W * 51.5°C/W = 93.7°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 4. THERMAL RESISTANCE θJA FOR 16 LEAD VFQFN, FORCED CONVECTION
θ
JA at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
858012AK
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REV.A NOVEMBER 28, 2005
11
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT ANDT ERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.895V
OH_MAX
CC_MAX
)
= 0.895V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.695V
OL_MAX
CC_MAX
)
= 1.695V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.895V)/50Ω] * 0.895V = 19.78mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.695V)/50Ω] * 1.695V = 10.34mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV.A NOVEMBER 28, 2005
12
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 5. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θJA at 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS858012 is: 113
Pin compatible with SY58012U
858012AK
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REV.A NOVEMBER 28, 2005
13
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
16
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
4
4
3.0
D2
E
0.25
1.25
3.0
E2
L
0.25
0.30
1.25
0.50
Reference Document: JEDEC Publication 95, MO-220
858012AK
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REV.A NOVEMBER 28, 2005
14
PRELIMINARY
ICS858012
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
TABLE 7.ORDERING INFORMATION
Part/Order Number
ICS858012AK
Marking
012A
012A
TBD
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
16 Lead VFQFN
ICS858012AKT
ICS858012AKLF
ICS858012AKLFT
16 Lead VFQFN
2500 tape & reel
tube
16 Lead "Lead-Free" VFQFN
16 Lead "Lead-Free" VFQFN
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark. HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
858012AK
www.icst.com/products/hiperclocks.html
REV.A NOVEMBER 28, 2005
15
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