ICS8624BYT [ICSI]
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER; 低偏移， 1到5差分至HSTL零延迟缓冲器
| 型号： | ICS8624BYT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER |
| 文件： | 总16页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8624 is a high performance, 1-to-5
• Fully integrated PLL
ICS
Differential-to-HSTL zero delay buffer and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8624 has two selectable clock input pairs.
• 5 differential HSTL outputs
HiPerClockS™
• Selectable differential CLKx, nCLKx input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most
standard differential input levels.The VCO operates at a fre-
quency range of 250MHz to 700MHz. Utilizing one of the
outputs as feedback to the PLL, output frequencies up to
700MHz can be regenerated with zero delay with respect to
the input. Dual reference clock inputs support redundant clock
or multiple reference applications.
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
• Cycle-to-cycle jitter: 25ps (maximum)
• Output skew: 25ps (maximum)
• Static phase offset: 100ps
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
PLL_SEL
Q1
nQ1
÷4, ÷8
0
1
32 31 30 29 28 27 26 25
CLK0
nCLK0
Q2
nQ2
0
1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SEL0
SEL1
VDDO
Q3
CLK1
nCLK1
Q3
nQ3
CLK0
nQ3
Q2
PLL
nCLK0
CLK1
Q4
nQ4
CLK_SEL
ICS8624
nQ2
Q1
nCLK1
CLK_SEL
MR
FB_IN
nFB_IN
nQ1
VDDO
9
10 11 12 13 14 15 16
SEL0
SEL1
MR
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
TopView
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REV. C JUNE 15, 2004
1
ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
Determines the input and output frequency range noted in Table 3.
LVCMOS / LVTTL interface levels.
Determines the input and output frequency range noted in Table 3.
LVCMOS / LVTTL interface levels.
1
SEL0
Input
Input
2
SEL1
Pulldown
3
4
5
6
CLK0
nCLK0
CLK1
Input
Input
Input
Input
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
nCLK1
Pullup
Inverting differential clock input.
Clock select input. When LOW, selects CLK0, nCLK0. When HIGH, selects
CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
7
CLK_SEL
MR
Input
Pulldown
8
Input
Pulldown
9, 32
10
VDD
Power
Input
Input
Core supply pins.
nFB_IN
FB_IN
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
11
Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
12, 13
28, 29
GND
Power
Output
Power
Output
Output
Output
Power supply ground.
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
14, 15
nQ0, Q0
VDDO
16, 17,
24, 25
Output supply pins.
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
18, 19
20, 21
22, 23
nQ1, Q1
nQ2, Q2
nQ3, Q3
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
26, 27
30
nQ4, Q4
VDDA
Output
Power
Analog supply pin.
Selects between the PLL and clock as the input to the dividers.
31
PLL_SEL
Input
Pullup
When HIGH, selects PLL. When LOW, selects reference clock.
LVCMOS / LVTTL interface levels.
NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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REV. C JUNE 15, 2004
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ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL1
SEL0
Reference Frequency Range (MHz)*
Q0:Q4, nQ0:nQ4
0
0
1
1
0
1
0
1
250 - 700
125 - 350
÷ 1
÷ 1
÷ 1
÷ 1
62.5 - 175
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Outputs
Inputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
SEL0
Q0:Q4, nQ0:nQ4
0
0
1
1
0
1
0
1
÷ 4
÷ 4
÷ 4
÷ 8
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ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
1.6
3.3
3.3
1.8
3.465
3.465
2.0
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
120
mA
mA
mA
IDDA
IDDO
15
No Load
0
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
SEL0, SEL1,
CLK_SEL, MR
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
IIH
Input High Current
PLL_SEL
SEL0, SEL1,
CLK_SEL, MR
V
-5
IIL
Input Low Current
PLL_SEL
VDD = 3.465V, VIN = 0V
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
CLK0, CLK1, FB_IN
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
IIH
Input High Current
V
-5
-150
0.1
IIL
Input Low Current
nCLK0, nCLK1, nFB_IN VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.5
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
1.0
0
1.4
0.4
60
V
V
VOL
Output Low Voltage; NOTE 1
VOX
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
40
0.6
ꢀ
V
VSWING
1.1
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
fIN Input Frequency
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum Typical Maximum Units
31.25
700
700
MHz
MHz
CLK0, nCLK0,
CLK1, nCLK1
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
700
4.4
Units
MHz
ns
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
IJ 700MHz
PLL_SEL = 3.3V
3.4
3.9
t(Ø)
tsk(o)
tjit(cc)
tjit(Ø)
tL
-100
100
25
ps
ps
25
ps
50
ps
1
ms
ps
tR
Output Rise Time
20ꢀ to 80ꢀ @ 50MHz
20ꢀ to 80ꢀ @ 50MHz
300
300
700
700
tF
Output Fall Time
ps
tPW
Output Pulse Width
tcycle/2 - 85 tcycle/2 tcycle/2 + 85
ps
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal
across all conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 10ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
Test Conditions
Minimum
Typical
Maximum
Units
35
ps
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ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V 5ꢀ or 10ꢀ
1.8V 0.2V
VDD
SCOPE
,
VDD
VDDA
Qx
nCLK0,
nCLK1
VDDO
VPP
VCMR
Cross Points
HSTL
CLK0,
CLK1
GND
nQx
GND
0V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
nQx
nQ
➤
➤
tcycle n
tcycle n+1
➤
➤
nQy
Qy
t
jit(cc) =
t
cycle n –tcycle n+1
tsk(o)
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nCLK0,
VOH
VOL
nCLK1
CLK0,
CLK1
VOH
VOL
nFB_IN
80ꢀ
tF
80ꢀ
VOD
FB_IN
➤
Clock
20ꢀ
t(Ø)
20ꢀ
➤
Outputs
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
tR
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
OUTPUT RISE/FALL TIME
PHASE JITTER AND STATIC PHASE OFFSET
nQ0:nQ4
nCLK0,
nCLK1
VDDO
2
VDDO
2
VDDO
2
Q0:Q4
CLK0,
CLK1
Pulse Width
nQ0:nQ4
tPERIOD
Q0:Q4
tPD
OUTPUT PULSE WIDTH/PERIOD
PROPAGATION DELAY
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Integrated
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L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS8624 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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Integrated
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Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
LAYOUT GUIDELINE
The schematic of the ICS8624 layout example is shown in will depend on the selected component types, the density of
Figure 4A. The ICS8624 recommended PCB board layout for the components, the density of the traces, and the stack up
this example is shown in Figure 4B. This layout example is of the P.C. board.
used as a general guideline. The layout in the actual system
VDD
SP = Space (i.e. not intstalled)
R7
VDD
VDDA
RU2
SP
RU3
1K
RU4
1K
RU5
SP
10
C11
0.01u
VDD=3.3V
C16
10u
VDDO=1.8V
CLK_SEL
PLL_SEL
SEL0
SEL1
Zo = 50 Ohm
Zo = 50 Ohm
155.5 MHz
DIV_SEL[1:0] = 01
+
-
VDDO
RD2
1K
RD3
SP
RD4
SP
RD5
LVHSTL_input
1K
VDD
U1
R4A
50
R4B
50
3.3V
(155.5 MHz)
Zo = 50 Ohm
SEL0
SEL1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SEL0
SEL1
VDDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
VDDO
CLK0
nCLK0
CLK1
nCLK2
CLK_SEL
MR
Bypass capacitor located near the power pins
Zo = 50 Ohm
CLK_SEL
VDD
(U1-9)
(U1-32)
3.3V PECL Driver
C1
0.1uF
C6
0.1uF
R8
50
R9
50
8624
VDDO
(U1-16)
(U1-17)
(U1-24)
(U1-25)
R10
50
R2B
50
R2A
50
C2
0.1uF
C4
0.1uF
C5
0.1uF
C7
0.1uF
FIGURE 4A. ICS8624 HSTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
The following component footprints are used in this layout
example:
trace delay might be restricted by the available space on the board
and the component location.While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
• The differential 50Ω output traces should have same
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
length.
• Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
GND
R7
C16
C11
C7
VDDO
C6
C5
VDD
U1
Pin 1
VDDA
VIA
50 Ohm
Traces
C4
C1
C2
FIGURE 4B. PCB BOARD LAYOUT FOR ICS8624
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ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8624.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8624 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 120mA = 416mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power_MAX (3.465V, with all outputs switching) = 416mW + 164mW = 580mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.580W * 42.1°C/W = 94.4°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 5.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 5. HSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
- V
)
)
OH_MIN
L
DD_MAX
OH_MIN
/R ) * (V
OL_MAX
L
DD_MAX
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8624 is: 1565
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ICS8624
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEADD LQFP
TABLE 9. PACKAGE DIMENISIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
D
9.00 BASIC
7.00 BASIC
5.60
D1
D2
E
9.00 BASIC
7.00 BASIC
5.60
E1
E2
e
0.80 BASIC
0.60
L
0.45
0.75
θ
0
°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
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ICS8624
Integrated
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L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS8624BY
Marking
Package
Count
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8624BY
ICS8624BY
32 Lead LQFP
250 per tray
1000
ICS8624BYT
32 Lead LQFP on Tape and Reel
32 Lead "Lead Free" LQFP
ICS8624BYLF
ICS8624BYLFT
ICS8624BYLF
ICS8624BYLF
250 per tray
1000
32 Lead "Lead Free" LQFP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
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Integrated
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L
OW
SKEW, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL ZERO
DELAY
BUFFER
REVISION HISTORY SHEET
Rev
A
Table
Page
Description of Change
Date
8
10
Switched labels on Figure 8, odc & tPERIOD diagram.
Revised label on Figure 11 to read ICS8624 LVHSTL... from ICS8634 LVDS...
10/30/01
10/31/01
8/13/02
A
1
Revised Block Diagram
7 - 8
Updated Phase Jitter Diagram and Output Rise & Fall Time Diagram.
A
11 - 12 Revised Figures 3A & 3B.
T1
2
Pin Description table - revised MR & VDD descriptions.
T4A
4
Power Supply table - revised VDD parameter description to correspond with the
Pin Description table.
B
T4C
4
9
Differential DC Charc. table - changed VPP limit from 0.15V minimum to 0.1V
minimum.
2/12/03
Revised Single Ended Signal diagram.
Updated format.
T2
3
4
5
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - updated Output rating.
HSTL DC Characteristics Table - changed VOX to 40% min. - 60% max. and
added note.
T4D
T6B
C
C
2/19/04
6/15/04
5
Added Table 6B AC Characteristics Table with VDD = VDDA = 3.3V 10%.
Changed LVHSTL to HSTL throughout the data sheet.
Added Differential Clock Input Interface section.
8
T10
14
Added "Lead Free" part number to Ordering Information table.
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