ICS8701-01Y [ICSI]
LOW SKEW ±1, ±2 CLOCK GENERATOR W/POLARITY CONTROL; 低偏移± 1 ，± 2时钟发生器W /极性控制
| 型号： | ICS8701-01Y |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW ±1, ±2 CLOCK GENERATOR W/POLARITY CONTROL |
| 文件： | 总10页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
GENERAL DESCRIPTION
FEATURES
The ICS8701-01 is a low skew, ÷1, ÷2 Clock 20 LVCMOS outputs, 7Ω typical output impedance
,&6
Generator and a member of the HiPerClockS
family of High Performance Colck Solutions
Output frequency up to 250 MHz
HiPerClockS™
from ICS. The low impedance LVCMOS outputs
are designed to drive 50Ω series or parallel ter-
250ps bank skew, 300ps output skew, 350ps multiple
frequency skew, 700ps part-to-part skew
minated transmission lines. The effective fanout can be in-
creased from 20 to 40 by utilizing the ability of the outputs to
drive two series terminated lines.
Selectable inverting and non-inverting outputs
LVCMOS / LVTTLclock input
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset/
output enable input, nMR/OE, resets the internal dividers and
controls the active and high impedance states of all outputs.
The output polarity inputs, INV0:1, control the polarity (invert-
ing or non-inverting) of the outputs of each bank. Outputs
QA0-QA4 are inverting for every combination of the INV0:1
input. The timing relationship between the inverting and non-
inverting outputs at different frequencies is shown in the Tim-
ing Diagrams.
LVCMOS / LVTTLcontrol inputs
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
0°C to 70°C ambient operating temperature
Other divide values available on request
The ICS8701-01 is characterized at 3.3V and mixed 3.3V in-
put supply, and 2.5V output supply operating modes. Guar-
anteed bank, output and part-to-part skew characteristics
make the ICS8701-01 ideal for those clock distribution appli-
cations demanding well defined performance and repeatabil-
ity.
BLOCK DIAGRAM
PIN ASSIGNMENT
1
0
÷1
÷2
LVCMOS_CLK
DIV_SELA
QAO - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
48 47 46 45 44 43 42 41 40 39 38 37
QC3
VDDOC
QC4
1
36
35
34
33
32
31
30
29
28
27
26
25
QB1
1
0
2
VDDOB
QB0
3
QD0
4
QA4
DIV_SELB
DIV_SELC
VDDOD
QD1
5
VDDOA
QA3
6
1
0
ICS8701-01
GND
7
GND
QA2
QD2
8
GND
9
GND
QA1
QD3
10
11
12
1
0
VDDOD
QD4
VDDOA
QA0
13 14 15 16 17 18 19 20 21 22 23 24
DIV_SELD
nMR/OE
Output
Polarity
Control
INV0
INV1
48-Pin LQFP
Y Package
Top View
8701-01
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REV. A - AUGUST 28, 2000
1
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDOC
VDDOD
VDDOA
VDDOB
Type
Description
2, 44
Power
Power
Power
Power
Output Bank C power supply. Connect to 3.3V or 2.5V.
Output Bank D power supply. Connect to 3.3V or 2.5V.
Output Bank C power supply. Connect to 3.3V or 2.5V.
Output Bank B power supply. Connect to 3.3V or 2.5V.
5, 11
26, 32
35, 41
7, 9, 18,
21, 28, 30,
37, 39, 46,
48
GND
VDDI
Power
Ground. Connect to ground.
16, 20
Power
Output
Input power supply. Connect to 3.3V.
25, 27, 29,
31, 33
QA0, QA1, QA2,
QA3, QA4
Bank A outputs. LVCMOS interface levels. 7Ω typical output impedance.
34, 36, 38,
40, 42
43, 45, 47, QC0, QC1, QC2,
1, 3
4, 6, 8,
10, 12
QB0, QB1, QB2,
QB3, QB4
Output
Output
Output
Bank B outputs. LVCMOS interface levels. 7Ω typical output impedance.
Bank C outputs. LVCMOS interface levels. 7Ω typical output impedance.
Bank D outputs. LVCMOS interface levels. 7Ω typical output impedance.
QC3, QC4
QD0, QD1, QD2,
QD3, QD4
22
13
LVCMOS_CLK
DIV_SELD
DIV_SELC
DIV_SELB
DIV_SELA
INV1, INV0
Input
Input
Input
Input
Input
Input
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Clock input. LVCMOS interface levels.
Controls frequency division for bank D outputs. LVCMOS interface levels.
Controls frequency division for bank C outputs. LVCMOS interface levels.
Controls frequency division for bank B outputs. LVCMOS interface levels.
Controls frequency division for bank A outputs. LVCMOS interface levels.
Determines polarity of outputs by banks. LVCMOS interface levels.
14
23
24
17, 19
Master reset and output enable. Resets non-inverting outputs to LOW. Sets
inverting outputs to HIGH. Enables and disables all outputs. LVCMOS interface
levels.
15
nMR/OE
Input
Pullup
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
RPULLUP
Input Pullup Resistor
51
KΩ
pF
VDDI, VDDOx = 3.465V
CPD
Power Dissipation Capacitance
(per output)
VDDI = 3.465V, VDDOx = 2.625V
pF
ROUT
Output Impedance
7
Ω
TABLE 3. FUNCTION TABLE
Inputs
DIV_SELx
Outputs
BANK C
Hi Z
nMR/OE
INV1
INV0
BANK A
Hi Z
BANK B
Hi Z
BANK D
Hi Z
Qx frequency
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
zero
fIN/2
fIN/2
fIN/2
fIN/2
fIN
Inverting
Inverting
Inverting
Inverting
Inverting
Inverting
Inverting
Inverting
Non-inverting Non-inverting Non-inverting
Inverting
Inverting
Inverting
Non-inverting Non-inverting
Inverting
Inverting
Non-inverting
Inverting
Non-inverting Non-inverting Non-inverting
Inverting
Inverting
Inverting
Non-inverting Non-inverting
fIN
Inverting
Inverting
Non-inverting
Inverting
fIN
fIN
8701-01
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REV. A - AUGUST 28, 2000
2
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
-0.5V to VDDI + 0.5V
-0.5V to VDDOx + 0.5V
0°C to 70°C
Ambient Operating Temperature
Storage Temperature
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical
Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
TABLE 4A. DC ELECTRICAL CHARACTERISTICS, VDDI = VDDOX = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
3.135
3.135
2
Typical
3.3
Maximum Units
VDDI
Input Power Supply Voltage
Output Power Supply Voltage
3.465
3.465
3.765
3.765
0.8
V
V
VDDOx
3.3
All except LVCMOS_CLK
V
VIH
VIL
Input High Voltage
Input Low Voltage
VDDI = 3.465V
VDDI = 3.135V
LVCMOS_CLK
2
V
All except LVCMOS_CLK
LVCMOS_CLK
-0.3
V
-0.3
1.3
V
IIH
IIL
Input High Current
Input Low Current
VDDI = VIN = 3.465V
VDDI = VIN = 0V
5
µA
µA
mA
-150
2.6
IDD
Quiescent Power Supply Current
Output High Voltage
70
VDDOx = 3.135V
IOH = -36mA
VDDOx =3.135V
IOL = 36mA
VOH
VOL
V
V
Output Low Voltage
0.5
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI = VDDOX = 3.3V±5%, TA=0°C TO 70°C
Symbol
fMAX
tpLH
tpHL
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Maximum Input Frequency
Propagation Delay, Low-to-High
Propagation Delay, High-to-Low
Bank Skew; NOTE 2
250
3.5
MHz
ns
0MHZ < f ≤ 200MHz
2.5
2.5
0MHZ < f ≤ 200MHz
3.5
ns
tsk(b)
tsk(o)
tsk(ω)
tsk(pp)
tR
Measured on falling edge at VDDOx/2
Measured on falling edge at VDDOx/2
Measured on falling edge at VDDOx/2
Measured on falling edge at VDDOx/2
250
300
350
700
700
700
ps
ps
ps
ps
ps
ps
Output Skew; NOTE 3
Multiple Frequency Skew; NOTE 4
Part to Part Skew; NOTE 5
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
150
150
tF
tCYCLE/2
- 0.5
tCYCLE/2
+ 0.5
0MHZ < f < 200MHz
tCYCLE/2
2.5
ns
tPW
Output Pulse Width
f = 200MHz
2
3
6
6
ns
ns
ns
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
tDIS
NOTE 1: All parameters measured at 200MHz unless noted otherwise. All outputs terminated with 50Ω to VDDOx/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs switching in the same direction at the same supply voltages and with equal load
conditions.
NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply
voltages and equal load conditions.
NOTE 5: Defined as the skew at different outputs switching in the same direction on different devices operating at the same supply voltages
and with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701-01
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REV. A - AUGUST 28, 2000
3
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
TABLE 4B. DC ELECTRICAL CHARACTERISTICS, VDDI = 3.3V±5%, VDDOX = 2.5V±5%, TA = 0°C TO 70°C
Symbol
VDDI
Parameter
Test Conditions
Minimum
3.135
2.375
2
Typical
3.3
Maximum Units
Input Power Supply Voltage
Output Power Supply Voltage
3.465
2.625
3.765
3.765
0.8
V
V
VDDOx
2.5
All except LVCMOS_CLK
V
VIH
VIL
Input High Voltage
Input Low Voltage
VDDI = 3.465V
VDDI = 3.135V
LVCMOS_CLK
2
V
All except LVCMOS_CLK
LVCMOS_CLK
-0.3
V
-0.3
1.3
V
IIH
IIL
Input High Current
Input Low Current
VDDI = VIN = 3.465V
VDDI = VIN = 0V
5
µA
µA
mA
-150
1.8
IDD
Quiescent Power Supply Current
70
VDDI = 3.135V
VDDOx = 2.375V
IOH = -27mA
VDDI =3.135V
VDDOx = 2.375V
IOL = 27mA
VOH
VOL
Output High Voltage
V
V
Output Low Voltage
0.5
TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VD DI = 3.3V±5%, VDDO = 2.5V±5%, T A = 0°C TO 70°C
Symbol
fMAX
tpLH
tpHL
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Maximum Input Frequency
Propagation Delay, Low-to-High
Propagation Delay, High-to-Low
Bank Skew; NOTE 2
250
3.5
MHz
ns
0MHZ < f ≤ 200MHz
2.5
2.5
0MHZ < f ≤ 200MHz
3.5
ns
tsk(b)
tsk(o)
tsk(ω)
tsk(pp)
tR
Measured on falling edge at VDDOx/2
Measured on falling edge at VDDOx/2
Measured on falling edge at VDDOx/2
Measured on falling edge at VDDOx/2
300
300
350
700
720
720
ps
ps
ps
ps
ps
ps
Output Skew; NOTE 3
Multiple Frequency Skew; NOTE 4
Part to Part Skew; NOTE 5
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
150
150
tF
tCYCLE/2
- 0.5
tCYCLE/2
+ 0.5
0MHZ < f < 200MHz
tCYCLE/2
2.5
ns
tPW
Output Pulse Width
f = 200MHz
2
3
6
6
ns
ns
ns
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
tDIS
NOTE 1: All parameters measured at 200MHz unless noted otherwise. All outputs terminated with 50Ω to VDDOx/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs switching in the same direction at the same supply voltages and with equal load
conditions.
NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequency with the same supply
voltages and equal load conditions.
NOTE 5: Defined as the skew at different outputs switching in the same direction on different devices operating at the same supply voltages
and with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701-01
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REV. A - AUGUST 28, 2000
4
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
FIGURE 1A, 1B - TIMING DIAGRAMS
LVCMOS_CLK
QA, ÷1, INV
QB, ÷2, INV
QC, ÷2, NINV
QD, ÷1, NINV
FIGURE 1A - ACTIVE, ÷1, ÷2, INVERTING AND NON-INVERTING
nMR/OE
LVCMOS_CLK
QA, ÷1, INV
QB, ÷2, INV
QC, ÷2, NINV
QD, ÷1, NINV
High Impedance
Active
FIGURE 1B - RESET TO ACTIVE, ÷1, ÷2, INVERTING AND NON-INVERTING
8701-01
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REV. A - AUGUST 28, 2000
5
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
FIGURE 2A, 2B - TIMING WAVEFORMS
CLK
3.3V
0V
VDDI/2
VDDI/2
tPHL
tPLH
Q
VDDI/2
VDDI/2
FIGURE 2A - PROPAGATION DELAYS
fin = 200MHz, Vamp = 3.3V, tr = tf = 600ps
nMR/OE
3.3V
0V
VDDI/2
VDDI/2
tPHZ
tPLZ
tPZH
tPZL
Q
VOH
VOH - 300mV
VDDO/2
VDDO/2
VOL
VOL + 300mV
Q
FIGURE 2B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8701-01
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REV. A - AUGUST 28, 2000
6
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
FIGURE 3A, 3B- SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew within a bank of outputs at the same supply voltages and with equal load conditions.
CLK
VDDO/2
VDDO/2
Qx0
tsk(b)
tsk(b)
VDDO/2
VDDO/2
Qx4
FIGURE 3A - BANK SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Output Skew - Skew across banks of outputs switching in the same direction at the same supply voltages and with equal load
conditions.
CLK
VDDO/2
VDDO/2
QA0 - QA4
tsk(o)
tsk(o)
VDDO/2
VDDO/2
QB0 - QB4
QC0 - QC4
QD0 - QD4
FIGURE 3B - INVERTING OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
8701-01
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REV. A - AUGUST 28, 2000
7
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
FIGURE 3C, 3D- SKEW DEFINITIONS & WAVEFORMS
Multiple Frequency Skew - Skew across banks of outputs switching in the same direction operating at different frequencies with
the same supply voltages and equal load conditions.
CLK
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
VDDO/2
or
QD0 - QD4
in ÷1, inverting
tsk(w)
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
or
VDDO/2
QD0 - QD4
in ÷2, inverting
FIGURE 3C - MULTIPLE FREQUENCY SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Part to Part Skew - Skew at different outputs switching in the same direction on different devices operating at the same supply
voltages and with equal load conditions.
CLK
PART 1 QA0 - QA4
QB0 - QB4
QC0 - QC4
VDDO/2
VDDO/2
QD0 - QD4
inverting
tsk(p)
tsk(p)
PART 2 QA0 - QA4
QB0 - QB4
QC0 - QC4
VDDO/2
VDDO/2
QD0 - QD4
inverting
FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
8701-01
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REV. A - AUGUST 28, 2000
8
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX
e / 2
NOTE 4
D
NOTE 5, 7
D1
D/2
NOTE 3
-D-
-A, B, OR -D-
D1/2
b
NOTE 3
-B-
NOTE 3
-A-
E1
E
-A, B, OR -D-
N
O
T
E
5,
7
N
O
T
E
4
e
NOTES:
1. ALL DIMENSIONS AND TOLERANCING CONFORM TO ANSI
Y14.5-1982
2. DATUM PLANE -H- LOCATED AT MOLD PARTING LINE AND
COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY
AT BOTTOM OF PARTING LINE.
E/2
N/4 TIPS
0.20 C A-B
4X
D
3. DATUMS A-B AND -D- TO BE DETERMINED AT CENTERLINE
BETWEEN LEADS WHERE LEADS EXIT PLASTIC AT DATUM
E1/2
PLANE -H-
.
4. TO BE DETERMINED AT SEATING PLACE -C-
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION.
.
SEE DETAIL “A”
6. “N” IS THE TOTAL NUMBER OF TERMINALS.
7. THESE DIMENSIONS TO BE DETEREMINED AT DATUM PLANE
-H-.
8. PACKAGE TOP DIMENSIONS ARE SMALLER THAN BOTTOM
DIMENSIONS AND TOP OF PACKAGE WILL NOT OVERHANG
BOTTOM OF PACKAGE.
8 PLACES
11 / 13°
A
9. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL
IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
10. CONTROLLING DIMENSION: MILLIMETER.
11. THIS OUTLINE CONFORMS TO JEDEC PUBLIBCATION 95
REGISTRATION MS-026, VARIATION BBC.
-H- NOTE 2 / / 0.10
C
ccc
-C-
SEE DETAIL “B”
12. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT OF THE PACKAGE.
NOTE 9
b
ddd
M C A-B S D S
S
JEDEC VARIATION
Y
M
B
O
L
N
O
T
WITH LEAD FINISH
ALL DIMENSIONS IN MILLIMETERS
E
BBC
0.09 / 0.20
0.09 / 0.16
MIN.
NOM.
MAX.
1.60
0.15
1.45
A
A1
A2
D
b1
12
0.05
BASE METAL
1.35
1.40
9.00 BSC.
7.00 BSC.
9.00 BSC.
7.00 BSC.
0.60
4
D1
E
7, 8
4
0° MIN.
E1
L
7, 8
-
0.05 S
0.08/0.20 R.
0.25
GAUGE PLANE
DATUM
PLANE
-H-
0.45
0.75
A2
A1
N
48
e
0.5 BSC.
0.22
0.08
R. MIN.
b
9
0.17
0.17
0.27
0.23
0.08
0.08
0° - 7 °
b1
ccc
ddd
0.20
0.20 MIN.
L
1.00 REF.
8701-01
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REV. A - AUGUST 28, 2000
9
ICS8701-01
LOW SKEW ¸1, ¸2 CLOCK
Integrated
Circuit
Systems, Inc.
GENERATOR W/POLARITY CONTROL
ORDERING INFORMATION
Part/Order Number
Marking
Package
48 Lead LQFP
Count
250 per tray
2000
Temperature
0°C to 70°C
0°C to 70°C
ICS8701-01Y
ICS8701-01
ICS8701-01
ICS8701-01YT
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
8701-01
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REV. A - AUGUST 28, 2000
10
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ICS8701AYI-01LF
Low Skew Clock Driver, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
IDT
ICS8701AYI-01LFT
Low Skew Clock Driver, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
IDT
ICS8701AYI-01T
Low Skew Clock Driver, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48
IDT
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