ICS8701CYI [ICSI]
LOW SKEW ±1, ±2 CLOCK GENERATOR; 低偏移± 1 ，± 2时钟发生器
| 型号： | ICS8701CYI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW ±1, ±2 CLOCK GENERATOR |
| 文件： | 总13页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8701I is a low skew, ÷1, ÷2 Clock Gen-
• 20 LVCMOS outputs, 7 typical output impedance
,&6
erator and a member of the HiPerClockS™
• Output frequency up to 250MHz
HiPerClockS™ family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS out-
• 200ps bank skew, 250ps output skew, 300ps multiple
frequency skew, 600ps part-to-part skew
puts are designed to drive 50 series or par-
allel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the
outputs to drive two series terminated lines.
• LVCMOS / LVTTL clock input
• LVCMOS control inputs
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also con-
trols the active and high impedance states of all outputs.
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
The ICS8701I is characterized at 3.3V and mixed 3.3V in-
put supply, and 2.5V output supply operating modes. Guar-
anteed bank, output and part-to-part skew characteristics
make the ICS8701I ideal for those clock distribution appli-
cations demanding well defined performance and repeat-
ability.
• -40°C to 85°C ambient operating temperature
• Other divide values available on request
BLOCK DIAGRAM
PIN ASSIGNMENT
1
1
LVCMOS_CLK
QAO - QA4
0
2
48 47 46 45 44 43 42 41 40 39 38 37
QC3
VDDO
QC4
1
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
36
35
34
33
32
31
30
29
28
27
26
25
QB1
2
VDDO
QB0
1
0
3
QB0 - QB4
QC0 - QC4
QD0 - QD4
QD0
4
QA4
VDDO
QD1
5
VDDO
QA3
6
ICS8701I
1
0
GND
QD2
7
GND
QA2
8
GND
QD3
9
GND
QA1
10
11
12
VDDO
QD4
VDDO
QA0
1
0
13 14 15 16 17 18 19 20 21 22 23
24
nMR/OE
BANK_EN0
BANK_EN1
Bank Enable
Logic
48-Pin LQFP
Y Package
Top View
8701I
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REV. A MARCH 16, 2001
1
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
2, 5,
Name
Type
Description
11, 26,
32, 35,
41, 44
7, 9, 18,
21, 28, 30,
37, 39, 46,
48
VDDO
Power
Power
Output power supply. Connect to 3.3V or 2.5V.
Ground. Connect to ground.
GND
VDDI
16, 20
Power
Output
Input power supply. Connect to 3.3V.
25, 27,
29,
31, 33
34, 36,
38,
40, 42
43, 45,
47,
1, 3
4, 6,
8,
10, 12
QA0, QA1,
QA2,
QA3, QA4
QB0, QB1,
QB2,
QB3, QB4
QC0, QC1,
QC2,
QC3, QC4
QD0, QD1,
QD2,
Bank A outputs. LVCMOS interface levels.
7
typical output impedance.
Bank B outputs. LVCMOS interface levels.
typical output impedance.
Output
Output
Output
7
Bank C outputs. LVCMOS interface levels.
typical output impedance.
7
Bank D outputs. LVCMOS interface levels
typical output impedance.
7
QD3, QD4
22
LVCMOS_CLK
Input
Input
Pulldown Clock input. LVCMOS interface levels.
Controls frequency division for bank D outputs.
13
DIV_SELD
Pullup
LVCMOS interface levels.
Controls frequency division for bank C outputs.
LVCMOS interface levels.
Controls frequency division for bank B outputs.
LVCMOS interface levels.
Controls frequency division for bank A outputs.
LVCMOS interface levels.
14
23
DIV_SELC
DIV_SELB
DIV_SELA
Input
Input
Input
Input
Input
Pullup
Pullup
24
Pullup
BANK_EN1,
BANK_EN0
17, 19
15
Pullup
Pullup
Enables and disables outputs by banks. LVCMOS interface levels.
Master reset and output enable. Enables and disables all outputs.
LVCMOS interface levels.
nMR/OE
8701I
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REV. A MARCH 16, 2001
2
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
LVCMOS_CLK
pF
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, NMR/OE,
BANK_EN1,
Input
Capacitance
CIN
RPULLUP
Input Pullup Resistor
51
51
K
K
RPULLDOWN Input Pulldown Resistor
VDDI, VDDO =
3.465V
VDDI = 3.465V,
VDDO = 2.625V
pF
CPD
Power Dissipation Capacitance
(per output)
pF
ROUT
Output Impedance
7
TABLE 3. FUNCTION TABLE
Inputs
Outputs
Qx
nMR/OE BANK_EN1 BANK_EN0 DIV_SELx QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4
frequency
zero
fIN/2
fIN/2
fIN/2
fIN/2
fIN
0
1
1
1
1
1
1
1
1
X
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
X
0
0
0
0
1
1
1
1
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Hi Z
Hi Z
Hi Z
Active
Active
Hi Z
Hi Z
Active
Hi Z
Active
Active
Active
Hi Z
Hi Z
fIN
Active
Active
Hi Z
fIN
Active
fIN
8701I
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REV. A MARCH 16, 2001
3
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
-40°C to 85°C
Outputs
Ambient Operating Temperature
Storage Temperature
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of product at these condition or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C
Symbol
VDDI
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Power Supply Voltage
Output Power Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VDDO
VDDI = VIH = 3.465V
VIL = 0V
IDD
Quiescent Power Supply Current
100
mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
VDDI = 3.465V
2
3.8
3.8
0.8
1.3
5
V
V
Input
VIH
High Voltage
BANK_EN1, nMR/OE
LVCMOS_CLK
VDDI = 3.465V
2
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
VDDI = 3.465V
-0.3
-0.3
V
Input
VIL
Low Voltage
BANK_EN1, nMR/OE
LVCMOS_CLK
VDDI = 3.465V
V
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
VDDI = VIN = 3.465V
VDDI = VIN = 3.465V
VDDI = 3.465V, VIN = 0V
VDDI = 3.465V, VIN = 0V
µA
µA
µA
Input
IIH
High Current
BANK_EN1, nMR/OE
LVCMOS_CLK
150
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
-150
Input
IIL
Low Current
BANK_EN1, nMR/OE
LVCMOS_CLK
-5
µA
V
VDDI = VDDO = 3.135V
IOH = -36mA
VDDI = VDDO = 3.135V
IOL = 36mA
VOH
VOL
Output High Voltage
Output Low Voltage
2.6
0.5
V
8701I
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REV. A MARCH 16, 2001
4
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 5A. AC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
tpLH
Maximum Input Frequency
250
3.6
MHz
ns
Propagation Delay,
Low-to-High
Propagation Delay,
High-to-Low
0MHZ
0MHZ
f
f
200MHz
200MHz
2.2
2.2
tpHL
3.6
ns
tsk(b)
tsk(o)
Bank Skew; NOTE 2
Output Skew; NOTE 3
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
200
250
ps
ps
Multiple Frequency Skew;
NOTE 4
tsk(w)
Measured on rising edge at VDDO/2
300
ps
tsk(pp)
tR
Part to Part Skew; NOTE 5 Measured on rising edge at VDDO/2
600
900
900
ps
ps
ps
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
30% to 70%
30% to 70%
200
200
tF
tCYCLE/2
- 0.6
tCYCLE/2
+ 0.6
0MHZ
f
200MHz
tCYCLE/2
2.5
ns
ns
ns
tPW
Output Pulse Width
f = 200MHz
f = 10MHz
1.9
3.1
Output Enable Time;
NOTE 6
tEN
6
Output Disable Time;
NOTE 6
tDIS
f = 10MHz
6
ns
NOTE 1: All parameters measured at 200MHz unless noted otherwise. All outputs terminated with 50 to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and
with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701I
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REV. A MARCH 16, 2001
5
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=-40°C TO 85°C
Symbol
VDDI
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Power Supply Voltage
Output Power Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
V
V
VDDO
VDDI = VIH = 3.465V
VIL = 0V
IDD
Quiescent Power Supply Current
100
mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=-40°C TO 85°C
Symbol Parameter
Test Conditions
VDDI = 3.465V
VDDI = 3.465V
VDDI = 3.465V
VDDI = 3.465V
VIN = 3.465V
VIN = 3.465V
VIN = 0V
Minimum Typical Maximum Units
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
2
3.8
3.8
0.8
1.3
5
V
V
Input
VIH
High Voltage
BANK_EN1, nMR/OE
LVCMOS_CLK
2
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
-0.3
-0.3
V
Input
VIL
Low Voltage
BANK_EN1, nMR/OE
LVCMOS_CLK
V
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
µA
µA
µA
Input
IIH
High Current
BANK_EN1, nMR/OE
LVCMOS_CLK
150
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0,
-150
Input
IIL
Low Current
BANK_EN1, nMR/OE
LVCMOS_CLK
VIN = 0V
-5
µA
V
VDDI = 3.135V,
VDDO = 2.375V
IOH = -27mA
VOH
VOL
Output High Voltage
1.8
VDDI = 3.135V,
VDDO = 2.375V
IOH = 27mA
Output Low Voltage
0.5
V
8701I
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REV. A MARCH 16, 2001
6
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 5B. AC CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=-40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
tpLH
Maximum Input Frequency
250
3.7
MHz
ns
Propagation Delay,
Low-to-High
Propagation Delay,
High-to-Low
0MHZ
0MHZ
f
f
200MHz
200MHz
2.4
2.4
tpHL
3.7
ns
tsk(b)
tsk(o)
Bank Skew; NOTE 2
Output Skew; NOTE 3
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
225
250
ps
ps
Multiple Frequency Skew;
NOTE 4
tsk(w)
Measured on rising edge at VDDO/2
300
ps
tsk(pp)
tR
Part to Part Skew; NOTE 5 Measured on rising edge at VDDO/2
650
900
900
ps
ps
ps
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
30% to 70%
30% to 70%
200
200
tF
tCYCLE/2
- 0.6
tCYCLE/2
+ 0.6
0MHZ
f
200MHz
tCYCLE/2
2.5
ns
ns
ns
tPW
Output Pulse Width
f = 200MHz
f = 10MHz
1.9
3.1
Output Enable Time;
NOTE 6
tEN
6
Output Disable Time;
NOTE 6
tDIS
f = 10MHz
6
ns
NOTE 1: All parameters measured at 200MHz unless noted otherwise. All outputs terminated with 50 to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and
with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8701I
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REV. A MARCH 16, 2001
7
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
FIGURE 1A, 1B - TIMING DIAGRAMS
CLK
Qx, ÷1
Qx, ÷2
FIGURE 1A - ACTIVE, ÷1, ÷2
nMR/OE
CLK
Qx, ÷1
Qx, ÷2
High Impedance
Active
FIGURE 1B - RESET TO ACTIVE, ÷1, ÷2
8701I
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REV. A MARCH 16, 2001
8
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
FIGURE 2A, 2B - TIMING WAVEFORMS
CLK
tPHL
tPLH
Q
VDDO/2
FIGURE 2A - PROPAGATION DELAYS
fin = 200MHz, Vamp = 3.3V, tr = tf = 600ps
nMR/OE,
BANK_ENx
3.3V
0V
BANK_ENx
Q
tPHZ
tPLZ
tPZH
tPZL
VOH
VOH - 300mV
VDDO/2
VDDO/2
VOL
VOL + 300mV
Q
FIGURE 2B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8701I
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REV. A MARCH 16, 2001
9
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
FIGURE 3A, 3B - SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with
equal load conditions.
CLK
Qx0
VDDO/2
VDDO/2
tsk(b)
tsk(b)
Qx4
VDDO/2
VDDO/2
FIGURE 3A - BANK SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with
equal load conditions.
CLK
QA0 - QA4
VDDO/2
VDDO/2
tsk(o)
tsk(o)
QB0 - QB4
QC0 - QC4
QD0 - QD4
VDDO/2
VDDO/2
FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
8701I
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REV. A MARCH 16, 2001
10
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
FIGURE 3C, 3D - SKEW DEFINITIONS & WAVEFORMS
Multiple Frequency Skew - Skew between banks of outputs operating at different frequencies. Outputs operating at the
same temperature, supply voltages and with equal load conditions.
CLK
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
VDDO/2
VDDO/2
or
QD0 - QD4
in ÷1
tsk(
)
tsk( )
VDDO/2
VDDO/2
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
or
FIGURE 3C - MULTIPLE FREQUENCY SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
QD0 - QD4
in ÷2
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply
voltages and with equal load conditions.
CLK
VDDO/2
VDDO/2
PART 1 QA0 - QA4
QB0 - QB4
tsk(p)
tsk(p)
QC0 - QC4
QD0 - QD4
VDDO/2
VDDO/2
PART 2 QA0 - QA4
QB0 - QB4
FIGURE 3B - OUTPUT SKEW
QC0 - QC4
QD0 - QD4
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
8701I
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REV. A MARCH 16, 2001
11
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
D
D2
θ
48
37
36
1
2
3
L
E1
E
E2
N
12
13
25
24
e
A
C
D1
A2
SEATING
PLANE
-C-
ccc
A1
c
b
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
D
9.00 BASIC
7.00 BASIC
5.50
D1
D2
E
9.00 BASIC
7.00 BASIC
5.50
E1
E2
e
0.5 BASIC
0.60
L
0.45
0.75
7°
0°
ccc
0.08
Reference Document: JEDEC Publication 95, MS-026
8701I
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REV. A MARCH 16, 2001
12
ICS8701I
LOW SKEW 1, 2
CLOCK GENERATOR
Integrated
Circuit
Systems, Incꢀ
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8701CYI
Marking
Package
48 Lead LQFP
Count
250 per tray
2000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS8701CYI
ICS8701CYI
ICS8701CYIT
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support
devices or critical medical instruments.
8701I
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REV. A MARCH 16, 2001
13
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