ICS8705BY [ICSI]
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR; 零延迟，差分至LVCMOS / LVTTL时钟发生器
| 型号： | ICS8705BY |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR |
| 文件： | 总17页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8705
Integrated
Circuit
Systems, Inc.
ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8705 is a highly versatile 1:8 Differen- • 8 LVCMOS/LVTTL outputs, 7Ω typical output impedance
ICS
tial-to-LVCMOS/LVTTL Clock Generator and a
• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
member of the HiPerClockS™family of High Per-
HiPerClockS™
• CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
formance Clock Solutions from ICS.The ICS8705
has two selectable clock inputs. The CLK1,
nCLK1 pair can accept most standard differential input lev-
els.The single ended CLK0 input accepts LVCMOS or LVTTL
input levels.The ICS8705 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider and
has an input and output frequency range of 15.625MHz to
250MHz.The reference divider, feedback divider and output
divider are each programmable, thereby allowing for the fol-
lowing output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2,
1:4, 1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock
is routed around the PLL and into the internal output dividers.
• CLK0 input accepts LVCMOS or LVTTL input levels
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: CLK0, 65ps (maximum)
CLK1, nCLK1, 55ps (maximum)
• Static Phase Offset: 25 125ps (maximum), CLK0
• Full 3.3V or 2.5V operating supply
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
Q0
÷2, ÷4, ÷8, ÷16,
÷32, ÷64, ÷128
0
1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK0
0
1
32 31 30 29 28 27 26 25
SEL0
SEL1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDDO
Q5
CLK1
nCLK1
PLL
CLK0
nc
GND
Q4
CLK_SEL
FB_IN
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
ICS8705
CLK1
nCLK1
CLK_SEL
MR
VDDO
Q3
GND
Q2
9
10 11 12 13 14 15 16
SEL0
SEL1
SEL2
SEL3
MR
32-Lead LQFP
7mm x 7mm x 1.4 mm
Y Package
Top View
8705BY
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REV. G JUNE 16, 2004
1
ICS8705
Integrated
Circuit
Systems, Inc.
ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
SEL0, SEL1,
SEL2
Type
Pulldown
Description
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
1, 2, 11
Input
Input
3
4
5
6
CLK0
nc
Pulldown Clock input. LVCMOS/LVTTL interface levels.
No connect.
CLK1
nCLK1
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Clock select input. When HIGH, selects differential CLK1, nCLK1.
7
CLK_SEL
Input
Pulldown When LOW, selects LVCMOS CLK0.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
8
MR
VDD
Input
Power
Input
9, 32
10
Core supply pins.
LVCMOS/LVTTL feedback input to phase detector for regenerating
Pulldown clocks with "zero delay". Connect to one of the outputs.
LVCMOS/LVTTL interface levels.
FB_IN
12, 16, 20,
24, 28
VDDO
Power
Output supply pins.
13, 15, 17,
19, 21, 23,
25, 27
Q0, Q1, Q2,
Q3, Q4, Q5, Output
Q6, Q7
Clock output. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
14, 18, 22, 26
GND
SEL3
VDDA
Power
Power supply ground.
Determines output divider values in Table 3.
Pulldown
29
30
Input
LVCMOS/LVTTL interface levels.
Power
Analog supply pin.
Selects between the PLL and reference clock as input to the dividers.
31
PLL_SEL
Input
Pullup
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance
(per output)
Output Impedance
VDD, VDDO, VDDA = 3.465V
23
7
pF
ROUT
Ω
8705BY
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REV. G JUNE 16, 2004
2
ICS8705
Integrated
Circuit
Systems, Inc.
ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
TABLE 3A. PLL ENABLE FUNCTION TABLE
Outputs
Inputs
SEL0
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
Reference Frequency Range (MHz)
125 - 250
Q0:Q7
÷ 1
÷ 1
÷ 1
÷ 1
÷ 2
÷ 2
÷ 2
÷ 4
÷ 4
÷ 8
x 2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
62.5 - 125
31.25 - 62.5
15.625 -31.25
125 - 250
62.5 - 125
31.25 - 62.5
125 - 250
62.5 - 125
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
31.25 - 62.5
15.625 - 31.25
15.625 - 31.25
x 2
x 2
x 4
x 4
x 8
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q0:Q7
÷ 8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 8
÷ 8
÷ 16
÷ 16
÷ 16
÷ 32
÷ 32
÷ 64
÷ 128
÷ 4
÷ 4
÷ 8
÷ 2
÷ 4
÷ 2
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REV. G JUNE 16, 2004
3
ICS8705
Integrated
Circuit
Systems, Inc.
ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
96
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
20
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
2
VDD + 0.3
V
V
Input
VIH
High Voltage
CLK0
2
V
DD + 0.3
0.8
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
-0.3
-0.3
V
Input
VIL
Low Voltage
CLK0
1.3
V
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
Input
IIH
High Current
PLL_SEL
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
V
-5
Input
IIL
Low Current
PLL_SEL
VDD = 3.465V, VIN = 0V
-150
2.6
µA
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section,
see "3.3V Output Load Test Circuit".
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REV. G JUNE 16, 2004
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ICS8705
Integrated
Circuit
Systems, Inc.
ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum Units
CLK1
V
DD = VIN = 3.465V
150
5
µA
µA
µA
µA
V
nCLK1
CLK1
VDD = VIN = 3.465V
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
nCLK1
V
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
15.625
250
MHz
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 3.3V,
fREF ≤ 200MHz, Qx ÷ 1
PLL_SEL = 3.3V,
fREF ≤ 167MHz, Qx ÷ 1
PLL_SEL = 3.3V,
CLK0
5
7
ns
Propagation Delay,
Low-to-High; NOTE 1
tpLH
CLK1, nCLK1
CLK0
5
7.3
150
285
250
100
300
ns
ps
ps
ps
ps
ps
-100
-15
-50
-150
0
25
+ 135
+100
-25
CLK1, nCLK1
Static Phase Offset;
NOTE 2, 4
t(Ø)
fREF = 200MHz, Qx ÷ 1
PLL_SEL = 3.3V,
fREF = 66MHz, Qx * 2
PLL_SEL = 3.3V,
CLK0
CLK1, nCLK1
150
fREF = 66MHz, Qx * 2
CLK0
PLL_SEL = 0V
PLL_SEL = 0V
fOUT > 40MHz
65
55
45
1
ps
ps
ps
mS
ps
ꢀ
Output Skew;
NOTE 3, 4
tsk(o)
CLK1, nCLK1
tjit(cc)
tL
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
tR / tF
Output Rise/Fall Time
400
43
950
57
odc
Output Duty Cycle
PLL x 4 mode, fin = 45MHz,
fOUT = 180MHz
47
53
ꢀ
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. G JUNE 16, 2004
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ICS8705
Integrated
Circuit
Systems, Inc.
ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.375
2.5
2.5
2.5
2.625
2.625
2.625
90
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
20
TABLE 4E. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
2
VDD + 0.3
V
V
Input
VIH
High Voltage
CLK0
2
V
DD + 0.3
0.8
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
-0.3
-0.3
V
Input
VIL
Low Voltage
CLK0
1.3
V
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
V
DD = VIN = 2.625V
VDD = VIN = 2.625V
DD = 2.625V, VIN = 0V
150
5
µA
µA
µA
Input
IIH
High Current
PLL_SEL
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
V
-5
Input
IIL
Low Current
PLL_SEL
VDD = 2.625V, VIN = 0V
-150
1.8
µA
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information section,
see "2.5V Output Load Test Circuit" figure.
TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum Units
CLK1
V
DD = VIN = 2.625V
150
5
µA
µA
µA
µA
V
nCLK1
CLK1
VDD = VIN = 2.625V
V
DD = 2.625V, VIN = 0V
DD = 2.625V, VIN = 0V
-5
IIL
Input Low Current
nCLK1
V
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V.
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ICS8705
Integrated
Circuit
Systems, Inc.
ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
15.625
250
MHz
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 2.5V,
fREF ≤ 200MHz, Qx ÷ 1
PLL_SEL = 2.5V,
fREF = 133MHz, Qx ÷ 1
PLL_SEL = 2.5V,
fREF = 200MHz, Qx ÷ 1
PLL_SEL = 2.5V,
fREF = 66MHz, Qx * 2
PLL_SEL = 2.5V,
fREF = 66MHz, Qx * 2
CLK0
5
7
ns
Propagation Delay,
Low-to-High; NOTE 1
tpLH
CLK1, nCLK1
CLK0
5
7.3
200
250
300
100
300
ns
ps
ps
ps
ps
ps
-250
-50
-100
-150
0
25
100
+100
-25
CLK1, nCLK1
Static Phase Offset;
NOTE 2, 4
t(Ø)
CLK0
CLK1, nCLK1
150
CLK0
PLL_SEL = 0V
PLL_SEL = 0V
fOUT > 40MHz
65
55
45
ps
ps
ps
Output Skew;
NOTE 3, 4
tsk(o)
CLK1, nCLK1
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
Phase Jitter; NOTE 4, 5
PLL_SEL = 2.5V,
fREF = 66MHz, Qx * 2
tjit(θ)
50
ps
tL
PLL Lock Time
1
950
57
mS
ps
ꢀ
tR / tF
Output Rise/Fall Time
400
43
odc
Output Duty Cycle
PLL x 4 mode, fin = 45MHz,
fOUT = 180MHz
45
55
ꢀ
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Phase jitter is dependent on the input source used.
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ICS8705
Integrated
Circuit
Systems, Inc.
ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD
VDDA
VDDO
,
VDD
VDDA
VDDO
LVCMOS
,
,
,
Qx
Qx
LVCMOS
GND
GND
-1.165V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
VDDO
Qx
Qy
2
nCLK
VPP
VCMR
Cross Points
VDDO
2
CLK
tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
VDDO
2
VDDO
2
VDDO
2
80ꢀ
tF
80ꢀ
tR
Q0:Q7
➤
➤
20ꢀ
20ꢀ
tcycle n+1
tcycle n
➤
➤
Clock
Outputs
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
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ICS8705
Integrated
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ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
nCLK1
CLK1
VOH
VOL
VDD
2
CLK0
VOH
VDDO
VO2L
nCLK1
CLK1
FB_IN
➤
t(Ø)
➤
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t(Ø) mean = Static Phase Offset
VDDO
2
Q0:Q7
➤
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
tPD
➤
PHASE JITTER & STATIC PHASE OFFSET
PROPAGATION DELAY
VDDO
2
VDDO
2
VDDO
2
Q0:Q7
tPW
tPERIOD
tPW
tPERIOD
odc =
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS8705
Integrated
Circuit
Systems, Inc.
ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS8705 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10 µF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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D
ELAY, DIFFERENTIAL
-
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C
LOCK
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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ZERO
D
ELAY, DIFFERENTIAL
-
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C
LOCK
GENERATOR
LAYOUT GUIDELINE
The schematic of the ICS8705 layout example is shown in depend on the selected component types, the density of the
Figure 4A. The ICS8705 recommended PCB board layout components, the density of the traces, and the stack up of the
for this example is shown in Figure 4B. This layout example is
used as a general guideline.The layout in the actual system will
P.C.board.
VDD
R1
43
Zo = 50
R7
10 - 15
VDDA
VDD
C16
10u
C11
0.01u
VDD
U1
SEL0
SEL1
1
2
3
4
5
6
7
8
24
SEL0
SEL1
CLK0
nc
CLK1
nCLK1
CLK_SEL
MR
VDDO
Q5
GND
Q4
VDDO
Q3
GND
Q2
Ro ~ 7 Ohm
Zo = 50
23
22
21
20
19
18
17
R4 43
Driv er_LVCMOS
R5
1K
R4
1K
ICS8705
VDD=3.3V or 2.5V
Logic Input Pin Examples
Set Logic
Set Logic
Input to
'0'
VDD
VDD
Zo = 50
Input to
'1'
R2
43
RU1
1K
RU2
Not Install
To Logic
Input
pins
To Logic
Input
pins
(U1-9)
(U1-12)
(U1-16) (U1-20)
(U1-24)
(U1-28)
(U1-32)
VDD
RD1
Not Install
RD2
1K
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C1
0.1uF
C7
0.1uF
FIGURE 4A. ICS8705 LVCMOS CLOCK GENERATOR SCHEMATIC EXAMPLE
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ELAY, DIFFERENTIAL
-
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C
LOCK
GENERATOR
trace delay might be restricted by the available space on the board
and the component location.While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
• The differential 50Ω output traces should have same
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred.This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
length.
• Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• Make sure no other signal traces are routed between the
clock trace pair.
• The series termination resistors should be located as
close to the driver pins as possible.
GND
50 Ohm
Trace
VDD
C16
C11
R7
R1
VIA
C1
VDDA
Other
signals
C7
Pin 1
C6
C5
U1
C4
C3
R2
C2
50 Ohm
Trace
FIGURE 4B. PCB BOARD LAYOUT FOR ICS8705
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ZERO
D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8705 is: 3126
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D
ELAY, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
C
LOCK
GENERATOR
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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D
ELAY, DIFFERENTIAL
-
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C
LOCK
GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8705BY
Marking
Package
32 Lead LQFP
Count
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8705BY
ICS8705BY
250 per tray
1000
ICS8705BYT
32 Lead LQFP on Tape and Reel
32 Lead "Lead Free" LQFP
ICS8705BYLF
ICS8705BYLFT
ICS8705BYLF
ICS8705BYLF
250 per tray
1000
32 Lead "Lead Free" LQFP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
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D
ELAY, DIFFERENTIAL
-
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C
LOCK
GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
A
1
3
5
Updated Block Diagram
1/25/02
T3A
T5A
PLL Enable Function Table - revised the Reference Frequency Range column
3.3V AC Characteristics Table - updated the Output Frequency row from
350MHz Max. to 275MHz Max.
B
C
3/14/02
4/4/02
T4D:T4F; T5B
T3A
6, 7
3
Added 2.5V tables.
PLL Enable Function Table - revised the Reference Frequency Range column
T5A
3.3V AC Characteristics Table - updated the Output Frequency row from
275MHz Max. to 250MHz Max.
5
T5B
2.5V AC Characteristics Table - updated the Output Frequency row from
275MHz Max. to 250MHz Max.
7
C
C
T1
T2
2
2
Pin Description Table - revised power pin descriptions.
Pin Characteristics Table - add 23pF (typical) in CPD row.
4/10/02
7/15/02
Pin Description Table - Pin# 10 from description, replaced "Connect to pin 10."
with "Connect to one of the outputs."
Revised CLK0 description and MR description.
C
C
T1
T1
2
8/1/02
2
8
8/21/02
Revised Output Rise/Fall Time Diagram.
T1, T4A, T4D
T5A, T5B
2, 4, 6 Revised description for VDD to read Core supply from Positive supply.
5, 7
AC Characteristics, added another row to "odc" with different test conditions
and values.
D
11/22/02
Updated format.
1
2
Pin Description table - revised MR description.
E
F
1/22/03
2/13/03
5 & 7
5 & 7
AC tables - Changed the Static Phase Offset limits for CLK1, nCLK1.
T5A & T5B
T5A & T5B
AC tables - added Static Phase Offset with "fREF = 66MHz, Qx * 2".
3.3V AC table - corrected typo in SPO parameter to read NOTE 4
from NOTE 7.
Throughout datasheet revised title to read "...Differential-to-LVCMOS/LVTTL..."
2.5V AC Characteristics Table - added Phase Jitter spec, and Note 5.
T5B
T2
7
G
G
3/14/03
5/15/03
9
2
Replaced Static Phase Offset Diagram with Phase Jitter & SPO Diagram.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
11
Added Differential Clock Input Interface section.
G
G
12 & 13 Added Layout Guideline
14 Ordering Information Table - added "Lead-Free" part number
6/6/03
T6
6/16/04
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