ICS873033 [ICSI]
HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR; 高速± 4差分至3.3V ， 5V LVPECL / ECL时钟发生器
| 型号： | ICS873033 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR |
| 文件： | 总16页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS873033 is a high speed, high perfor- • One differential 3.3V, 5V LVPECL / ECL output
ICS
mance Differential-to-3.3V, 5V LVPECL/ECL
• One differential PCLK, nPCLK input pair
Clock Generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS873033
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
is characterized to operate from either a 3.3V or a 5V
power supply.
• Input frequency: 3.2GHz (maximum)
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
• Additive phase jitter, RMS: 0.20ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 3.0V to 5.5V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.5V to -3.0V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
RESET
RESET
PCLK
nPCLK
VBB
Vcc
Q
1
2
3
4
8
7
6
5
nQ
VEE
Q
PCLK
nPCLK
÷4
nQ
ICS873033
8-Lead SOIC
VBB
3.90mm x 4.90mm x 1.37mm package body
M Package
TopView
ICS873033
8-LeadTSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
873033AM
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REV.A OCTOBER 19, 2005
1
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
RESET
PCLK
nPCLK
VBB
Type
Description
1
2
Input
Input
Pulldown Reset pin. Single-ended 100h LVPECL interface levels.
Pulldown Clock input. Default LOW when left floating. LVPECL interface levels.
Pulldown Clock input. LVPECL interface levels.
Bias voltage.
3
Input
4
Output
Power
Output
Power
5
VEE
Negative supply pin.
6, 7
8
nQ, Q
VCC
Differential output pair. LVPECL interface levels.
Positive supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Input Pulldown Resistor
75
kΩ
TABLE 3. TRUTH TABLE
Inputs
Outputs
nQ
PCLK
X
nPCLK
X
RESET
Q
L
LH
L
H
LH
HL
÷4
÷4
LH = LOW to HIGH transistion
HL = HIGH to LOW transistion
PCLK
RESET
Q
tRR
tPW
FIGURE 1. TIMING DIAGRAM
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REV.A OCTOBER 19, 2005
2
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5V
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sink/Source, IBB
0.5mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 112.7°C/W (0 lfpm)
(Junction-to-Ambient) for 8 Lead SOIC
PackageThermal Impedance, θJA 101.7°C/W (0 m/s)
(Junction-to-Ambient) for 8 Lead TSSOP
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 5.5V;VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.0
3.3
5.5
30
V
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Typ
Max
Min
Max
2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365
1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference
2.075
1.43
1.86
150
2.36 2.075
1.765 1.43
2.36 2.075
1.765 1.43
2.36
1.765
1.98
VIL
1.98
1.86
150
1.98
1.86
150
VBB
VPP
800
1200
800
1200
800
1200
Peak-to-Peak Input Voltage
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
1.2
3.3
1.2
3.3
1.2
3.3
V
VCMR
IIH
Input
150
150
150
µA
µA
PCLK, nPCLK
High Current
Input
-10
-10
IIL
PCLK, nPCLK
Low Current
-10
Input and output parameters vary 1:1 with VCC. VEE can vary +0.3V to -2.2V.
NOTE 1: Outputs terminated with 50 to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
Ω
873033AM
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REV.A OCTOBER 19, 2005
3
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
3.875 3.975 4.08 3.925 3.995 4.07 3.995 4.03 4.065
3.105 3.245 3.38 3.125 3.22 3.315 3.14 3.235 3.33
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference
3.775
3.13
3.56
150
4.06 3.775
3.465 3.13
4.06 3.775
3.465 3.13
4.06
3.465
3.68
VIL
3.68
3.56
150
3.68
3.56
150
VBB
VPP
800
1200
800
1200
800
1200
Peak-to-Peak Input Voltage
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
1.2
5
1.2
5
1.2
5
V
VCMR
IIH
Input
150
150
150
µA
µA
PCLK, nPCLK
High Current
Input
-10
-10
IIL
PCLK, nPCLK
Low Current
-10
Input and output parameters vary 1:1 with VCC. VEE can vary +2V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V
-40°C
Typ Max
25°C
Typ Max
85°C
Symbol Parameter
Units
Min
-1.125
-1.895
-1.225
-1.87
-1.44
150
Min
-1.075
-1.875
-1.225
-1.87
-1.44
150
Min
-1.005
-1.86
-1.225
-1.87
-1.44
150
Typ Max
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
-1.32
1200
-1.005
-1.78
-0.93
-1.685
-0.94
-1.535
-1.32
1200
-0.97
-0.935
-1.67
-0.94
-1.535
-1.32
1200
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
-1.765
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference
VIL
VBB
VPP
800
800
800
Peak-to-Peak Input Voltage
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
IIH
Input
150
150
150
µA
µA
PCLK, nPCLK
High Current
Input
-10
-10
-10
IIL
PCLK, nPCLK
Low Current
Input and output parameters vary 1:1 with VCC
.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
873033AM
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REV.A OCTOBER 19, 2005
4
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 5. AC CHARACTERISTICS, VCC = 0V;VEE = -5.5V TO -3.0V OR VCC = 3.0V TO 5.5V;VEE = 0V
-40°C 25°C
Min Typ Min Typ
85°C
Min Typ
Symbol Parameter
Units
Max
3.2
Max
3.2
Max
3.2
fMAX
Input Frequency
GHz
ps
tPD
Propagation Delay; NOTE 1
300
475
300
430
0.20
100
530
350
450
0.20
100
550
Buffer Additive Phase Jitter, RMS;
155.52MHz, Integration Range
12kHz - 20MHz; Refer to Additive
Phase Jitter Section
tjit(Ø)
0.20
100
ps
tRR
Set/Reset Recovery; NOTE 2
150
200
100
550
200
100
550
ps
ps
ps
tR/tF
tPW
Output Rise/Fall Time 20% to 80% 100
Pulse Width; NOTE 3 RESET 550
250
250
250
480
480
480
All parameters are measured at f ≤ 1.7GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: See Figure 1, Timing Diagram.
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REV.A OCTOBER 19, 2005
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ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
0
-10
-20
-30
-40
Additive Phase Jitter
@ 155.52MHz (12kHz to 20MHz)
= 0.20ps typical
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measure- above. The device meets the noise floor of what is shown, but
ments have issues. The primary issue relates to the limita- can actually be lower. The phase noise is dependant on the
tions of the equipment. Often the noise floor of the equipment input source and measurement equipment.
is higher than the noise floor of the device. This is illustrated
873033AM
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REV.A OCTOBER 19, 2005
6
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nPCLK
PCLK
VEE
LVPECL
VEE
VPP
VCMR
Cross Points
nQx
-3.5V to -1.0V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
Phase Noise Plot
nPCLK
PCLK
nQ
Phase Noise Mask
Q
tPD
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
PROPAGATION DELAY
RMS PHASE JITTER
80%
tF
80%
VSWING
20%
Clock
20%
Outputs
tR
OUTPUT RISE/FALL TIME
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REV.A OCTOBER 19, 2005
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ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
VBB generated from the device is connected to the negative
input. The C1 capacitor should be located as close as possible
to the input pin.
VCC
C1
0.1u
CLK_IN
PCLK
VBB
nPCLK
FIGURE 3. SINGLE ENDED LVPECL SIGNAL DRIVING
DIFFERENTIAL INPUT
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ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 4A to 4F show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
R1
100
nPCLK
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
R3
84
R4
84
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
1K
R4
1K
R3
120
R4
120
C1
C2
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
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REV.A OCTOBER 19, 2005
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ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. Figures 5A and 5B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 5A. LVPECL OUTPUTT ERMINATION
FIGURE 5B. LVPECL OUTPUTTERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termina-
equivalence of Figure 6A. In actual application where the 3V
DC power supply is not available, this approached is nor-
tion. Figure 6A shows standard termination for 5V LVPECL.
The termination requires matched load of 50Ω resistors pull mally used.
down toVCC - 2V = 3V at the receiver.Figure 6B showsThevenin
5V
5V
5V
5V
R3
84
R4
84
PECL
Zo = 50 Ohm
Zo = 50 Ohm
PECL
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
PECL
PECL
R1
125
R2
125
R1
50
R2
50
3V
FIGURE 6A. STANDARD 5V PECL OUTPUTTERMINATION
FIGURE 6B. 5V PECL OUTPUTT ERMINATION EXAMPLE
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REV.A OCTOBER 19, 2005
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ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS873033.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS873033 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 5.5V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 30mA = 165mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
Total Power_MAX (5.5V, with all outputs switching) = 165mW + 30.94mW = 195.94mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W perTable 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.196W * 103.3°C/W = 105.2°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 6B.THERMAL RESISTANCE θJA FOR 8-PINTSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
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REV.A OCTOBER 19, 2005
11
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT ANDTERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
–0.935V
OH_MAX
CC_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CC_MAX
)
= 1.67V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
873033AM
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REV.A OCTOBER 19, 2005
12
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS873033 is: 165
Pin compatible with MC100EP33
873033AM
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REV.A OCTOBER 19, 2005
13
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
Millimeters
MINIMUN MAXIMUM
SYMBOL
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
873033AM
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REV.A OCTOBER 19, 2005
14
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
8
--
1.10
0.15
0.97
0.38
0.23
A1
A2
b
0
0.79
0.22
0.08
c
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 BASIC
1.95 BASIC
E
E1
e
e1
L
0.40
0°
0.80
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-187
873033AM
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REV.A OCTOBER 19, 2005
15
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS873033AM
Marking
873033AM
873033AM
873033AL
873033AL
TBD
Package
8 lead SOIC
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS873033AMT
ICS873033AMLF
ICS873033AMLFT
ICS873033AG
8 lead SOIC
2500 tape & reel
tube
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
8 lead TSSOP
2500 tape & reel
tube
ICS873033AGT
ICS873033AGLF
ICS873033AGLFT
TBD
8 lead TSSOP
2500 tape & reel
tube
TBD
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV.A OCTOBER 19, 2005
16
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