ICS8752 [ICSI]
LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER; 低偏移， 1至8 LVCMOS时钟乘法器/零延迟缓冲器
| 型号： | ICS8752 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER |
| 文件： | 总15页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8752 is a low voltage, low skew
• Fully integrated PLL
,&6
LVCMOS clock generator and a member of
• 8 LVCMOS outputs, 7Ω typical output impedance
HiPerClockS™
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. With output fre-
quencies up to 240MHz, the ICS8752 is targeted
• Selectable LVCMOS CLK0 or CLK1 inputs for
redundant clock applications
for high performance clock applications. Along with a fully in-
tegrated PLL, the ICS8752 contains frequency configurable
outputs and an external feedback input for regenerating clocks
with “zero delay”.
• Input/Output frequency range: 18.33MHz to 240MHz
at VCC = 3.3V ± 5%
• VCO range: 220MHz to 480MHz
Dual clock inputs, CLK0 and CLK1, support redundant clock
applications. The CLK_SEL input determines which reference
clock is used. The output divider values of Bank A and B are
controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively.
• External feedback for “zero delay” clock regeneration
• Cycle-to-cycle jitter: 75ps (maximum),
(all outputs are the same frequency)
• Output skew: 100ps (maximum)
For test and system debug purposes, the PLL_SEL input
allows the PLL to be bypassed. When HIGH, the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
• Bank skew: 55ps (maximum)
• 3.3V or 2.5V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Functionally compatible with MPC952 in some applications
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
PLL
FB_IN
PHASE
÷2
÷4
00
01
10
11
VCO
CLK0
0
32 31 30 29 28 27 26 25
DETECTOR
1
0
CLK1
QA0
QA1
QA2
QA3
1
÷6
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
CLK0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB1
QB0
VDDO
VDDO
QA3
QA2
GND
CLK_SEL
÷8
÷12
DIV_SELA1
DIV_SELA0
ICS8752
00
01
10
11
QB0
QB1
QB2
QB3
GND
FB_IN
DIV_SELB1
DIV_SELB0
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
MR/nOE
Top View
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REV. A AUGUST 19, 2002
1
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
DIV_SELB0,
DIV_SELB1
DIV_SELA0,
DIV_SELA1
Determines output divider values for Bank B as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank A as described in Table 3.
LVCMOS / LVTTL interface levels.
1, 2
Input
Input
3, 4
Pulldown
Active LOW Master Reset and output enable. When logic LOW, the
5
6
MR/nOE
Input
Pulldown internal dividers are reset. When HIGH, the Master Reset is disabled.
LVCMOS / LVTTL interface levels.
CLK0
GND
Input
Pulldown Clock input. LVCMOS / LVTTL interface levels.
7, 13, 17,
24, 28, 29
Power
Power supply ground.
Feedback input to phase detector for generating clocks with "zero delay".
LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 or CLK1 as phase detector
Pulldown reference. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
8
FB_IN
Input
Input
Pulldown
9
CLK_SEL
10
11, 32
12
VDDA
VDD
Power
Power
Input
Analog supply pin.
Positive supply pins.
CLK1
Pulldown Clock input. LVCMOS / LVTTL interface levels.
14, 15,
18, 19
16, 20,
21, 25
22, 23,
26, 27
QA0, QA1,
QA2, QA3
Bank A clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
Power
VDDO
Output supply pins.
QB0, QB1,
QB2, QB3
Bank B clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
30
nc
Unused
No connect.
Selects between the PLL and CLK0 or CLK1 as the input to the dividers.
31
PLL_SEL
Input
Pullup
When HIGH selects PLL. When LOW selects CLK0 or CLK1.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
Power Dissipation Capacitance
(per output)
CPD
V
DDA, VDD, VDDO = 3.465V
23
7
pF
ROUT
Output Impedance
Ω
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
DIV_
SELA1
Outputs
DIV_
SELA0
DIV_
SELB1
DIV_
SELB0
MR/nOE PLL_SEL CLK_SEL
QAx
QBx
1
0
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
Hi-Z
Hi-Z
0
0
1
1
0
0
1
1
0
0
1
1
fVCO/2
fVCO/4
fVCO/6
fVCO/8
fCLK0/2
fCLK0/4
fCLK0/6
fCLK0/8
fCLK1/2
fCLK1/4
fCLK1/6
fCLK1/8
fVCO/4
fVCO/6
fVCO/8
fVCO/12
fCLK0/4
fCLK0/6
fCLK0/8
fCLK0/12
fCLK1/4
fCLK1/6
fCLK1/8
fCLK1/12
NOTE: For normal operation, MR/nOE is LOW. When MR/nOE is HIGH, all ouputs are disabled.
TABLE 4A. QA OUTPUT FREQUENCY W/FB_IN = QB
Inputs
Outputs
CLK0, CLK1 (MHz)
(NOTE 1)
QB Output
Divider Mode
(NOTE 2)
DIV_
SELB1 SELB0
DIV_
DIV_
DIV_
QA Output
QA Multiplier
(NOTE 2)
FB_IN
SELA1 SELA0 Divider Mode
Minimum Maximum
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
2
1
QB
0
0
1
1
0
1
0
1
÷4
÷6
55
120
80
0.667
0.5
3
1.5
1
QB
QB
QB
36.66
27.5
0.75
4
2
÷8
60
1.33
1
6
3
÷12
18.33
40
2
1.5
NOTE 1: VCO frequency range is 220MHz to 480MHz.
NOTE 2: QA output frequency equal to CLKx frequency times the multiplier;
QB output frequency equal to CLKx.
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4B. QB OUTPUT FREQUENCY W/FB_IN = QA
Inputs
CLK0, CLK1 (MHz)
Outputs
QA Output
Divider Mode
(NOTE 2)
QB Output
Divider Mode
DIV_
SELA1 SELA0
DIV_
DIV_
SELB1
DIV_
SELB0
QB Multiplier
(NOTE 2)
(NOTE 1)
FB_IN
Minimum Maximum
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
÷4
÷6
0.5
0.333
0.25
0.167
1
QA
0
0
110
240
(NOTE 3)
÷2
÷8
÷12
÷4
÷6
0.667
0.5
QA
QA
QA
0
1
1
1
0
1
÷4
÷6
÷8
55
120
80
÷8
÷12
÷4
0.333
1.5
÷6
1
36.66
27.5
÷8
0.75
0.5
÷12
÷4
2
÷6
1.333
1
60
÷8
÷12
0.667
NOTE 1: VCO frequency range is 220MHz to 480MHz.
NOTE 2: QB output frequency equal to CLKx frequency times the multiplier;
QA output frequency equal to CLKx.
NOTE 3: Maximum frequency of 240MHz valid for VCC = 3.3V ± 5% only.
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REV. A AUGUST 19, 2002
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Positive Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
105
V
V
Analog Supply Voltage
Output Supply Voltage
Positive Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
20
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
CLK0, CLK1,
FB_IN, CLK_SEL,
DIV_SELA1, DIV_SELA0,
DIV_SELB1, DIV_SELB0,
MR/nOE
VDD = VIN = 3.465V
150
5
µA
µA
µA
IIH
Input High Current
PLL_SEL
VDD = VIN = 3.465V
CLK0, CLK1,
FB_IN, CLK_SEL,
DIV_SELA1, DIV_SELA0,
DIV_SELB1, DIV_SELB0,
MR/nOE
VDD = 3.465V,
-5
V
IN = 0V
IIL
Input Low Current
VDD = 3.465V,
VIN = 0V
PLL_SEL
-150
2.4
µA
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
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REV. A AUGUST 19, 2002
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 6A. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
Input Reference Frequency
fREF
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
20
240
MHz
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
÷2
÷4
110
55
240
120
80
MHz
MHz
MHz
MHz
MHz
MHz
fOUT
Output Frequency (PLL Mode)
÷6
36.67
27.5
18.33
220
÷8
60
÷12
40
fVCO
PLL VCO Lock Range
480
fVCO = 400MHz,
Feedback ÷ 8
t(Ø)
Static Phase Offset; NOTE 1
-30
70
170
55
ps
ps
Measured on rising edge
at VDDO/2
tsk(b)
tsk(o)
Bank Skew; NOTE 2, 4
Output Skew; NOTE 3, 4
Measured on rising edge
at VDDO/2
100
400
75
ps
ps
ps
Different Frequencies
on Different Banks
All Outputs at
Cycle-to-Cycle
Jitter; NOTE 4
tjit(cc)
Same Frequency
tL
PLL Lock Time
Output Rise Time
Output Fall Time
1
mS
ps
ps
%
tR
20% to 80%
20% to 80%
400
400
47
950
950
53
tF
odc
Output Duty Cycle
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8752CY
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REV. A AUGUST 19, 2002
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 5C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Positive Supply Voltage
2.375
2.375
2.375
2.5
2.5
2.5
2.625
2.625
2.625
100
V
V
Analog Supply Voltage
Output Supply Voltage
Positive Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
20
TABLE 5D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
CLK0, CLK1,
FB_IN, CLK_SEL,
DIV_SELA1, DIV_SELA0,
DIV_SELB1, DIV_SELB0,
MR/nOE
VDD = VIN = 2.625V
150
5
µA
µA
µA
IIH
Input High Current
PLL_SEL
VDD = VIN = 2.625V
CLK0, CLK1,
FB_IN, CLK_SEL,
DIV_SELA1, DIV_SELA0,
DIV_SELB1, DIV_SELB0,
MR/nOE
VDD = 2.625V,
-5
V
IN = 0V
IIL
Input Low Current
VDD = 2.625V,
VIN = 0V
PLL_SEL
-150
1.8
µA
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section,
"2.5 Output Load Test Circuit".
TABLE 6B. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Input Reference Frequency
Test Conditions
Minimum Typical Maximum Units
20 120 MHz
fREF
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
÷2
÷4
110
55
240
120
80
MHz
MHz
MHz
MHz
MHz
MHz
fOUT
Output Frequency (PLL Mode)
÷6
36.67
27.5
18.33
220
÷8
60
÷12
40
fVCO
PLL VCO Lock Range
480
fVCO = 400MHz
Feedback ÷ 8
Measured on rising edge
at VDDO/2
t(Ø)
Static Phase Offset; NOTE 1
-90
50
190
55
ps
ps
ps
ps
ps
tsk(b)
tsk(o)
Bank Skew; NOTE 2, 4
Output Skew; NOTE 3, 4
Measured on rising edge
at VDDO/2
90
Different Frequencies
400
75
on Different Banks
All Outputs at
Cycle-to-Cycle
Jitter; NOTE 4
tjit(cc)
Same Frequency
tL
PLL Lock Time
Output Rise Time
Output Fall Time
1
mS
ps
ps
%
tR
20% to 80%
20% to 80%
400
400
45
950
950
55
tF
odc
Output Duty Cycle
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8752CY
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REV. A AUGUST 19, 2002
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
SCOPE
VDD
VDDA
VDDO
,
,
Qx
LVCMOS
GND
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
1.25V±5%
SCOPE
VDD
VDDA
VDDO
,
,
Qx
LVCMOS
GND
-1.25V±5%
2.5V OUTPUT LOAD TEST CIRCUIT
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
VDDO
2
Qx
Qy
VDDO
2
tsk(o)
OUTPUT SKEW
VDDO
VDDO
2
VDDO
2
2
QAx, QBx
➤
➤
tcycle n+1
tcycle n
➤
➤
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
VDD
/2
CLK0, CLK1
FB_IN
VDD
/2
➤
t(Ø)
➤
STATIC PHASE OFFSET
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REV. A AUGUST 19, 2002
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
80%
80%
20%
20%
Clock Outputs
tR
tF
OUTPUT RISE AND FALL TIME
VDDO
2
QAx, QBx
Pulse Width
tPERIOD
odc & tPERIOD
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8752 is: 1546
8752CY
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REV. A AUGUST 19, 2002
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ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8752CY
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REV. A AUGUST 19, 2002
13
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8752CY
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8752CY
ICS8752CY
ICS8752CYT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
8752CY
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
14
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Rev
Table
T1
Page
Description of Change
Date
A
2
Pin Descriptions Table. Revised MR/nOE description.
8/19/02
8752CY
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REV. A AUGUST 19, 2002
15
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