ICS87973I-147 [ICSI]
LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER; 低偏移， 1到12 LVCMOS / LVTTL时钟乘法器/零延迟缓冲器
| 型号： | ICS87973I-147 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER |
| 文件： | 总16页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS87973I-147 is a LVCMOS/LVTTL clock
• Fully integrated PLL
ICS
generator and a member of the HiPerClockS™fam-
• 14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync
• Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs
HiPerClockS™
ily of High Performance Clock Solutions from ICS.
The ICS87973I-147 has three selectable inputs
and provides 14 LVCMOS/LVTTL outputs.
• CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
The ICS87973I-147 is a highly flexible device.The three select-
able inputs (1 differential and 2 single ended inputs) are often
used in systems requiring redundant clock sources. Up to three
different output frequencies can be generated among the three
output banks.
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 10MHz to 150MHz
• VCO range: 240MHz to 500MHz
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. The output fre-
quency range is 10MHz to 150MHz.The input frequency range is
6MHz to 120MHz.
• Output skew: 200ps (maximum)
• Cycle-to-cycle jitter, (all banks ÷ 4): 55ps (maximum)
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible with MPC973
The ICS87973I-147 also has a QSYNC output which can be
used for system synchronization purposes. It monitors Bank A
and Bank C outputs and goes low one period prior to coincident
rising edges of Bank A and Bank C clocks. QSYNC then goes
high again when the coincident rising edges of Bank A and
Bank C occur.This feature is used primarily in applications where
Bank A and Bank C are running at different frequencies, and is
particularly useful when they are running at non-integer mul-
tiples of one another.
• Compatible with PowerPC™andPentium™ Microprocessors
PIN ASSIGNMENT
Example Applications:
1. System Clock generator: Use a 16.66MHz reference
clock to generate eight 33.33MHz copies for PCI and
four 100MHz copies for the CPU or PCI-X.
39 38 37 36 35 34 33 32 31 30 29 28 27
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
FSEL_FB1
QSYNC
GNDO
QC0
2. Line Card Multiplier: Multiply differential 62.5MHz from
a back plane to single-ended 125MHz for the line Card
ASICs and Gigabit Ethernet Serdes.
VDDO
VDDO
QC1
3. Zero Delay buffer for Synchronous memory: Fan out
up to twelve 100MHz copies from a memory controller
reference clock to the memory chips on a memory module
with zero delay.
QA2
FSEL_C0
FSEL_C1
QC2
ICS87973I-147
GNDO
QA1
VDDO
VDDO
QA0
QC3
GNDO
VCO_SEL
GNDO
INV_CLK
1
2
3
4
5
6
7
8
9 10 11 12 13
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
TopView
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
BLOCK DIAGRAM
VCO_SEL
PLL_SEL
REF_SEL
CLK
1
0
nCLK
SYNC
FRZ
D
Q
QA0
QA1
QA2
QA3
CLK0
CLK1
0
1
0
1
SYNC
FRZ
PHASE
DETECTOR
VCO
SYNC
FRZ
LPF
CLK_SEL
EXT_FB
SYNC
FRZ
SYNC
FRZ
D
Q
QB0
QB1
QB2
QB3
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
FSEL_FB2
nMR/OE
D
D
D
Q
Q
Q
QC0
QC1
QC2
QC3
QFB
POWER-ON
RESET
SYNC
FRZ
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
SYNC
FRZ
SYNC
FRZ
2
2
2
3
0
1
÷4, ÷6, ÷8, ÷10
SYNC PULSE
FSEL_A0:1
÷2
FSEL_B0:1
FSEL_C0:1
FSEL_FB0:2
SYNC
SYNC
FRZ
FRZ
D
Q
QSYNC
DATA GENERATOR
FRZ_CLK
OUTPUT DISABLE
CIRCUITRY
12
FRZ_DATA
INV_CLK
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
SIMPLIFIED BLOCK DIAGRAM
nMR/OE
FSEL_A[0:1]
2
CLK
1
0
nCLK
CLK0
FSEL_
A1 A0
SYNC
FRZ
QA0
QA1
QA2
QA3
0
1
QAx
÷4
÷6
÷8
PLL
0
0
1
1
0
1
0
1
CLK1
SYNC
FRZ
VCO RANGE
240MHz - 500MHz
CLK_SEL
REF_SEL
SYNC
FRZ
0
1
÷12
SYNC
FRZ
÷2
÷1
0
1
EXT_FB
FSEL_B[0:1]
2
SYNC
FRZ
QB0
QB1
QB2
QB3
FSEL_
B1 B0
QBx
÷4
÷6
÷8
VCO_SEL
PLL_SEL
0
0
1
1
0
1
0
1
SYNC
FRZ
SYNC
FRZ
÷10
SYNC
FRZ
FSEL_C[0:1]
2
FSEL_
QC0
QC1
QC2
QC3
C1 C0 QCx
0
0
1
1
0
1
0
1
÷2
÷4
÷6
÷8
SYNC
FRZ
SYNC
FRZ
0
1
SYNC
FRZ
INV_CLK
FSEL_FB[0:2]
3
FSEL_
FB2 FB1 FB0 QFB
QFB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
FRZ_CLK
FRZ_DATA
O
UTPUT
D
ISABLE
SYNC
FRZ
QSYNC
CIRCUITRY
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
GNDI
Power
Input
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs. When
LOW, resets the outputs to tristate and resets output divide circuitry.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
2
nMR/OE
Pullup
3
4
FRZ_CLK
Input
Input
Pullup
Pullup
Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Configuration data input for freeze circuitry.
LVCMOS / LVTTL interface levels.
FRZ_DATA
FSEL_FB2,
FSEL_FB1, Input
FSEL_FB0
Select pins control Feedback Divide value.
LVCMOS / LVTTL interface levels.
5, 26, 27
Pullup
Pullup
Pullup
Pullup
Selects between the PLL and reference clocks as the input to the output
dividers. When HIGH, selects PLL. When LOW, bypasses the PLL.
LVCMOS / LVTTL interface levels.
Selects between CLK0 or CLK1 and CLK, nCLK inputs.
When HIGH, selects CLK, nCLK. When LOW, selects CLK0 or CLK1.
LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 and CLK1 as phase detector
reference. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
6
7
PLL_SEL
REF_SEL
CLK_SEL
Input
Input
8
Input
Input
CLK0,
CLK1
9, 10
Pullup
Pullup
Reference clock inputs. LVCMOS / LVTTL interface levels.
11
12
13
CLK
nCLK
VDDA
Input
Input
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Analog supply pin.
Power
Inverted clock select for QC2 and QC3 outputs.
LVCMOS / LVTTL interface levels.
14
INV_CLK
GNDO
Input
Power
Output
Power
Input
Pullup
15, 24, 30,
35, 39, 47, 51
16, 18,
21, 23
17, 22, 33,
37, 45, 49
Power supply ground.
QC3, QC2,
QC1, QC0
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
VDDO
Output supply pins.
FSEL_C1,
FSEL_C0
19, 20
25
Pullup
Pullup
Select pins for Bank C outputs. LVCMOS / LVTTL interface levels.
Synchronization output for Bank A and Bank C. Refer to Figure 1,
Timing Diagrams. LVCMOS / LVTTL interface levels.
QSYNC
Output
28
29
31
VDD
QFB
Power
Output
Input
Core supply pins.
Feedback clock output. LVCMOS / LVTTL interface levels.
Extended feedback. LVCMOS / LVTTL interface levels.
EXT_FB
32, 34,
36, 38
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
Bank B clock outputs.7Ω typical output impedance.
Output
Input
LVCMOS / LVTTL interface levels.
40, 41
42, 43
Pullup
Pullup
Select pins for Bank B outputs. LVCMOS / LVTTL interface levels.
Select pins for Bank A outputs. LVCMOS / LVTTL interface levels.
Input
44, 46,
48, 50
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1.
When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.
Output
Input
52
VCO_SEL
Pullup
NOTE: Pullup refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
RPULLUP
RPULLDOWN
,
Input Pullup/Pulldown Resistor
51
KΩ
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDA, VDDO = 3.465V
18
12
pF
ROUT
Output Impedance
5
7
Ω
TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Outputs
QA
Inputs
Outputs
QB
Inputs
Outputs
QC
÷2
FSEL_A1 FSEL_A0
FSEL_B1
FSEL_B0
FSEL_C1
FSEL_C0
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷6
÷6
÷4
÷8
÷8
÷6
÷12
÷10
÷8
TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Outputs
FSEL_FB2
FSEL_FB1
FSEL_FB0
QFB
÷4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷6
÷8
÷10
÷8
÷12
÷16
÷20
TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE
Control Pin
VCO_SEL
REF_SEL
CLK_SEL
PLL_SEL
nMR/OE
Logic 0
VCO/2
Logic 1
VCO
CLK0 or CLK1
CLK0
CLK, nCLK
CLK1
BYPASS PLL
Enable PLL
Enable Outputs
Inverted QC2, QC3
Master Reset/Output Hi Z
Non-Inverted QC2, QC3
INV_CLK
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
fVCO
1:1 MODE
2:1 MODE
3:1 MODE
3:2 MODE
4:1 MODE
4:3 MODE
6:1 MODE
QA
QC
QSYNC
QA
QC
QSYNC
QC(÷2)
QA(÷4)
QSYNC
QC(÷2)
QA(÷8)
QSYNC
QC(÷2)
QA(÷8)
QSYNC
QA(÷6)
QC(÷8)
QSYNC
QA(÷12)
QC(÷2)
QSYNC
FIGURE 1. TIMING DIAGRAMS
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Inputs, VI
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
Outputs, VO
PackageThermal Impedance, θJA 42.3°C/W (0 lfpm)
StorageTemperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
2.935
3.135
3.3
3.3
3.3
3.465
3.465
3.465
225
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
IDDA
20
NOTE: Special thermal handling may be required in some configurations.
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS Inputs
LVCMOS Inputs
2
VDD + 0.3
0.8
V
V
Input Low Voltage
Input Current
-0.3
IIN
120
µA
V
VOH
VOL
VPP
VCMR
Output High Voltage
Output Low Voltage
IOH = -20mA
IOL = 20mA
CLK, nCLK
CLK, nCLK
2.4
0.5
1
V
Peak-to-Peak Input Voltage; NOTE 1, 2
Common Mode Input Voltage; NOTE 1, 2
0.3
V
VDD - 2V
VDD - 0.6V
V
NOTE 1: Common mode voltage is defined as VIH of the differential signal.
NOTE 2. For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fIN Input Frequency
Test Conditions
Minimum Typical Maximum Units
CLK0, CLK1,
CLK, nCLK; NOTE 1
120
MHz
FRZ_CLK
20
MHz
NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * Feedback Divide" is in the VCO range of
240MHz to 500MHz.
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ICS87973I-147
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK
M
ULTIPLIER/ZERO
DELAY
BUFFER
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±±5, TA = -40°C TO 8±°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
1±0
Units
MHz
MHz
MHz
÷2
÷4
÷6
÷8
12±
fMAX
Output Frequency
83.33
62.±
300
24±
16±
200
±±
MHz
ps
CLK0
-10
-6±
14±
90
QFB ÷8
In Frequency = ±0MHz
Static Phase Offset;
NOTE 1
t(Ø)
CLK1
ps
CLK, nCLK
-130
18
ps
tsk(o)
tjit(cc)
fVCO
Output Skew; NOTE 2
ps
Cycle-to-Cycle Jitter; NOTE 3, 4
PLL VCO Lock Range
PLL Lock Time; NOTE 3
Output Rise/Fall Time
Output Duty Cycle
All Banks ÷ 4
0.8V to 2V
ps
240
±00
10
MHz
mS
ps
tLOCK
tR / tF
odc
1±0
4±
2
700
±±
5
tPZL, tPZH Output Enable Time; NOTE 3
tPLZ, tPHZ Output Disable TIme; NOTE 3
10
ns
2
8
ns
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 6±.
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
VDD
SCOPE
VDD
,
V
DDA, VDDO
nCLK
Qx
LVCMOS
VPP
VCMR
Cross Points
CLK
GND
GND
-1.65V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
VDDO
VDDO
2
VDDO
VDDO
2
Qx
2
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
QFB
2
➤
➤
tcycle n
tcycle n+1
➤
➤
VDDO
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Qy
2
tsk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nCLK
CLK
VDD
2
CLK0,
CLK1
VDD
VDD
2
2
EXT_FB
EXT_FB
➤
➤
t(Ø)
➤
➤
t(Ø)
t(Ø) mean = Static Phase Offset
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET (LVCMOS)
STATIC PHASE OFFSET (DIFFERENTIAL)
VDDO
2
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
2V
2V
Pulse Width
tPERIOD
0.8V
0.8V
QFB
Clock
tR
tF
Outputs
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/ PULSE WIDTH PERIOD
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
USING THE OUTPUT FREEZE CIRCUITRY
OVERVIEW
To enable low power states within a system, each output of edge of the FRZ_CLK signal. To place an output in the freeze
ICS87973I-147 (Except QC0 and QFB) can be individually fro- state, a logic “0” must be written to the respective freeze enable
zen (stopped in the logic “0” state) using a simple serial inter- bit in the shift register.To unfreeze an output, a logic “1” must be
face to a 12 bit shift register. A serial interface was chosen to written to the respective freeze enable bit. Outputs will not be-
eliminate the need for each output to have its own Output En- come enabled/disabled until all 12 data bits are shifted into the
able pin, which would dramatically increase pin count and pack- shift register.When all 12 data bits are shifted in the register, the
age cost. Common sources in a system that can be used to next rising edge of FRZ_CLK will enable or disable the outputs.
drive the ICS87973I-147 serial interface are FPGA’s and ASICs. If the bit that is following the 12th bit in the register is a logic “0”,
it is used for the start bit of the next cycle;otherwise, the device
PROTOCOL
will wait and won’t start the next cycle until it sees a logic “0” bit.
The Serial interface consists of two pins, FRZ_Data (Freeze Freezing and unfreezing of the output clock is synchronous (see
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which the timing diagram below).When going into a frozen state, the
can be frozen has its own freeze enable bit in the 12 bit shift output clock will go LOW at the time it would normally go LOW,
register.The sequence is started by supplying a logic “0” start and the freeze logic will keep the output low until unfrozen. Like-
bit followed by 12NRZ freeze enable bits. The period of each wise, when coming out of the frozen state, the output will go
FRZ_DATA bit equals the period of the FRZ_CLK signal. The HIGH only when it would normally go HIGH. This logic, there-
FRZ_DATA serial transmission should be timed so the fore, prevents runt pulses when going into and out of the frozen
ICS87973I-147 can sample each FRZ_DATA bit with the rising state.
FRZ_DATA
QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC
FRZ_CLK
FIGURE 2A. FREEZE DATA INPUT PROTOCOL
Qx FREEZE Internal
Qx Internal
Qx Out
FIGURE 2B. OUTPUT DISABLE TIMING
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS87973I-147 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 3 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10 µF
FIGURE 3. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87973DYI-147
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REV. A AUGUST 26, 2003
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 5A to 5D show inter- For example in Figure 5A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers.If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
87973DYI-147
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REV. A AUGUST 26, 2003
12
ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
SCHEMATIC EXAMPLE
Figure 6 shows a schematic example of using ICS87973I-147. logic control input pull up/down and power supply filtering. In
This example shows general design of input, output termination, this example, the clock input is driven by an LVCMOS driver.
R1
43
Zo = 50
VDD
U1
VDD
R9
1K
Serial Clcok
R8
1K
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
GNDI
GNDO
QB0
VDDO
QB1
GNDO
QB2
VDDO
QB3
EXT_FB
GNDO
QFB
VDD
FSEL_FB0
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2
PLL_SEL
REF_SEL
CLK_SEL
CLK0
CLK1
CLK
nCLK
VDDA
R10 1K
Zo = 50
Serial Data
RS
VDD
LVCMOS CLOCK
R7
VDD
10 - 15
C16
10u
R5
1K
R6
1K
C11
0.01u
ICS87973I-147
R2
43
Zo = 50
Logic Input Pin Examples
Set Logic
R4
1K
Set Logic
Input to
'0'
VDD
VDD
Input to
'1'
RU1
1K
RU2
Not Install
R3
43
Zo = 50
To Logic
Input
pins
To Logic
Input
pins
(U1-17)
C3
(U1-22)
(U1-28)
(U1-33)
(U1-37)
(U1-45)
(U1-49)
VDD
RD1
RD2
1K
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
VDD=3.3V
Not Install
0.1uF
FIGURE 6. ICS87973I-147 SCHEMATIC EXAMPLE
87973DYI-147
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REV. A AUGUST 26, 2003
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
47.1°C/W
36.4°C/W
500
42.0°C/W
34.0°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
58.0°C/W
42.3°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87973I-147 is: 8364
87973DYI-147
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REV. A AUGUST 26, 2003
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ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
52
--
--
1.60
0.15
1.45
0.38
0.20
A1
A2
b
0.05
1.35
0.22
0.09
--
1.40
0.32
c
--
D
12.00 BASIC
10.00 BASIC
12.00 BASIC
10.00 BASIC
0.65 BASIC
--
D1
E
E1
e
L
0.45
0.75
θ
--
0
°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
87973DYI-147
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REV. A AUGUST 26, 2003
15
ICS87973I-147
LOW SKEW, 1-TO-12
LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS87973DYI-147
ICS87973DYI-147T
Marking
Package
52 Lead LQFP
Count
160 per tray
500
Temperature
-40°C to 85°C
-40°C to 85°C
ICS7973DI147
ICS7973DI147
52 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
87973DYI-147
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REV. A AUGUST 26, 2003
16
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