ICS889831AKT [ICSI]
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER; 低偏移， 1到4路差分LVPECL至LVPECL / ECL扇出缓冲器
| 型号： | ICS889831AKT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER |
| 文件： | 总18页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS889831 is a high speed 1-to-4 Differential- • 4 differential LVPECL/ECL outputs
ICS
to-LVPECL/ECL Fanout Buffer and is a member
• IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
HiPerClockS™
of the HiPerClockS™family of high performance
clock solutions from ICS. The ICS889831 is
optimized for high speed and very low output
• 50Ω internal input termination toVT
• Maximum output frequency: > 2.1GHz
• Output skew: 30ps (maximum)
skew, making it suitable for use in demanding applications
such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre
Channel. The internally terminated differential input and
VREF_AC pin allow other differential signal families such as
LVDS, LVHSTL and CML to be easily interfaced to the input
with minimal use of external components.The device also has
an output enable pin which may be useful for system test
and debug purposes.The ICS889831 is packaged in a small
3mm x 3mm 16-pin VFQFN package which makes it ideal
for use in space-constrained applications.
• Part-to-part skew: 185ps (maximum)
• Additive phase jitter, RMS: 0.27ps (typical)
• Propagation delay: 570ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.5V 5ꢀ, 3.3V 5ꢀ, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.3V 5ꢀ, 2.5V 5ꢀ
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
16 15 14 13
EN
D
Q0
Q1
nQ1
Q2
1
2
3
4
12 IN
Q
nQ0
11 VT
LE
10 VREF_AC
Q1
50Ω
50Ω
IN
VT
nIN
nQ2
9
nIN
nQ1
5
6
7
8
Q2
nQ2
ICS889831
16-LeadVFQFN
VREF_AC
Q3
3mm x 3mm x 0.95 package body
K Package
nQ3
TopView
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REV. A JUNE 16, 2005
1
ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
VCC
Type
Description
Output
Output
Output
Power
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Positive supply pins.
3, 4
5, 6
7, 14
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ
outputs will go HIGH on the next LOW transition at IN inputs. Input
8
EN
Input
Pullup
threshold is VCC/2V. Includes a 37kΩ pull-up resistor. Default state is
HIGH when left floating. The internal latch is clocked on the falling edge
of the input signal IN. LVTTL / LVCMOS interface levels.
9
10
nIN
VREF_AC
VT
Input
Output
Input
Inverting differential clock input. 50Ω internal input termination to VT.
Reference voltage for AC-coupled applications.
Termination input.
11
12
IN
Input
Non-inverting differential clock input. 50Ω internal input termination to VT.
Negative supply pin.
13
VEE
Power
Output
15, 16
Q0, nQ0
Differential output pair. LVPECL / ECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLUP
Input Pullup Resistor
37
kΩ
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Input
EN
0
Outputs
Q0:Q3
Disabled; LOW
Enabled
nQ0:nQ3
Disabled; HIGH
Enabled
1
After EN switches, the clock outputs are disabled or enabled
following a falling input clock edge as shown in Figure 1.
EN
VCC/2
VCC/2
tS
tH
nIN
IN
VIN
tPD
→
←
nQx
Qx
VOUT Swing
FIGURE 1. EN TIMING DIAGRAM
TABLE 3B. TRUTH TABLE
Inputs
Outputs
IN
0
nIN
1
EN
1
Q0:Q3
nQ0:nQ3
0
1
1
0
1
1
0
X
X
0
0(1)
1(1)
NOTE 1: On next negative transition of the input signal (IN).
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REV. A JUNE 16, 2005
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-4.6V (ECL mode, VCC = 0)
-0.5V toVCC + 0.5 V
Negative SupplyVoltage, VEE
Inputs,VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Input Current, IN, nIN
VT Current, IVT
50mA
100mA
0.5mA
Input Sink/Source, IREF_AC
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature, TSTG -65°C to 150°C
PackageThermal Impedance, θJA 51.5°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, 3.3V 5ꢀ; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
3.465
60
V
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, 3.3V 5ꢀ; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
0
VCC + 0.3
V
V
Input Low Voltage
Input High Current
Input Low Current
0.8
5
VCC = VIN = 3.465V
µA
µA
IIL
VCC = 3.465V, VIN = 0V
-150
TABLE 4C. DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, 3.3V 5ꢀ; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
RIN
Differential Input Resistance (IN, nIN)
IN-to-VT
40
1.2
0
50
60
VCC
Ω
V
VIH
Input High Voltage
Input Low Voltage
Input Voltage Swing
Reference Voltage
(IN, nIN)
(IN, nIN)
VIL
VIH - 0.15
2.8
V
VIN
0.15
V
VREF_AC
VDIFF_IN
IIN
VCC - 1.42 VCC - 1.37 VCC - 1.32
V
Differential Input Voltage Swing
Input Current; NOTE 1 (IN, nIN)
0.3
3.4
35
V
mA
NOTE 1: Guaranteed by design.
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REV. A JUNE 16, 2005
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.465V; VEE = 0V
Symbol Parameter Conditions
Minimum
Typical
Maximum Units
VOH
VOL
Output High Voltage; NOTE 1
VCC - 1.125 VCC - 1.005 VCC - 0.935
V
V
V
V
Output Low Voltage; NOTE 1
Output Voltage Swing
VCC - 1.895 VCC - 1.78
VCC - 1.67
1.0
VOUT
0.6
1.2
VDIFF_OUT Differential Output Voltage Swing
2.0
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.3V 5ꢀ, -2.5V 5ꢀ OR VCC = 2.5 5ꢀ, 3.3V 5ꢀ; VEE = 0V
Symbol Parameter
fMAX Maximum Output Frequency
Condition
Minimum Typical Maximum Units
Output Swing ≥ 450mV
Input Swing: 100mV
Input Swing: 800mV
2.1
300
255
GHz
ps
435
370
570
485
30
Propagation Delay; (Differential);
NOTE 1
tPD
ps
tsk(o)
Output Skew; NOTE 2, 4
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
185
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
155.52MHz, Integration
Range: 12kHz - 20MHz
tjit
0.27
ps
tR/tF
tS
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
300
300
250
ps
ps
ps
Clock Enable Setup Time EN to IN, nIN
tH
Clock Enable Hold Time
EN to IN, nIN
All parameters characterized at ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A JUNE 16, 2005
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz)
= 0.27ps typical
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
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REV. A JUNE 16, 2005
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nIN
VIN
VIH
LVPECL
Cross Points
IN
nQx
VEE
VIL
VEE
-0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nIN
IN
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
Clock
20ꢀ
nQ0:nQ3
Outputs
tR
Q0:Q3
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nIN
IN
VIN, VOUT
VDIFF_IN, VDIFF_OUT
800mV
(typical)
1600mV
(typical)
tHOLD
EN
tSET-UP
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
SETUP & HOLD TIME
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
2.5V LVPECL INPUT WITH BUILT-IN 50Ω TERMINATION INTERFACES
The IN /nIN with built-in 50Ω terminations accepts LVDS,
LVPECL, LVHSTL, CML, SSTL and other differential signals.
Both VOUT and VOH must meet the VPP and VCMR input
requirements.Figures 4A to 4D show interface examples for the
by the most common driver types. The input interfaces sug-
gested here are examples only.If the driver is from another ven-
dor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termi-
HiPerClockS IN/nIN input with built-in 50Ω terminations driven nation requirements.
2.5V
2.5V
3.3V or 2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
Built-In
50 Ohm
2.5V LVPECL
LVDS
R1
18
Built-In
50 Ohm
FIGURE 4A. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 4B. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER
BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER
2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
VT
Zo = 50 Ohm
Zo = 50 Ohm
nIN
nIN
Receiver
Receiver
With
With
CML - Built-in 50 Ohm Pull-up
CML - Open Collector
Built-In
Built-In
50 Ohm
50 Ohm
FIGURE 4C. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 4D. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN OPEN COLLECTOR
CML DRIVER
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH BUILT-IN 50Ω PULLUP
2.5V
2.5V
Zo = 50 Ohm
R1
R2
25
IN
VT
Zo = 50 Ohm
nIN
25
Receiver With Built-In 50Ω
SSTL
FIGURE 4E. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
3.3V LVPECL INPUT WITH BUILT-IN 50Ω TERMINATION INTERFACES
The IN /nIN with built-in 50Ω terminations accepts LVDS,
LVPECL, LVHSTL, CML, SSTL and other differential signals.
Both VOUT and VOH must meet the VPP and VCMR input require-
ments. Figures 5A to 5E show interface examples for the
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another ven-
dor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termi-
HiPerClockS IN/nIN input with built-in 50Ω terminations driven nation requirements.
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
nIN
VT
nIN
Receiver
With
Receiver
With
Built-In
50 Ohm
LVPECL
LVDS
R1
50
Built-In
50 Ohm
FIGURE 5A. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 5B. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER
BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
IN
IN
VT
VT
Zo = 50 Ohm
Zo = 50 Ohm
nIN
nIN
Receiver
Receiver
With
With
CML- Built-in 50 Ohm Pull-Up
CML- Open Collector
Built-In
Built-In
50 Ohm
50 Ohm
FIGURE 5D. HIPERCLOCKS IN/nIN INPUT WITH
FIGURE 5C. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH BUILT-IN 50Ω PULLUP
BUILT-IN 50Ω DRIVEN BY A CML DRIVER
WITH OPEN COLLECTOR
3.3V
3.3V
R1
25
Zo = 50 Ohm
Zo = 50 Ohm
IN
VT
nIN
Receiver
With
SSTL
R2
25
Built-In
50 Ohm
FIGURE 5E. HIPERCLOCKS IN/nIN INPUT WITH
BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
3.3V DIFFERENTIAL INPUT WITH BUILT-IN 50Ω TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and compliment of the
unused input as shown in Figure 6.
3.3V
3.3V
R1
1K
IN
VT
nIN
Receiver
with
Built-In
50 Ohm
R2
1K
FIGURE 6. UNUSED INPUT HANDLING
2.5V DIFFERENTIAL INPUT WITH BUILT-IN 50Ω TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to
have pullup and pulldown connect to true and compliment of the
unused input as shown in Figure 7.
2.5V
2.5V
R1
680
IN
VT
nIN
Receiver
with
Built-In
50 Ohm
R2
680
FIGURE 7. UNUSED INPUT HANDLING
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
SCHEMATIC EXAMPLE
Figure 8 shows a schematic example of the ICS889831. This 2.5V LVPECL driver with AC couple. The ICS889831 outputs
are LVPECL driver. In this example, we assume the traces are
long transmission line and the receiver is high input impedance
without built-in matched load.An example of 3.3V LVPECL ter-
schematic provides examples of input and output handling.The
ICS889831 input has built-in 50Ω termination resistors.The in-
put can directly accept various types of differential signal with-
out AC couple. For AC couple termination, the ICS889831 also mination is shown in this schematic. Additional termination ap-
provides the VREF_AC pin for proper offset level after the AC proaches are shown in the LVPECLTermination Application Note.
couple. This example shows the ICS889831 input driven by a
3.3V
3.3V
C2
R3
133
R5
133
3.3V
Zo = 50
Zo = 50
0.1u
-
U1
ICS889831
+
2.5V
C5
Zo = 50
Zo = 50
9
10
11
12
4
3
2
1
R4
82.5
R6
82.5
nIN
VREF_AC
VT
IN
nQ2
Q2
nQ1
Q1
LVPECL
C6
3.3V
R1
100
R2
100
3.3V
R7
R9
Zo = 50
Zo = 50
133
133
-
3.3V
+
C1
0.1u
R8
82.5
R10
82.5
FIGURE 8. ICS889831 APPLICATION SCHEMATIC EXAMPLE
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS839831.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS889831 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 60mA = 217.8mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.94mW = 123.8mW
•
Power Dissipation at built-in terminations:Assume the input is driven by a 3.3V SSTL driver as shown in Figure 5E
and estimated approximately 1.75V drop across IN and nIN.
Total Power Dissipation for the two 50Ω built-in terminations is: (1.75V)2 / (50Ω + 50Ω) = 30.6mW
Total Power_MAX (3.63V, with all outputs switching) = 217.8mW + 123.8mW + 30.6mW = 372.2mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θ
JA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.372W * 51.5°C/W = 104°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 16-PIN VFQFN, FORCED CONVECTION
θJAvs. 0Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 9.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 9. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.935V
CC_MAX
OH_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CC_MAX
)
= 1.67V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θJA vs. 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS889831 is: 234
Pin compatible with SY89831U
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
16
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
4
4
3.0
D2
E
0.25
1.25
3.0
E2
L
0.25
0.30
1.25
0.50
Reference Document: JEDEC Publication 95, MO-220
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ICS889831
LOW SKEW, 1-TO-4
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS889831AK
Marking
831A
831A
TBD
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
16 Lead VFQFN
ICS889831AKT
ICS889831AKLF
ICS889831AKLFT
16 Lead VFQFN
3500 tape & reel
tube
16 Lead "Lead-Free" VFQFN
16 Lead "Lead-Free" VFQFN
TBD
3500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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