ICS9112M-06 [ICSI]
Low Skew Output Buffer; 低偏移的输出缓冲器
| 型号： | ICS9112M-06 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Skew Output Buffer |
| 文件： | 总8页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9112-06/07
Low Skew Output Buffer
General Description
Features
The ICS9112 is a high performance, low skew, low jitter clock
driver. It uses a phase lock loop (PLL) technology to align, in
both phase and frequency, the REF input with the CLKOUT
signal. It is designed to distribute high speed clocks in PC
systems operating at speeds from 25 to
•
•
•
•
•
•
•
Zero input - output delay
Frequency range 25 - 75 MHz (3.3V), 30-90MHz (5.0V)
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 or 16 pin versions, 150 mil SOIC packages
3.3V ±10%, 5.0V±10% operation
75 MHz (30 to 90mHz for 5V operation).
ICS9112 is a zero delay buffer that provides synchronization
between the input and output. The synchronization is
established via CLKOUT feed back to the input of the PLL.
Since the skew between the input and output is less than +/-
350 pS, the part acts as a zero delay buffer.
Pin Configuration
The ICS9112 comes in with two different options; dash 06
and dash 07. The dash 07 is available in a 16 pin 150 mil SOIC
package. It has two banks of four outputs controlled by two
address lines. Depending on the selected address line, bank B
or both banks can be put in a tri-state mode. In this mode, the
PLL is still running and only the output buffers are put in a
high impedance mode. The test mode shuts off the PLL and
connects the input directly to the output buffers (see table
below for functionality).
The dash 06 is an eight pin 150 mil SOIC package. It has five
output clocks. In the absence of REF input, both ICS9112-06
and -07 will be in the power down mode. In this mode, the
PLLis turned off and the output buffers are pulled low. Power
down mode provides the lowest power consumption for a
standby condition.
16 pin SOIC
Block Diagram
8 pin SOIC
Functionality (-07)
CLKA CLKB
Output
Source
PLL
Shutdown
FS2 FS1
CLKOUT
(1, 4)
(1, 4)
0
0
0
1
Tristate Tristate
Driven Tristate
Driven
Driven
PLL
PLL
N
N
Test
Mode
Test
Mode
Test
Mode
1
1
0
1
REF
PLL
Y
N
Driven Driven
Driven
9112-069112-07RevH1/22/99
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all device
data to verify that any information being relied upon by the customer is current and accurate.
ICS9112-06/07
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
IN
DESCRIPTION
Input reference frequency. 5V tolerant input
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
1
2
REF2
CLKA23
CLKA13
VDD
OUT
OUT
PWR
PWR
OUT
OUT
IN
3
4, 13
5, 12
6
GND
Ground
CLKB13
CLKB23
FS24
Buffered clock output. Bank B
Buffered clock output. Bank B
Select input, bit 2
7
8
9
FS14
IN
Select input, bit 1
10
11
14
15
16
CLKB33
CLKB43
CLKA23
CLKA33
CLKOUT3
OUT
OUT
OUT
OUT
OUT
Buffered clock output. Bank B
Buffered clock output. Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output, internal feedback on this pin
PIN NUMBER
PIN NAME
REF2
TYPE
DESCRIPTION
Input reference frequency. 5V tolarant input
Buffered clock output
1
2
3
4
5
6
7
IN
CLK23
CLK33
GND
OUT
OUT
PWR
OUT
PWR
OUT
Buffered clock output
Ground
CLK33
Buffered clock output
VDD
3.3v Supply
CLK43
Buffered clock output
CLK6
8
OUT
Buffered clock output. Internal feedback on this pin
(CLKOUT)3
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. Weak pull-down
3. Weak pull-down on all outputs
4. Weak pull-ups on these inputs
PB
ICS9112-06/07
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7 V, TA = 0 –70°C unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage1
Output High Voltage1
SYMBOL
VIL
TEST CONDITIONS
MIN
2.0
TYP
MAX
0.8
UNITS
V
VIH
IIL
V
VIN=0V
19
0.10
0.25
2.9
50.0
100.0
0.4
µA
µA
V
IIH
VIN=VDD
IOL = 8mA
IOH = 8mA
VOL
VOH
IDD
2.4
V
Power Down Supply
Current
REF = 0 MHz
37.0
16.0
75.0
40.0
µA
IDD
Unloaded oututs at 66.66 MHz SEL
inputs at VDD or GND
Supply Current
mA
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
3
ICS9112-06/07
Switching Characteristics (3.3V Continued)
PARAMETER
Output period
SYMBOL
t1
CONDITION
With CL=30pF
MIN
TYP
MAX
UNITS
40.00
(25)
20.00
(50)
ns
(MHz)
40.00
(25)
13.33
(75)
ns
(MHz)
Output period
Duty Cycle1
Rise Time1
t1
Dt1
tr1
With CL=20pF
Measured at 1.4V; CL=30pF
40.0
49.1
1.70
60.0
2.50
%
ns
Measured between 0.8V and 2.0V:
CL=30pF
Measured between 0.8V and 2.0V:
CL=20pF
Rise Time1
Fall Time1
Fall Time1
tr2
tf1
tf2
1.4
1.50
1.3
2.0
2.50
2.0
ns
ns
ns
Measured between 2.0V and 0.8V;
CL=30pF
Measured between 2.0V and 0.8V;
CL=20pF
Delay, REF Rising
Edge to CLKOUT
Rising Edge1, 2
Dr1
Measured at VDD/2
0
±350
ps
Output to Output
Skew1
Tskew
Tdsk-Tdsk
Tcyc-Tcyc
tLOCK
Tjabs
All outputs equally loaded, CL=20pF
250
700
200
1.0
ps
ps
Device to Device
Skew1
Measured at VDD/2 on the CLKOUT
pins of devices
0
Measured at 66.66 MHz, loaded
outputs
Cycle to Cycle Jitter1
PLL Lock Time1
Stable power supply, valid clock
presented on REF pin
ms
ps
@ 10,000 cycles
CL=30pF F=20 - 50MHz
Jitter; Absolute Jitter1
Jitter; 1 - Sigma1
-100
70
14
100
30
@ 10,000 cycles
CL=30pF F=20 - 50MHz
Tj1s
ps
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of VDD/2
3. All parameters expected with loaded outputs
PB
ICS9112-06/07
Electrical Characteristics at 5.0V
VDD = 4.5 – 5.5 V, TA = 0 –70°C unless otherwise stated
DC Characteristics
TEST CONDITIONS
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage1
Output High Voltage1
SYMBOL
VIL
MIN
TYP
MAX
0.8
UNITS
V
VIH
2.0
V
IIL
VIN=0V
-100
-19
0.10
0.25
4.0
µA
µA
V
IIH
VIN=VDD
100.0
0.4
VOL
VOH
IOL = 10mA
IOH = 10mA
3.4
V
Power Down Supply
Current
IDD
IDD
REF = 0 MHz
48
24
150
65
µA
Unloaded oututs at 66.66 MHz SEL
inputs at VDD or GND
Supply Current
mA
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
5
ICS9112-06/07
Switching Characteristics (5.0V Continued)
PARAMETER
Output period
SYMBOL
t1
CONDITION
With CL=30pF
MIN
TYP
MAX
UNITS
60.00
(30)
20.00
(50)
ns
(MHz)
60.00
(30)
16.11
(90)
ns
(MHz)
Output period
Duty Cycle1
Rise Time1
t1
Dt1
tr1
With CL=20pF
Measured at 1.4V; CL=30pF
40.0
49.1
1.5
60
%
ns
Measured between 0.8V and 2.0V:
CL=30pF
2.3
Measured between 0.8V and 2.0V:
CL=20pF
Rise Time1
Fall Time1
Fall Time1
tr2
tf1
tf2
0.7
1.2
0.9
1.8
2.3
1.8
ns
ns
ns
Measured between 2.0V and 0.8V;
CL=30pF
Measured between 2.0V and 0.8V;
CL=20pF
Delay, REF Rising
Edge to CLKOUT
Rising Edge1, 2
Dr1
Measured at VDD/2
-400
0
+400
ps
Output to Output
Skew1
Tskew
Tdsk-Tdsk
Tcyc-Tcyc
tLOCK
Tjabs
All outputs equally loaded, CL=20pF
80
0
250
700
300
1.5
ps
ps
Device to Device
Skew1
Measured at VDD/2 on the CLKOUT
pins of devices
Measured at 66.66 MHz, loaded
outputs
Cycle to Cycle Jitter1
PLL Lock Time1
Stable power supply, valid clock
presented on REF pin
ms
ps
@ 10,000 cycles
CL=30pF F=20 - 50MHz
Jitter; Absolute Jitter1
Jitter; 1 - Sigma1
-200
80
14
100
30
@ 10,000 cycles
CL=30pF F=20 - 50MHz
Tj1s
ps
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of VDD/2
3. All parameters expected with loaded outputs
PB
ICS9112-06/07
Application Suggestion:
ICS9112 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise generated by
charging or discharging of internal or external capacitor on the power supply pins. This type of noise will cause excess jitter
to the outputs of ICS9112. Below is a recommended lay out to alleviate any addition noise. Figure below depicts only ICS9112-
07, but similar techniques could be used for dash 06. For additional information on FT. layout, please refer to our AN07. The
0.1 uF capacitors should be connected as close as possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF
capacitor to ground will enhance the power line stability.
7
ICS9112-06/07
8 pin SOIC Package
16-Pin SOIC Package
Ordering Information
ICS9112M-06
ICS9112M-07
Example:
ICS XXXX M- PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all device
data to verify that any information being relied upon by the customer is current and accurate.
PB
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