ICS9147-16 [ICSI]
Frequency Generator & Integrated Buffers for PENTIUMTM; 频率发生器和集成缓冲器对PENTIUMTM
| 型号： | ICS9147-16 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUMTM |
| 文件： | 总6页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9147-16
Frequency Generator & Integrated Buffers for PENTIUMTM
General Description
Features
Generates four processor, eight bus, four 14.31818
The ICS9147-16 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
PentiumPro. Two different reference frequency multiplying
factors are externally selectable with smooth frequency
transitions. Glitch-free Stop clock control is provided for
CPU and BUS clocks. Complete chip low current mode is
achieved with the Power Down# pin.
MHz, two 48 MHz clocks for USB support.
CPU to BUS clock skew 1 to 4ns (CPU early)
Synchronous clocks skew matched to 250ps window on
CPU and 500ps window on BUS.
Selectable multiplying ratios
Glitch free stop clock controls CPUEN and BUSEN
3.0V 3.7V supply range, 2.5V to VDD supply range for
CPU (1:4) clocks and IOAPIC clock.
48-pin SSOP package
High drive BUS outputs typically provide greater than 1 V/
ns slew rate into 30pF loads. CPU outputs typically provide
better than 1V/ns slew rate into 20 pF loads while
50±
maintaining
5% duty cycle. The REF and IOAPIC clock
outputs typically provide better than 0.5V/ns slew rates.
Separate buffer supply pins VDDL allow for nominal 3.3V
voltage or reduced voltage swing (from 2.9 to 2.5V) for
CPU (1:4) and IOAPIC outputs.
Pin Configuration
Block Diagram
48-Pin SSOP
Pentium is a trademark of Intel Corporation
9147-16 Rev A 072897P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9147-16
Functionality
REF
IOAPIC
48
(MHz)
PD#
BUSEN
CPUEN
FS1
FS0
CPU (1:4)
BUS
1
1
1
1
1
1
0
1
1
1
1
1
0
X
1
1
1
1
0
1
X
0
0
0
1
Tristate
60
Tristate
30
Tristate
14.31818
14.31818
REF
Tristate
48
1
0
66.6
33.3
48
1
1
REF/2
LOW
Running
LOW
REF/4
Running
LOW
LOW
REF/2
48
X
X
X
X
X
X
14.31818
14.31818
LOW
48
LOW
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
OUT
DESCRIPTION
1, 2, 47
3, 10, 18, 24, 30, 32,
37, 43, 44
REF1, REF2, REF3
14.318 MHz reference clock outputs.
GND
PWR
Ground.
Crystal input, has internal crystal load capacitor, and feedback resistor
from X2. Nominally 14.31818MHz.
4
X1
IN
5
X2
OUT
OUT
Crystal output, has internal crystal load capacitor
8, 9, 11, 12, 13, 14,
16, 17
BUS (1:8)
FS (0:1)
BUS clock outputs, operates synchronously at CPU/2.
26, 27
IN
Select pin for enabling CPU and BUS clock frequencies.*
Core and Buffer output clock power supply.
48 MHz clock output
7, 15, 21, 25, 34, 48 VDD3
PWR
OUT
22, 23
48M (1:2)
Device power down input, stops outputs low and shuts off crystal
oscillator and PLLs when low.*
Output enable for all CPU clocks, a logic low will Stop low all CPU
clocks.*
CPU clock output clocks, operates at VDDL supply voltage (with
IOAPIC), either nominal 3.3V VDD or reduced voltage 2.9 to 2.5V.
Output enable for all BUS clock, a logic low will stop Low all Bus
clocks.*
28
PD#
IN
IN
29
CPUEN
CPU (1:4)
BUSEN
38, 39, 41, 42
6
OUT
IN
IOAPIC clock output. (14.318 MHz), operates at VDDL supply voltage
with CPU (1:4), either nominal 3.3V VDD or reduced voltage
2.9 to 2.5V.
45
IOAPIC
OUT
Power supply for CPU and IOAPIC block buffers, operates at nominal
3.3V VDD or reduced voltage 2.9 to 2.5V.
40, 46
VDDL
N/C
PWR
-
19, 20, 31, 33, 36
No connection internally to these pins.
* Has internal pull-up to VDD3
.
2
ICS9147-16
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDDL=VDD3=3.0 3.7 V, TA = 0 70°C unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
SYMBOL
TEST CONDITIONS
MIN
-
0.7VDD
-28.0
-5.0
TYP
-
-
-10.5
-
MAX
0.2VDD
-
-
5.0
UNITS
V
V
µA
µA
VIL
VIH
IIL
VIN = 0V
VIN = VDD
IIH
VOL = 0.8V;
for BUS & REF1
(and CPU & IOAPIC at VDDL= 3.0
to 3.7V)
VOH = 2.0V;
for BUS & REF1
(and IOAPIC at VDDL = 3.0 to 3.7V)
VOH = 2.0V; for CPU @
VDDL = 3.0 to 3.7V
VOL = 0.8V; REF (2:3), 48 CLKs
VOH = 2.0V; REF (2:3), 48 CLKs
Output Low Current
IOL1
19.0
-
30.0
-
mA
IOH1a
-28.0
-45.0
-16.0
-27.0
mA
mA
Output High Current
IOH1b
IOL2
IOH2
Output Low Current
Output High Current
8.0
-
13.0
-11.0
-
mA
mA
-7.0
VOL=0.8V; for CPU at
VDDL = 2.5V
VOH = 2.0V; for CPU at
VDDL = 2.5V
VOH = 2.0V; for IOAPIC @
VDDL = 2.5V
Output Low Current
IOL3
IOH3a
IOH3b
19.0
-
30.0
-12.5
-13.0
-
mA
mA
mA
-9.5
-10.0
Output High Current
IOL = 10mA;
Output Low Voltage
Output High Voltage
for BUS & REF1
(and CPU at VDDL = 3.0 to 3.7V)
IOH = -10mA;
for BUS & REF1
-
0.22
2.8
0.4
-
V
V
VOL1
2.4
VOH1
(and CPU at VDDL = 3.0 to 3.7V)
Output Low Voltage
Output High Voltage
VOL2
VOH2
IOL = 4mA; REF (2:3), 48 CLKs
IOH = -4mA; REF (2:3), 48 CLKs
-
2.4
0.25
2.6
0.4
-
V
V
IOL = 8mA; for CPU at
VDDL = 2.5V
IOH = -8mA; for CPU at
VDDL = 2.5V
@66.6 MHz; all outputs unloaded
PD# = Low
Output Low Voltage
Output High Voltage
VOL3
VOH3
-
0.25
2.25
0.4
-
V
V
2.1
-
Supply Current
Supply Current
IDD
IDDPD
70
230
140
500
mA
µA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
ICS9147-16
Electrical Characteristics at 3.3V
VDDL=VDD3=3.0 3.7 V, TA = 0 70°C unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL
Tr1a
TEST CONDITIONS
20pF load, 0.8 to 2.0V CPU
20pF load, 2.0 to 0.8V CPU
CL=20pF, VDD=2.5V
0.8 to 2.0V CPU
MIN
-
-
TYP
0.9
0.8
MAX
1.2
1.2
UNITS
ns
Rise Time1
Fall Time1
Rise Time1
Tf1a
ns
Tr1b
Tf1b
Tr2
Tf2
Tr3
Tf3
Tr4
-
-
-
-
-
-
-
1.0
1.0
0.9
0.8
1.4
1.8
-
1.2
1.2
1.6
1.5
2.4
2.4
1.6
ns
ns
ns
ns
ns
ns
ns
CL=20pF, VDD=2.5V
2.0 to 0.8V CPU
30pF load, 0.8 to 2.0V
BUS & REF1
30pF load, 2.0 to 0.8V
BUS & REF1
20pF load, 0.8 to 2.0V
48 clock & REF (2:3)
20pF load, 2.0 to 0.8V
48 clock & REF (2:3)
20pF load, 0.8 to 2.0V , IOAPIC with
VDDL = 2.5V
Fall Time1
Rise Time1
Fall Time1
Rise Time1
Fall Time1
Rise Time1
20pF load, 2.0 to 0.8V, IOAPIC with
VDDL = 2.5V
20pF load @ VOUT=1.4V
REF (1:3) Load = 20pF REF 2, 3
Load = 47pF REF1
Fall Time1
Duty Cycle1
Duty Cycle1
Tf4
Dt1
Dt2
-
-
1.6
55
50
ns
%
%
45
40
50
45
CPU & Fixed BUS Load=20pF,
BUS; Load = 30pF
CPU & Fixed BUS Load=20pF,
BUS; Load = 30pF
REF1; Load = 47pF
Jitter, One Sigma1
Tjis1
-
50
150
250
ps
ps
Jitter, Absolute1
Tjab1
-250
-
Jitter, One Sigma1
Tjis2
Tjab2
Fi
CIN
CINX
-
-500
12.0
-
55
200
14.318
5
250
500
16.0
-
ps
ps
MHz
pF
Jitter, Absolute1
REF1; Load = 47pF
Input Frequency1
Logic Input Capacitance1
Oscillator Input Capacitance1
Logic input pins
X1, X2 pins
-
18
-
pF
From VDD=3.0V to 1st crossing of
66.6 MHz VDD supply ramp < 1 ms
CPU to CPU; Load=20pF; @1.4V
(Same VDD)
BUS to BUS; Load=20pF; @1.4V
CPU to BUS; Load=20pF; @1.4V
(CPU is early) (All at 3.3V)
CPU @ 2.5V to BUS @ 3.3V
REF @ 3.3V to IOAPIC @ 2.5V
Power-on Time1
ton
-
1.5
3.0
ms
Clock Skew1
Clock Skew1
Clock Skew1
Tsk1
Tsk2
Tsk3
-
-
150
300
3.3
250
500
4
ps
ps
ns
1
1
Tsk4
Tsk5
4
1.5
ns
ns
Clock Skew1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9147-16
Recommended PCB Layout for ICS9147-16
NOTE:
This PCB Layout is based on a 4 layer board with an internal Ground (common) and Vcc plane. Placement of
components will depend on routing of signal trace. The 0.1uf Capacitors should be placed as close as possible
to the Power pins. Placement on the backside of the board is also possible. The Ferrite Beads can be replaced
with 10-15ohm Resistors. For best results, use a Fixed Voltage Regulator between the main (board) Vcc and the
different Vdd planes.
5
ICS9147-16
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
NOM. MAX.
A
A1
A2
B
AC
.625
.630
48
C
D
See Variations
E
.292
.296
.299
e
H
h
L
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
.032
N
See Variations
5°
0°
8°
X
.085
.093
.100
Ordering Information
ICS9147F-16
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
6
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