ICS9248-64 [ICSI]
AMD-K7TM System Clock Chip; AMD- K7TM系统时钟芯片
| 型号： | ICS9248-64 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | AMD-K7TM System Clock Chip |
| 文件： | 总15页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-64
TM
AMD-K7 System Clock Chip
General Description
Features
The ICS9248-64 is a main clock synthesizer chip for AMD-
K7 based systems. This provides all clocks required for such
a system when used with a Zero Delay Buffer Chip such as
the ICS9179-06.
•
Generates the following system clocks:
- 3 differential pair open drain CPU clocks
(1.5V external
pull-up; up to 133MHz).
- 8 PCI including 1 free running (3.3V) @33.3MHz.
- 2AGP(3.3V) up to 66.6MHz.
- 2 REF(3.3V)@14.318MHz
- 1 48MHz(3.3V)
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9248-64 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process and
temperature variations.
- 24 / 48MHz(3.3V)
•
Skew characteristics:
- CPU -CPU<250ps
- CPUt - CPUc <200ps (differential pair)
- PCI – PCI: <500ps
- CPU – SDRAM_OUT: < 250ps
- CPU –AGP <500ps
•
•
•
Efficient Power Management through PD#, PCI_STOP#
and CPU_STOP#.
Spread Spectrum option for EMI reduction
(-1.0% down spread).
Block Diagram
Uses external 14.318 MHz crystal
Pin Configuration
*FS0/REF0
*FS1/REF1
GNDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDREF
GNDSD
SDRAM_OUT
VDDSD
X2
RESERVED
CPUCLKC2
CPUCLKT2
GNDCPU
CUCLKC1
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
RESERVED
VDD
GNDPCI
PCICLK_F
PCICLK0
VDDPCI
PCICLK1
PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
VDDAGP
AGP0
AGP1
GNDAGP
VDD48
GND
PCI_STOP#
CPU_STOP#
PD#
SPREAD#
TEST#
SDATA
SCLK
GND48
I2C
{
48MHz
SEL24_48#/24-48MHz
48-Pin SSOP
* Internal 120K pullup resistor on indicated inputs
AMD-K is a trademark of Advanced Micro Devices.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-64RevC03/19/01
information being relied upon by the customer is current and accurate.
ICS9248-64
Pin Descriptions
PIN NUMBER
PIN NAME
FS(0:1)
REF(0:1)
GNDREF
TYPE
IN
OUT
PWR
DESCRIPTION
Frequency Select pins, has pull-up to VDD
14.318MHz clock output
1, 2
3
Ground for REF outputs
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
4
X1
IN
5
X2
GNDPCI
OUT
PWR
6, 12
Free Running PCI output. Not affected by the PCI_STOP#
input.
7
PCICLK_F
OUT
OUT
8, 10, 11, 13,
14,16,17
9, 15
PCICLK (0:6)
PCI clock outputs. TTL compatible 3.3V
VDDPCI
VDDAGP
AGP (0:1)
GNDAGP
VDD48
PWR
PWR
OUT
PWR
PWR
OUT
Power for PCICLK outputs, nominally 3.3V
Power for AGP outputs, nominally 3.3V
AGP outputs defined as 2X PCI. These may not be stopped.
Ground for AGP clock outputs
Power for USB, FDC outputs nominally 3.3V
48MHz output
18
19, 20
21
22
23
48MHz
Selects 24 or 48MHz output for pin 24
Low = 48MHz High = 24MHz
SEL24-48#
IN
24
24-48MHz
GND48
SCLK
OUT
PWR
IN
Fixed clock out selectable through SEL24-48#
Ground for 48MHz outputs
25
26
27
Clock input for I2C
SDATA
IN
Data input for I2C
Tri State or test mode when low
(please refer to frequency table)
Enables Spread Spectrum feature when LOW. Down Spread
0.5% modulation frequency =50KHz
Powers down chip, active low. Internal PLL & all outputs are
disabled.
28
29
30
TEST#
SPREAD#
PD#
IN
IN
IN
Halts CPUCLKs. CPUCLKT(0:2) is driven LOW whereas
CPUCLKC(0:2) is driven HIGH when this pin is asserted
(Active LOW).
31
CPU_STOP#
IN
Halts PCI Bus at logic "0" level when driven low. PCICLK_F
is not affected by this pin
32
PCI_STOP#
IN
33
34
35, 44
GND
VDD
RESERVED
PWR
PWR
N/C
Isolated ground for core
Isolated power for core, nominally 3.3V
Furture CPU power rail
"True" clocks of differential pair CPU outputs. These open
drain outputs need an external 1.5V pull-up.
"Complementory" clocks of differental pair CPU output. These
open drain outputs need an external 1.5V pull_up.
Ground for CPUCLK outputs.
36, 39, 42,
37, 40, 43
CPUCLKT (0:2)
CPUCLKC(0:2)
OUT
OUT
38, 41
45
GNDCPU
VDDSD
PWR
PWR
OUT
PWR
PWR
Power for SDRAM_OUT pin. Norminally 3.3V
Reference clock for SDRAM zero delay buffer
Ground for SDRAM_OUT pins
46
47
48
SDRAM_OUT
GNDSD
VDDREF
Power for REF (0:1), X1, X2, nominally 3.3V
2
ICS9248-64
Frequency Select
CPU,
SDRAM
TEST# FS1 FS0
PCI
AGP
48MHz
REF
Comments
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Hi-Z
50.0
66.6
Hi-Z
25.0
33.3
Hi-Z
50.0
66.6
Hi-Z
48
Hi-Z
Tri-state
14.318
14.318
TCLK
14.318
14.318
14.318
14.318
48
TCLK/2 TCLK/6 TCLK/3 TCLK/4
Test mode(1)
90.0
30.0
33.3
30.0
33.3
60.0
66.6
60.0
66.6
48
48
48
48
133.3
120.0
100.0
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
3
ICS9248-64
I2C Command Bitmaps
Byte 1: Reserved for Buffer
Byte 0: Reserved for Buffer
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
(Reserved for Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
Byte 3: Reserved for Buffer
Byte 2: Reserved for Buffer
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
(Reserved for Buffer)
4
ICS9248-64
Byte 5: PCI Clock Control Register
BIT PIN# PWD DESCRIPTION
REF1 enable
Byte 4: Clock Control Register
BIT PIN# PWD
DESCRIPTION
REF0 enable
7
6
5
4
3
2
1
0
2
1
1
1
1
1
1
1
1
7
6
5
4
3
1
1
1
1
1
1
17
16
14
13
11
10
8
PCICLK6 enable
PCICLK5 enable
PCICLK4 enable
PCICLK3 enable
PCICLK2 enable
PCICLK1 enable
PCICLK0 enable
24
23
20
19
24MHz/48MHz enable
48MHz enable
AGP1 enable
AGP0 enable
CPUCLK2 enable (both of
differential pair, True" and
"Complimentary"
CPUCLK1 enable (both of
differential pair, True" and
"Complimentary"
CPUCLK0 enable (both of
differential pair, True" and
"Complimentary"
2
1
0
42, 43
39, 40
36, 37
1
1
1
Notes: A value of '1'b is enable, '0'b is disable
Notes: A value of '1'b is enable, '0'b is disable
Byte 6: SDRAM Clock & Generator Mode Control Register
Bit
Description
PWD
7
Spread Spectrum enable down spread
1
Bit
CPU
PCI
Spread Percentage
654
111
110
101
100
100
120
133
90
33.3
30
33.3
30
1% Down Spread
1% Down Spread
1% Down Spread
-0.5%Down Spread
6:4
1
011 TCLK/2 TCLK/6 1% Down Spread
010
001
000
66
50
HI-Z
33
25
HI-Z
-0.5%Down Spread
1% Down Spread
1% Down Spread
2:3
1
0
(Reserved)
1
1
1
I2C enable
SDRAM_OUT Enable
Notes: A value of '1'b is enable, '0'b is disable
5
ICS9248-64
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
CONDITIONS
MIN
2
TYP
MAX UNITS
VIH
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
IIH
VIN = VDD
0.1
2.0
µ
µ
µ
A
A
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
100
110
120
IDD3.3OP66 CL = max cap loads; Select @ 66MHz
IDD3.3OP100 CL = max cap loads; Select @ 100MHz
IDD3.3OP133 CL = max cap loads; Select @ 133MHz
PD
Operating Supply
Current
180
mA
600
16
5
Power Down
Input frequency
95
14.318
A
µ
MHz
Fi
VDD = 3.3 V;
12
27
CIN
Logic Inputs
pF
Input Capacitance1
Clk Stabilization1
CINX
TSTAB
X1 & X2 pins
36
45
3
pF
From VDD = 3.3 V to 1% target Freq.
VT = 50%
ms
ps
tCPU-SDRAM
tCPU-AGP
190
60
250
Skew1
VT = 50%
500
ps
1Guaranteed by design, not 100% tested in production.
6
ICS9248-64
Electrical Characteristics - 24_48M, REF(0:1)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
2.8
0.32
-27
22
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
2.3
2.4
4
4
ns
ns
dt5
VT = 50%
51
55
%
400
1000
ps
VT = 1.5 Volts, REF
VT = 1.5 Volts, USB, 24_48M
Jitter, Cycle-to-cycle1
tjcyc-cyc1
260
500
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
SYMBOL
ZO
CONDITIONS
VO = VX
MIN
TYP
50
MAX
UNITS
Ω
Termination to
Vpull-up(external)
Termination to
Vpull-up(external)
VOL = 0.3 V
VOH2B
Output High Voltage
1
1.2
0.4
V
VOL2B
IOL2B
tr2B
Output Low Voltage
Output Low Current
0.175
21
V
mA
ns
18
Rise Time1
VOL = 0.3 V, VOH = 1.2 V
0.85
0.9
Differential voltage-
AC1
Differential voltage-
DC1
Vpullup(external)
VDIF
VDIF
VX
Note 2
Note 2
Note 3
0.4
0.2
V
V
+ 0.6
Vpullup(external)
+ 0.6
Differential Crossover
550
45
750
1100
mV
Voltage1
Duty Cycle1
dt2B
tsk2B
tsk2B
VT = 50%
VT = 50%
VT = 50%
51
55
%
ps
ps
Skew1, CPU to CPU
100
135
250
200
Skew1, CPUT to CPUC
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = VX
110
250
ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input
level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
7
ICS9248-64
Electrical Characteristics - PCICLK(0:6)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.6
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
3.1
0.17
-54
44
VOL1
0.4
-16
V
IOH1
mA
mA
IOL1
19
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1(window)
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
1.8
1.65
51
2
2
ns
ns
%
ps
dt1
55
500
1
Tsk
VT = 50%
470
Jitter, Cycle-to-cycle1
tjcyc-cyc1
120
500
ps
VT = 1.5 Volts
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.6
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.165
-54
0.4
-12
V
IOH1
mA
mA
IOL1
12
45
44
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
1.75
1.65
51
2
2
ns
ns
%
dt1
55
Jitter, Cycle-to-cycle1
tjcyc-cyc1
120
500
ps
VT = 1.5 Volts
1Guaranteed by design, not 100% tested in production.
8
ICS9248-64
Electrical Characteristics - AGP(0:1)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH4B
VOL4B
CONDITIONS
MIN
2
TYP
3
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -18 mA
IOL = 18 mA
VOH = 2.0 V
VOL = 0.8 V
0.31
-63
30
0.4
-19
V
IOH4B
mA
mA
IOL4B
19
45
Rise Time1
Fall Time1
Duty Cycle1
Tr4B
Tf4B
Dt4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 50%
1.3
1.4
50
2
2
ns
ns
%
55
Jitter, Cycle-to-cycle1
tjcyc-cyc1
290
500
ps
VT = 1.5 Volts
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH3
CONDITIONS
MIN
2
TYP
3
MAX UNITS
V
IOH = -11 mA
IOL = 11 mA
VOH = 2.0 V
VOL = 0.8 V
VOL3
0.31
-60
30
0.4
-12
V
mA
mA
ns
IOH3
IOL3
12
45
1
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
1.7
1.9
55
2.2
2.2
55
Fall Time1
Duty Cycle1
1
Tf3
ns
1
Dt3
%
Jitter, Cycle-to-cycle1
tjcyc-cyc1
130
250
ps
VT = 1.5 Volts
1Guarenteed by design, not 100% tested in production.
9
ICS9248-64
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
10
ICS9248-64
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9248-
64 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
11
ICS9248-64
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-64 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
12
ICS9248-64
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-64. All other clocks will continue to run while the CPUCLKs clocks are
disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width
is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PCI_STOP# (High)
PD# (High)
CPUCLKT
CPUCLKC
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9248-64.
3. All other clocks continue to run undisturbed including SDRAMR.
4. PD# and PCI_STOP# are shown in a high (true) state.
13
ICS9248-64
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-64. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-64 internally. PCICLK clocks are stopped in a low state and started with a full
high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK
clock.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
PCICLK
(External)
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
14
ICS9248-64
In Millimeters
In Inches
c
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
α
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS9248yF-64
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
15
information being relied upon by the customer is current and accurate.
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