ICS9248YF-96LF-T [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9248YF-96LF-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总12页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-96
Integrated
Circuit
Systems, Inc.
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Pin Configuration
Output Features:
•
•
2- CPUs @ 2.5V, up to 166.5MHz.
9 - SDRAM @ 3.3V, up to 155MHz including
1 free running
•
•
•
•
•
•
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V,
2 - 3V66MHz @ 3.3V, 2X PCI MHz
2 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz, @3.3V selectable by I2C
1 - REF @v3.3V, 14.318MHz.
Features:
•
•
Up to 166.5MHz frequency support
Support FS0-FS3 strapping status bit for I2C read
back.
•
Support power management: Through Power down
Mode from I2C programming.
•
•
Spread spectrum for EMI control ( ± 0.25% center).
Uses external 14.318MHz crystal
48-Pin 300mil SSOP
Skew Specifications:
* These inputs have a 120K pull up to VDD.
** 60K pull-up to VDD on indicated input
1 These are double strength.
•
•
•
•
•
•
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
CPU-SDRAM<500ps
For group skew specifications, please refer to group
timing relationship table.
Block Diagram
Functionality
IOAPIC
1=PCICLK/2
(MHz)
IOAPIC
0=PCICLK
(MHz)
CPU
(MHz)
SDRAM
(MHz)
3V66
(MHz)
PCICLK
(MHz)
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.80 100.20 66.80 33.40
68.00 102.00 68.00 34.00
100.30 100.30 66.87 33.43
103.00 103.00 68.67 34.33
133.73 100.30 66.87 33.43
145.00 108.75 72.50 36.25
133.73 100.30 66.87 33.43
137.33 103.00 68.67 34.33
140.00 105.00 70.00 35.00
140.00 140.00 93.33 46.67
118.00 118.00 78.67 39.33
124.00 124.00 82.67 41.33
133.70 133.70 89.13 44.57
137.00 137.00 91.33 45.67
150.00 112.50 75.00 37.50
72.50 108.75 72.50 36.25
16.70
17.00
16.72
17.17
16.72
18.13
16.72
17.17
17.50
23.33
19.67
20.67
22.28
22.83
18.75
18.13
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
Additional frequencies selectable through I2C
programming.
0311D—04/23/04
ICS9248-96
General Description
Power Groups
ICS9248-96 is the single chip clock solution for designs
using the 810/810E style chipset. It provides all necessary
clock signals for such a system.
GNDREF, VDDREF = REF0, X1, X2
GNDPCI , VDDPCI = PCICLK [9:0]
GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F,
supply for PLL core
Spread spectrum may be enabled through I2C
programming.
GND3V66 , VDD3V66 = 3V66
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting
to board design iterations or costly shielding.The ICS9248-
96 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
GND48 , VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]
SerialprogrammingI2Cinterfaceallowschangingfunctions,
stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER
PIN NAME
FREQ_IOAPIC
REF0
TYPE
IN
DESCRIPTION
If FREQ_APIC = 0, APIC Clock = PCICLK
If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default)
14.318 MHz reference clock.
1
OUT
PWR
2, 9, 10, 18, 25,
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
Crystal input,nominally 14.318MHz.
VDD
30, 38
3
X1
X2
IN
4
5, 6, 14, 21, 29,
34, 42
OUT
Crystal output, nominally 14.318MHz.
GND
PWR
Ground pin for 3V outputs.
8, 7
3V66 [1:0]
FS0
OUT
IN
3.3V Clocks
Frequency select pin.
11
12
PCICLK0
FS1
OUT
IN
PCI clock output
Frequency select pin.
PCICLK1
OUT
PCI clock output
Logic inputs frequency select I/O/USB output,
When a "0" is latched, output frequency = 48MHz
When a "1" is latched, output frequency = 24MHz
PCI clock output
SEL24_48MHz#
PCICLK2
IN
13
OUT
OUT
20, 19, 17, 16, 15 PCICLK [7:3]
PCI clock outputs.
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms.
22
PD#
IN
SCLK
SDATA
FS3
IN
IN
Clock input of I2C input, 5V tolerant input
Data input for I2C serial input, 5V tolerant input
Frequency select pin.
23
24
IN
26
27
28
48MHz_0
48MHz_1
FS2
OUT
OUT
IN
48MHz output clocks
48MHz output clocks
Frequency select pin.
24_48MHz
OUT
24 or 48MHz output
Free running SDRAM - used for feed back to chipset, should remain
on always.
31
SDRAM_F
OUT
32, 33, 35, 36, 37,
SDRAM [7:0]
OUT
SDRAM clock outputs
39, 40, 41,
43
44, 45
46
GNDLCPU
CPUCLK [1:0]
VDDLCPU
IOAPIC
PWR
OUT
PWR
OUT
PWR
Ground pin for the CPU clocks.
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2.5V clock output
47
48
VDDLAPIC
Power pin for the IOAPIC. 2.5V
0311D—04/23/04
2
ICS9248-96
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0311D—04/23/04
3
ICS9248-96
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
FREQ_IOAPIC
(MHz)
CPUCLK SDRAM
3V66
(MHz)
PCICLK
(MHz)
Bit (2, 7:4)
Spread Precentage
(MHz)
(MHz)
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.80
68.00
100.20
102.00
100.30
103.00
100.30
108.75
100.30
103.00
105.00
140.00
118.00
124.00
133.70
137.00
112.50
108.75
112.50
83.00
66.80
68.00
66.87
68.67
66.87
72.50
66.87
68.67
70.00
93.33
78.67
82.67
89.13
91.33
75.00
72.50
75.00
27.67
73.33
80.00
83.33
69.25
70.00
76.67
96.67
66.50
100.00
66.50
103.33
111.00
76.67
66.50
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
37.50
13.83
36.67
40.00
41.67
34.63
35.00
38.33
48.33
33.25
50.00
33.25
51.67
55.50
38.33
33.25
16.70
17.00
16.72
17.17
16.72
18.13
16.72
17.17
17.50
23.33
19.67
20.67
22.28
22.83
18.75
18.13
18.75
6.92
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
37.50
13.83
36.67
40.00
41.67
34.63
35.00
38.33
48.33
33.25
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
100.30
103.00
133.73
145.00
133.73
137.33
140.00
140.00
118.00
124.00
133.70
137.00
150.00
72.50
00011
Note1
Bit 2,
Bit 7:4
75.00
83.00
110.00
120.00
125.00
69.25
110.00
120.00
125.00
103.88
105.00
115.00
145.00
99.75
18.33
20.00
20.83
17.31
17.50
19.17
24.17
16.63
25.00
16.63
25.83
27.75
19.17
16.63
70.00
76.67
145.00
66.50
150.00
99.75
150.00
99.75
50.00 +/- 0.25% Center*
33.25 +/- 0.25% Center*
155.00
166.50
153.33
133.00
155.00
166.50
115.00
99.75
51.67
55.50
38.33
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
33.25 +/- 0.25% Center*
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled ± 0.25% Center Spread
0 - Running
Bit 3
Bit 1
Bit 0
0
1
0
1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency (Bit 3 = 0).
* These frequencies with spread enabled are equal to original Intel defined frequencies with -0.5% down spread.
I2C is a trademark of Philips Corporation
0311D—04/23/04
4
ICS9248-96
Byte 1: Control Register
(1= enable, 0 = disable)
Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
SDRAM7
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
32
33
35
36
37
39
40
41
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
X
X
X
1
FS3#
FS0#
FS2#
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
-
28
27
26
-
24_48MHz, 0 = 24MHz
48MHz_1
1
48MHz_0
1
(Reserved)
31
1
SDRAM_F
Byte 3: PCI, Control Register
(1= enable, 0 = disable)
Byte 4: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
(Reserved)
BIT PIN# PWD
DESCRIPTION
PCICLK7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
8
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
17
16
15
13
12
11
1
1
1
1
1
1
1
1
3V66_1
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
7
1
3V66_0
-
X
1
FREQ_IOAPIC#
IOAPIC
47
-
X
1
FS1#
44
45
CPUCLK1
CPUCLK0
1
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved (Note)
BIT PIN# PWD
DESCRIPTION
Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
Note: Don’t write into this register.Writing into this
register can cause malfunction
1. Disable means outputs are held LOW and are
disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted
logic load of the input frequency select pin conditions.
0311D—04/23/04
5
ICS9248-96
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, then only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) on the ICS9248-
96 serve as dual signal functions to the device. During
initial power-up, they act as input pins. The logic level
(voltage) that is present on these pins at this time is read
and stored into a 5-bit internal data latch. At the end of
Power-On reset, (see AC characteristics for timing values),
the device changes the mode of operations for these pins
to an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Fig. 1
0311D—04/23/04
6
ICS9248-96
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low, all clocks need to be
driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than
3 ms. The power down latency should be as short as possible but conforming to the sequence requirements shown
below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state
of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock
cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0311D—04/23/04
7
ICS9248-96
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Group Timing Relationship Table
Group
CPU 66MHz
CPU 100MHz
CPU 133MHz
Offset Tolerance Offset Tolerance Offset Tolerance
CPU to SDRAM
CPU to 3V66
SDRAM to 3V66
3V66 to PCI
2.5ns
7.5ns
500ps
500ps
500ps
500ps
1.0ns
N/A
5.0ns
5.0ns
500ps
500ps
500ps
500ps
1.0ns
N/A
0.0ns
0.0ns
500ps
500ps
500ps
500ps
1.0ns
N/A
0.0ns
0.0ns
0.0ns
1.5-3.5ns
0.0ns
1.5-3.5ns
0.0ns
1.5-3.5ns
0.0ns
PCI to PCI
USB & DOT
Async
Async
Async
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS
V
V
VIL
VSS - 0.3
-5
IIH
VIN = VDD
5
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
Input Low Current
mA
mA
mA
mA
IIL2
-200
IDD3.3OP
IDD2.5OP
IDD3.3OP
IDD2.5OP
IDD3.3OP
IDD2.5OP
300
12
340
15
CL = Max loads; CPU @ 66 MHz; SDRAM @ 100 MHz
CL = Max loads; CPU @ 100 MHz; SDRAM @ 100 MHz
CL = Max loads; CPU @ 133 MHz; SDRAM @ 133 MHz
Operating Supply
Current
300
25
350
30
300
35
420
40
Power Down Supply
Current
IDD3.3PD CL = Max loads; VIN = VDD or GND
300
600
µ
A
Input Frequency
Input Capacitance1
Transition time1
Fi
VDD = 3.3 V
14.31818
MHz
pF
CIN
Logic Inputs
5
6
COUT
CINX
Ttrans
Ts
Output pin capacitance
X1 & X2 pins
pF
27
45
3
pF
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From VDD = 3.3 V to 1% target frequency
ms
ms
ms
Settling time1
3
Clk Stabilization1
1Guaranteed by design, not 100% tested in production.
TSTAB
3
0311D—04/23/04
8
ICS9248-96
Electrical Characteristics - CPU
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP2B
VOH2B
CONDITIONS
MIN
13.5
2
TYP
14
MAX UNITS
Output Impedance1
Output High Voltage
Output Low Voltage
VO = VDD/2
IOH = -1 mA
IOL = 1 mA
VOH = 1.0 V
45
Ω
V
V
2.5
0.2
-85
-9
VOL2B
0.4
-27
IOH
IOL
Output High Current
mA
mA
V
OH = 2.375 V
VOL = 1.2 V
OL = 0.3 V
-27
27
68
Output Low Current
V
20
30
2
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
tr
tf
0.4 V to 2.0 V
2.0 V to 0.4 V
VT = 1.25 V
VT = 1.25 V
0.5
0.5
45
1.1
1.1
50
ns
ns
%
2
dt
tsk
55
50
175
ps
VT = 1.25 V; 66 MHz < fCPU < 133 MHz
fSDRAMb= 100 MHz or 133 MHz
Spread ON or OFF
Jitter, Cycle-to-cycle1
tjcyc-cyc
200
250
ps
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP1B
VOH1
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance1
Output High Voltage
Output Low Voltage
VO = VDD/2
12
18
3.3
0.1
-136
-13
115
28
55
Ω
V
V
IOH = -1 mA
IOL = 1 mA
2.4
VOL1
0.4
-33
VOH = 1.0 V
VOH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
IOH1
IOL1
Output High Current
mA
mA
-33
30
Output Low Current
38
2
Rise Time1
Fall Time1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
1.2
1.3
53.6
37
ns
ns
%
2
Duty Cycle1
dt1
55
175
500
Skew window1
tsk1
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
ps
ps
Jitter, Cycle-to-cycle1
280
1Guaranteed by design and characterization, not 100% tested in production.
0311D—04/23/04
9
ICS9248-96
Electrical Characteristics - IOAPIC
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP2B
VOH2B
CONDITIONS
MIN
13.5
2
TYP
14
MAX UNITS
Output Impedance1
Output High Voltage
Output Low Voltage
VO = VDD/2
IOH = -1 mA
IOL = 1 mA
VOH = 1.0 V
45
0.4
-27
Ω
V
V
2.5
0.2
VOL2B
-27
27
IOH
IOL
Output High Current
mA
mA
V
OH = 2.375 V
VOL = 1.2 V
OL = 0.3 V
-9
68
Output Low Current
V
20
30
2
Rise Time1
Fall Time1
tr
tf
0.4 V to 2.0 V
2.0 V to 0.4 V
VT = 1.25 V
0.5
0.5
45
1.1
1.1
50
ns
ns
%
2
Duty Cycle1
dt
55
500
Jitter, Cycle-to-cycle1
tjcyc-cyc4B VT = 1.25 V
130
ps
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP3
VOH3
CONDITIONS
VO = VDD/2
MIN
10
TYP
MAX UNITS
Output Impedance1
Output High Voltage
Output Low Voltage
24
0.4
-46
Ω
V
V
IOH = -1 mA
IOL = 1 mA
2.4
3.3
0.01
-124
-20
105
46
VOL3
VOH = 2.0 V
VOH = 3.135 V
-54
54
IOH3
IOL3
Output High Current
mA
mA
V
OL = 1.0 V
OL = 0.4 V
Output Low Current
V
53
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
Jitter1
tr3
tf3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1
ns
ns
%
1
dt3
tsk3
53
VT = 1.5 V
98
250
250
ps
ps
tjcyc-cyc VT = 1.5 V
170
1Guaranteed by design and characterization, not 100% tested in production.
0311D—04/23/04
10
ICS9248-96
Electrical Characteristics - PCI
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP1B
VOH1
CONDITIONS
MIN
11
TYP
MAX UNITS
Output Impedance1
Output High Voltage
Output Low Voltage
VO = VDD/2
25
3.2
55
0.55
-33
Ω
V
V
IOH = -1 mA
IOL = 1 mA
2.4
VOL1
0.1
VOH = 1.0 V
VOH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
-33
30
-136
-13
115
38
IOH1
IOL1
Output High Current
mA
mA
Output Low Current
38
2
Rise Time1
Fall Time1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
1.3
ns
ns
%
1.6
2
Duty Cycle1
dt1
51.6
330
145
55
500
500
Skew window1
tsk1
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
ps
ps
Jitter, Cycle-to-cycle1
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 26)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP5
VOH5
CONDITIONS
MIN
20
TYP
22
MAX UNITS
Output Impedance1
Output High Voltage
Output Low Voltage
VO = VDD/2
IOH = -1 mA
IOL = 1 mA
60
0.4
-23
Ω
V
V
2.4
3.2
VOL5
0.1
VOH = 1.0 V
-29
29
-136
-13
115
IOH5
IOL5
Output High Current
mA
mA
VOH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
Output Low Current
27
4
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
1
1
1.2
1.2
53
ns
ns
%
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
dt5
45
55
VT = 1.5 V; 48MHz
VT = 1.5 V; REF
1Guaranteed by design and characterization, not 100% tested in production.
200
780
500
1000
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc5
0311D—04/23/04
11
ICS9248-96
300 mil SSOP
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
SYMBOL
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
SEE VARIATIONS
.395
.291
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
c
INDEX
AREA
D
E
E1
e
SEE VARIATIONS
10.03
7.40
10.68
7.60
.420
.299
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
1
22
N
a
SEE VARIATIONS
SEE VARIATIONS
α
0°
8°
0°
8°
h xx 4455°°
D
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
A
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
A1
- CC --
e
SEATING
PLANE
b
.10 ((..000044)) CC
Ordering Information
ICS9248yF-96LF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0311D—04/23/04
12
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