ICS9250-29_技术文档

Integrated

Circuit

Systems, Inc.

ICS9250-29

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Recommended Application:

Solano type chipset.

Pin Configuration

IOAPIC

VDDL

GNDL

*FS1/REF

VDDR

X1

1

2

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

GNDL

VDDL

3

4

5

6

7

8

9

CPUCLK0

CPUCLK1

GND1

SDRAM0

SDRAM1

VDD1

Output Features:

•

2 CPU (2.5V) (up to 133MHz achievable through I²C)

13 SDRAM (3.3V) (up to 133MHz achievable

X2

GNDR

VDD3

through I²C)

GND1

•

5 PCI (3.3 V) @33.3MHz

3V66-0

3V66-1

3V66-2

GND3

PCICLK0

PCICLK1

PCICLK2

VDD2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

SDRAM2

SDRAM3

SDRAM4

SDRAM5

VDD1

1 IOAPIC (2.5V) @ 33.3 MHz

3 Hublink clocks (3.3 V) @ 66.6 MHz

2 (3.3V) @ 48 MHz (Non spread spectrum)

1 REF (3.3V) @ 14.318 MHz

GND1

SDRAM6

SDRAM7

SDRAM8

SDRAM9

VDD1

GND2

PCICLK3

PCICLK4

FS0

GNDA

VDDA

Features:

•

Supports spread spectrum modulation,

0 to -0.5% down spread.

GND1

SDRAM10

SDRAM11

VDD1

•

I²C support for power management

Efficient power management scheme through PD#

Uses external 14.138 MHz crystal

Alternate frequency selections available through I²C

control.

SCLK

SDATA

GNDF

VDDF

GND1

SDRAM12

TRISTATE#/PD#**

48MHz_1

48MHz_0

56-Pin 300mil SSOP

* This input has a 50K pull-down to GND.

** This input has a 50K pull-up to VDD

Functionality

Block Diagram

CPU

MHz

SDRAM

MHz

Tristate# FS0

FS1

X1

X2

XTAL

OSC

0

1

0

1

0

1

0

1

X

0

Tristate Tristate

Test Test

REF

PLL1

Spread

Spectrum

66MHz 100MHz

100MHz 100MHz

133MHz 133MHz

133MHz 100MHz

0

/2

/3

VDDL

1

CPU66/100/133 [1:0]

2

1

3V66 [2:0]

FS(1:0)

PD#

3

Control

Logic

SDRAM [12:0]

PCICLK [4:0]

13

Power Groups

TRISTATE#

Config

Reg

/2

5

VDDA, GNDA = CPU, PLL (analog)

VDDF, GNDF = Fixed PLL, 48M (analog/digital)

VDDR, GNDR = REF, X1, X2 (analog/digital)

VDD3, GND3 = 3V66 (digital)

SDATA

SCLK

IOAPIC

VDDL

/2

48MHz [1:0]

PLL2

VDD2, GND2 = PCI (digital)

2

VDD1, GND1 = SDRAM (digital)

VDDL, GNDL = IOAPIC, CPU (digital)

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the

latest version of all device data to verify that any information being relied

upon by the customer is current and accurate.

9250-29 Rev A 02/01/01

Third party brands and names are the property of their respective owners.

ICS9250-29

General Description

The ICS9250-29 is a single chip clock solution for Solano type chipset. It provides all necessary clock signals for such

a system.

Spread spectrum may be enabled through I²C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB.

This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-29

employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and

temperature variations.

Pin Configuration

PIN NUMBER PIN NAME

TYPE

DESCRIPTION

1

IOAPIC

VDDL

GNDL

FS1

OUT 2.5V clock output running at 33.3MHz.

PWR 2.5V power supply for CPU & IOAPIC

PWR Ground for 2.5V power supply for CPU & IOAPIC

2, 55

3, 56

IN

Function Select pin. Determines CPU frequency, all output functionality

4

REF

OUT 3.3V, 14.318MHz reference clock output.

PWR 3.3V power supply

5, 9, 17, 23, 27,

33, 37, 43, 49

VDDx

X1

Crystal input, has internal load cap (33pF) and feedback

resistor from X2

6

7

IN

Crystal output, nominally 14.318MHz. Has internal load

cap (33pF)

X2

OUT

8, 13, 18, 22, 26,

32, 36, 42, 48, 52

GNDx

PWR Ground pins for 3.3V supply

12, 11, 10

21

3V66 (2:0)

FS0

OUT 3.3V Fixed 66MHz clock outputs for HUB

IN

Function Select pin. Determines CPU frequency, all output functionality.

20, 19, 16, 15, 14 PCICLK (4:0)

TRISTATE#

OUT 3.3V PCI clock outputs

At power up the TRISTATE#/PD# pin defaults to the TRISTATE#

IN

input function to enable the TRISTATE# and TEST modes. (see Shared

Pin Operation for full description).

30

Asynchronous active low input pin used to power down the device into

a low power state. The internal clocks are disabled and the VCO and

the crystal are stopped. The latency of the power down will not be

greater than 3ms.

PD#

24

25

SCLK

IN

Clock input of I²C input

SDATA

Data input for I²C serial input.

29, 28

48MHz (1:0)

OUT 3.3V Fixed 48MHz clock outputs.

31, 34, 35, 38,

39, 40, 41, 44,

45, 46, 47, 50, 51

SDRAM

[12:0]

3.3V output running 100MHz and 133MHz. All SDRAM outputs can

OUT

be turned off through I²C

2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending

on FS pins.

53, 54

CPUCLK (1:0)

OUT

2

ICS9250-29

Power Down Waveform

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the

output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

Maximum Allowed Current

Max 2.5V supply consumption

Max discrete cap loads,

Vddq2 = 2.625V

Max 3.3V supply consumption

Max discrete cap loads,

Vddq3 = 3.465V

Solano

Condition

All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND

Powerdown Mode

2mA

35mA

50mA

60mA

2mA

(PWRDWN# = 0)

Full Active 66MHz

FS(1:0) = 00

440mA

430mA

440mA

500mA

Full Active 100MHz

FS(1:0) = 01

Full Active 133MHz

FS(1:0) = 11

Full Active 133MHz

FS(1:0) = 10

Clock Enable Configuration

REF,

48MHz

PD# CPUCLK SDRAM IOAPIC

3V66

PCICLK

Osc VCOs

0

1

LOW

ON

LOW

ON

LOW

ON

LOW

ON

LOW

ON

LOW

ON

OFF

ON

OFF

ON

3

ICS9250-29

General I²C serial interface information

The information in this section assumes familiarity with I²C programming.

For more information, contact ICS for an I²C programming application note.

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2_(H)

• ICS clock will acknowledge

• Controller (host) sends a dummy command code

• ICS clock will acknowledge

• Controller (host) sends a dummy byte count

• ICS clock will acknowledge

• Controller (host) starts sending first byte (Byte 0) through byte 5

• ICS clock will acknowledge each byte one at a time.

• Controller (host) sends a Stop bit

How to Write:

Controller (Host)

ICS (Slave/Receiver)

Start Bit

Address

D2_(H)

ACK

Dummy Command Code

Dummy Byte Count

Byte 0

Note: This clock does not support Read Back. Doing a

read back will lock up the PIIX-4 system.

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Stop Bit

Notes:

1.

The ICS clock generator is a slave/receiver, I²C (SMB) component. It is only a "write" mode SMB device, no readback on

this part. Read-Back will lock up the PIIX-4 due to the Byte count of 00_H.

The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

The input is operating at 3.3V logic levels.

2.

3.

4.

5.

The data byte format is 8 bit bytes.

To simplify the clock generator I²C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been

transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The

data is loaded until a Stop sequence is issued.

6.

At power-on, all registers are set to a default condition, as shown.

4

ICS9250-29

Truth Table

Tristate FS0 FS1

CPU

SDRAM

Tristate

TCLK/2

3V66

Tristate

TCLK/3

PCI

48MHz

Tristate

TCLK/2

48 MHz

REF

IOAPIC

Tristate

TCLK/6

0

1

0

1

0

1

0

1

X

0

Tristate

TCLK/6

Tristate

TCLK

TCLK/2

66.6 MHz

100 MHz

133 MHz

100 MHz 66.6 MHz 33.3 MHz

133 MHz 66.6 MHz 33.3 MHz

100 MHz 66.6 MHz 33.3 MHz

14.318 MHz 33.3 MHz

0

1

Byte 0: Control Register

(1 = enable, 0 = disable)

Bit

Pin#

-

29

28

-

Name

(Reserved ID)

Spread Spectrum

48MHz_1

PWD

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

0

1

0

(Active / Inactive )

(1=On / 0=Off )

(Active / Inactive )

48MHz_0

(Reserved ID)

Note:

Reserved ID bits must be written with "0"

Byte 1: Control Register

(1 = enable, 0 = disable)

Bit

Pin#

40

41

44

45

46

47

50

51

Name

SDRAM7

PWD

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

(Active / Inactive )

SDRAM6

SDRAM5

SDRAM4

SDRAM3

SDRAM2

SDRAM1

SDRAM0

5

ICS9250-29

Byte 2: Control Register

(1 = enable, 0 = disable)

Bit

Pin#

12

31

34

35

38

39

15

-

Name

3V66_2 (AGP)

SDRAM12

SDRAM11

SDRAM10

SDRAM9

SDRAM8

PCICLK1

Undefined bit

PWD

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

0

(Active / Inactive )

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at

power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default

3. Undefined bits can be written with either "1" or "0"

Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)

Bit

Description

PWD

Bit 7 ICS Reserved bit (Note 2)

Bit 6 ICS Reserved bit (Note 2)

Bit 5 ICS Reserved bit (Note 2)

Bit 4 ICS Reserved bit (Note 2)

0

1

Bit 3 5% overclock mode (1 = 5% / 0= normal )

Bit 2 Undefined bit (note 3)

Bit 1 Tristate#/PWRDN# ( 1 = PWRDN# / 0 = Tristate# ) see pin description

CPUCLK SDRAM 3V66 PCICLK IOAPIC

Bit 0

FS1

FS0

MHz

100.0

133.32

100.0

133.32

MHz

66.66

MHz

33.33

MHz

33.33

0

1

0

1

0

1

0

1

0

1

0

1

0

1

66.66

100.0

133.32

66.66

0

Bit 0

Note 1

100.0

133.32

Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS1 for the appropriate CPU speed, always with

SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to 1

to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the

133MHz FSB speed as shown in this table. The CPU, 3V66, PCI and IOAPIC clocks will be glitch free during this

transition, and only SDRAM will change.

Note 2: Must be written with "0"

Note 3: Undefined bits can be written with either "1" or "0"

6

ICS9250-29

Byte 4: Reserved Register

(1 = enable, 0 = disable)

Bit

Pin#

-

20

19

16

Name

(Reserved)

PWD

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

(Active / Inactive )

(Reserved)

PCICLK4

PCICLK3

PCICLK2

Byte 5: Reserved Register

(1 = enable, 0 = disable)

Bit

Pin#

Name

(Reserved)

PWD

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

0

(Active / Inactive )

(Reserved)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at

power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default

7

ICS9250-29

Absolute Maximum Ratings

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD+0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections

of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product

reliability.

Group Timing Relationship Table¹

Group

CPU 66MHz

SDRAM 100MHz

CPU 100MHz

SDRAM 100MHz

CPU 133MHz

SDRAM 100MHz

CPU 133MHz

SDRAM 133MHz

Offset

-2.5ns

7.5ns

0.0ns

Tolerance

500ps

Offset

5.0ns

0.0ns

Tolerance

500ps

Offset

0.0ns

Tolerance

500ps

Offset

3.75ns

0.0ns

Tolerance

500ps

CPU to SDRAM

CPU to 3V66

500ps

SDRAM to 3V66

500ps

-3.75ns

500ps

3V66 to PCI

PCI to IOAPIC

USB & DOT

1.5-3.5ns

0.0ns

500ps

1ns

1.5-3.5ns

0.0ns

500ps

1ns

1.5-3.5ns

0.0ns

500ps

1ns

1.5 -3.5ns

0.0ns

500ps

1ns

Asynch

N/A

Asynch

N/A

Asynch

N/A

Asynch

N/A

Electrical Characteristics - Input/Supply/Common Output Parameters

T_A= 0 - 70C; Supply Voltage V_DD= 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)

PARAMETER

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

Operating

SYMBOL

V_IH

CONDITIONS

MIN

2

TYP

MAX UNITS

V_DD+0.3

V

V_IL

V_SS-0.3

-5

0.8

5

A

I_IH

V_IN= V_DD

µ

A

I_IL1

V_IN= 0 V; Inputs with no pull-up resistors

V_IN= 0 V; Inputs with pull-up resistors

C_L= 0 pF; Select @ 66M

-5

µ

A

I_IL2

-200

µ

I_DD3.3OP

100

600

mA

Supply Current

Power Down

A

I_DD3.3PDC_L= 0 pF; With input address to Vdd or GND

µ

Supply Current

Input frequency

Pin Inductance¹

F_i

V_DD= 3.3 V;

14.318

MHz

nH

pF

L_pin

C_IN

7

5

Logic Inputs

Input Capacitance¹

C_out

C_INX

T_trans

T_s

Out put pin capacitance

X1 & X2 pins

6

pF

13.5

22.5

3

pF

Transition Time¹

Settling Time¹

Clk Stabilization¹

To 1st crossing of target Freq.

From 1st crossing to 1% target Freq.

From V_DD= 3.3 V to 1% target Freq.

ms

3

T_STAB

3

t

_PZH,t_PZHoutput enable delay (all outputs)

1

10

Delay¹

t_PLZ,t_PZH

output disable delay (all outputs)

¹Guarenteed by design, not 100% tested in production.

8

ICS9250-29

Electrical Characteristics - CPU

T_A= 0 - 70C, V_DD=3,3V +/-5%, V_DDL= 2.5 V +/-5%; C_L= 10 - 20 pF (unless otherwise stated)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time

SYMBOL

CONDITIONS

MIN

13.5

2

TYP MAX UNITS

1

R_DSP2B

V_O= V_DD*(0.5)

I_OH= -1 mA

45

Ω

V

1

R_DSN2B

V_OH2B

V_OL2B

I_OH2B

I_OL2B

I_OL= 1 mA

0.4

-27

30

V

mA

ns

V_{OH @MIN}= 1.0V , V_{OH@ MAX}= 2.375V

V_{OL @MIN}= 1.2V , V_{OL@ MAX}= 0.3V

V_OL= 0.4 V, V_OH= 2.0 V

V_OH= 2.0 V, V_OL= 0.4 V

V_T= 1.25 V

-27

27

1

t_r2B

0.4

45

1.10

1.26

53.6

1.6

55

1

Fall Time

t_f2B

ns

1

Duty Cycle

d_t2B

%

1

Skew

t_sk2B

V_T= 1.25 V

175

250

ps

1

t_jcyc-cyc

V_T= 1.25 V

Jitter

ps

¹Guarenteed by design, not 100% tested in production.

Electrical Characteristics - 3V66

T_A= 0 - 70C; V_DD= 3.3 V +/-5%; V_DDL= 2.5 V +/-5%;C_L= 10-30 pF (unless otherwise stated)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time

SYMBOL

CONDITIONS

MIN

12

TYP MAX UNITS

1

R_DSP1

V_O= V_DD*(0.5)

I_OH= -1 mA

55

Ω

1

R_DSN1

12

55

Ω

V

V_OH1

V_OL1

I_OH1

I_OL1

2.4

I_OL= 1 mA

0.4

-33

38

2

V

mA

ns

VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33

VOL@ MIN = 1.95 V, VOL@ MAX= 0.4V

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

30

0.5

45

1

t_r1

1.46

1.47

50.2

1

Fall Time

t_f1

2

ns

1

Duty Cycle

d_t1

55

175

500

%

1

Skew

t_sk1

V_T= 1.5 V

ps

1

t_jcyc-cyc

V_T= 1.5 V

Jitter

ps

¹Guarenteed by design, not 100% tested in production.

9

ICS9250-29

Electrical Characteristics - IOAPIC

T_A= 0 - 70C;V_DD= 3.3 V +/-5%, V_DDL= 2.5 V +/-5%; C_L= 10 - 20 pF (unless otherwise stated)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time

SYMBOL

CONDITIONS

MIN

TYP MAX UNITS

1

R_DSP4B

V_O= V_DD*(0.5)

I_OH= -1 mA

9

2

30

Ω

1

R_DSN4B

30

Ω

V

V_OH4B

V_OL4B

I_OH4B

I_OL4B

I_OL= 1 mA

0.4

-27

30

V

mA

ns

V_{OH@ min}= 1.0 V, V_{OH@ MAX}= 2.375 V

V_{OL@ MIN}= 1.2 V, V_{OL@ MAX=}0.3V

V_OL= 0.4 V, V_OH= 2.0 V

V_OH= 2.0 V, V_OL= 0.4 V

V_T= 1.25 V

-27

27

1

t_r4B

0.4

45

1.09

1.22

50.2

1.6

55

1

Fall Time

t_f4B

ns

1

Duty Cycle

d_t4B

%

1

t_jcyc-cyc

V_T= 1.25 V

Jitter

500

ps

¹Guarenteed by design, not 100% tested in production.

Electrical Characteristics - SDRAM

T_A= 0 - 70C; V_DD= 3.3 V +/-5%, V_DDL= 2.5 V +/-5%, C_L= 20 - 30 pF (unless otherwise stated)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time

SYMBOL

CONDITIONS

MIN

10

TYP MAX UNITS

1

R_DSP3

V_O= V_DD*(0.5)

I_OH= -1 mA

24

Ω

1

R_DSN3

10

24

Ω

V

V_OH3

V_OL3

I_OH3

I_OL3

2.4

I_OL= 1 mA

0.4

-46

53

V

mA

ns

V_{OH @MIN}= 2.0 V, V_{OH@ MAX}=3.135 V

V_{OL@ MIN}= 1.0 V, V_{OL@ MAX}=0.4 V

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

-54

49

1

t_r3

0.4

45

1.19

1.43

54.9

1.6

55

1

Fall Time

t_f3

ns

1

Duty Cycle

d_t3

%

1

Skew

t_sk3

V_T= 1.5 V

250

ps

t_jcyc-cyc¹V_T= 1.5 V

Jitter

ps

¹Guarenteed by design, not 100% tested in production.

10

ICS9250-29

Electrical Characteristics - PCI

T_A= 0 - 70C; V_DD= 3.3 V+/-5%, V_DDL= 2.5 V+/-5%; C_L= 10-30 pF (unless otherwise stated)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

1

R_DSP1

V_O= V_DD*(0.5)

I_OH= -1 mA

12

2.4

55

Ω

V

1

R_DSN1

V_OH1

V_OL1

I_OH1

I_OL1

I_OL= 1 mA

0.4

-33

38

2

V

mA

ns

V_{OH@ MIN}= 1.0 V, V_{OH@ MAX}= 3.135 V

V_{OL@ MIN}= 1.95 V, V_{OL@ MAX}= 0.4

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

-33

30

1

t_r1

0.5

45

1.43

1.63

51.9

1

Fall Time

t_f1

2

ns

1

Duty Cycle

d_t1

55

500

%

1

Skew

t_sk1

V_T= 1.5 V

ps

1

t_jcyc-cyc

V_T= 1.5 V

Jitter

ps

¹Guarenteed by design, not 100% tested in production.

Electrical Characteristics - REF, 48MHz_0

T_A= 0 - 70C; V_DD= 3.3 V+/-5%, VDDL = 2.5 V+/-5%, C_L= 10 -20 pF (unless otherwise stated)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output LowCurrent

Rise Time

SYMBOL

CONDITIONS

MIN

20

TYP MAX UNITS

1

R_DSP5

V_O= V_DD*(0.5)

I_OH= 1 mA

60

Ω

1

R_DSN5

20

60

Ω

V

V_OH5

V_OL5

I_OH5

I_OL5

2.4

I_OL= -1 mA

0.4

-23

27

V

mA

ns

V_{OH @MIN}=1 V, V_OH@MAX= 3.135 V

V_OL@MIN=1.95 V, V_OL@MIN=0.4 V

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

-29

29

1

t_r5

1.53

1.76

53.6

4

1

Fall Time

t_f5

1

4

ns

1

Duty Cycle

d_t5

45

55

%

1

t_jcyc-cyc

V_T= 1.5 V; Fixed Clocks

V_T= 1.5 V; Ref Clocks

500

1000

ps

Jitter

1

t_jcyc-cyc

ps

¹Guarenteed by design, not 100% tested in production.

11

ICS9250-29

Electrical Characteristics - 48MHz_1

T_A= 0 - 70C; V_DD= 3.3 V +/-5%, V_DDL= 2.5 V +/-5%; C_L= 10 - 15 pF (unless otherwise stated)

PARAMETER

Output Impedance

Output High Voltage

Output Low Voltage

Output High Current

Output Low Current

Rise Time

SYMBOL

CONDITIONS

MIN

10

TYP MAX UNITS

1

R_DSP3

V_O= V_DD*(0.5)

I_OH= -1 mA

24

Ω

1

R_DSN3

10

24

Ω

V

V_OH3

V_OL3

I_OH3

I_OL3

2.4

I_OL= 1 mA

0.4

-33

38

V

mA

ns

V_{OH @MIN}= 2.0 V, V_{OH@ MAX}=3.135 V

V_{OL@ MIN}= 1.0 V, V_{OL@ MAX}=0.4 V

V_OL= 0.4 V, V_OH= 2.4 V

V_OH= 2.4 V, V_OL= 0.4 V

V_T= 1.5 V

-33

30

1

t_r3

0.5

45

0.81

0.95

53.1

2.0

55

1

Fall Time

t_f3

ns

1

Duty Cycle

d_t3

%

t_jcyc-cyc¹V_T= 1.5 V

Jitter

500

ps

¹Guarenteed by design, not 100% tested in production.

12

ICS9250-29

0ns

10ns

20ns

30ns

40ns

Cycle Repeats

CPU 66MHz

CPU 100MHz

CPU 133MHz

SDRAM 100MHz

SDRAM 133MHz

3.3V 66MHz

PCI 33MHz

IOAPIC 33MHz

REF 14.318MHz

USB 48MHz

Group Offset Waveforms

13

ICS9250-29

Shared Pin Operation -

Input/Output Pins

Figure 1 shows a means of implementing this function when

a switch or 2 pin header is used. With no jumper is installed

the pin will be pulled high. With the jumper in place the pin

will be pulled low. If programmability is not necessary, than

only a single resistor is necessary.The programming resistors

should be located close to the series termination resistor to

minimize the current loop area. It is more important to locate

the series termination resistor close to the driver than the

programming resistor.

The I/O pins designated by (input/output) on the ICS9250-29

serve as dual signal functions to the device. During initial

power-up, they act as input pins. The logic level (voltage) that

is present on these pins at this time is read and stored into a 5-

bit internal data latch. At the end of Power-On reset, (see AC

characteristics for timing values), the device changes the

mode of operations for these pins to an output function. In this

modethepinsproducethespecifiedbufferedclockstoexternal

loads.

To program (load) the internal configuration register for these

pins, a resistor is connected to either theVDD (logic 1) power

supply or the GND (logic 0) voltage potential. A 10 Kilohm

(10K) resistor is used to provide both the solid CMOS

programming voltage needed during the power-up

programming period and to provide an insignificant load on

the output clock during the subsequent operating period.

Via to

VDD

Programming

Header

2K W

Via to Gnd

Device

Pad

8.2K W

Clock trace to load

Series Term. Res.

Fig. 1

TRISTATE#/PD# pin description:

TheTRISTATE#/PD# pin provides the capability of invoking

Tristate mode during board level testing.

At power up the TRISTATE#/PD# pin defaults to the

TRISTATE# input function to enable the TRESTATE# and

TEST modes.

Approximately1.5msto3msafterpoweron, theTRISTATE#/

PD# changes to the PD# input function and the TRISTATE#

functionality is disabled (if TRISTATE# is not active).

14

ICS9250-29

SYMBOL

In Millimeters

In Inches

COMMON DIMENSIONS

MIN

MAX

2.794

0.406

0.343

0.254

MIN

.095

.008

.005

MAX

.110

.016

.0135

.010

A

A1

b

2.413

0.203

0.127

c

SEE VARIATIONS

D

E

10.033

7.391

10.668

7.595

.395

.291

.420

.299

E1

e

0.635 BASIC

0.025 BASIC

h

0.381

0.508

0.635

1.016

.015

.020

.025

.040

L

SEE VARIATIONS

N

α

0°

8°

0°

8°

VARIATIONS

D mm.

D (inch)

N

MIN

MAX

MIN

.720

MAX

.730

56

18.288

18.542

JEDEC MO-118

6/1/00

DOC# 10-0034

REV B

Ordering Information

ICS9250yF-29-T

Example:

ICS XXXX y F - PPP - T

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the

latest version of all device data to verify that any information being relied

upon by the customer is current and accurate.

15


型号：	ICS9250-29
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ 频率发生器和缓冲器集成的赛扬和PII / III⑩
文件：	总15页 (文件大小：220K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS9250-29 [ICSI]

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