ICS9250YF-29-T [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩型号: | ICS9250YF-29-T |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
文件: | 总15页 (文件大小:220K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Solano type chipset.
Pin Configuration
IOAPIC
VDDL
GNDL
*FS1/REF
VDDR
X1
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GNDL
VDDL
3
4
5
6
7
8
9
CPUCLK0
CPUCLK1
GND1
SDRAM0
SDRAM1
VDD1
Output Features:
•
•
2 CPU (2.5V) (up to 133MHz achievable through I2C)
13 SDRAM (3.3V) (up to 133MHz achievable
X2
GNDR
VDD3
through I2C)
GND1
•
•
•
•
•
5 PCI (3.3 V) @33.3MHz
3V66-0
3V66-1
3V66-2
GND3
PCICLK0
PCICLK1
PCICLK2
VDD2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD1
1 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
GND1
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDD1
GND2
PCICLK3
PCICLK4
FS0
GNDA
VDDA
Features:
•
Supports spread spectrum modulation,
0 to -0.5% down spread.
GND1
SDRAM10
SDRAM11
VDD1
•
•
•
•
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I2C
control.
SCLK
SDATA
GNDF
VDDF
GND1
SDRAM12
TRISTATE#/PD#**
48MHz_1
48MHz_0
56-Pin 300mil SSOP
* This input has a 50K pull-down to GND.
** This input has a 50K pull-up to VDD
Functionality
Block Diagram
CPU
MHz
SDRAM
MHz
Tristate# FS0
FS1
X1
X2
XTAL
OSC
0
0
1
1
1
1
0
1
0
1
0
1
X
X
0
Tristate Tristate
Test Test
REF
PLL1
Spread
Spectrum
66MHz 100MHz
100MHz 100MHz
133MHz 133MHz
133MHz 100MHz
0
/2
/3
VDDL
1
CPU66/100/133 [1:0]
2
1
3V66 [2:0]
FS(1:0)
PD#
3
Control
Logic
SDRAM [12:0]
PCICLK [4:0]
13
Power Groups
TRISTATE#
Config
Reg
/2
5
VDDA, GNDA = CPU, PLL (analog)
VDDF, GNDF = Fixed PLL, 48M (analog/digital)
VDDR, GNDR = REF, X1, X2 (analog/digital)
VDD3, GND3 = 3V66 (digital)
SDATA
SCLK
IOAPIC
VDDL
/2
48MHz [1:0]
PLL2
VDD2, GND2 = PCI (digital)
2
VDD1, GND1 = SDRAM (digital)
VDDL, GNDL = IOAPIC, CPU (digital)
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
9250-29 Rev A 02/01/01
Third party brands and names are the property of their respective owners.
ICS9250-29
General Description
The ICS9250-29 is a single chip clock solution for Solano type chipset. It provides all necessary clock signals for such
a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-29
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Pin Configuration
PIN NUMBER PIN NAME
TYPE
DESCRIPTION
1
IOAPIC
VDDL
GNDL
FS1
OUT 2.5V clock output running at 33.3MHz.
PWR 2.5V power supply for CPU & IOAPIC
PWR Ground for 2.5V power supply for CPU & IOAPIC
2, 55
3, 56
IN
Function Select pin. Determines CPU frequency, all output functionality
4
REF
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply
5, 9, 17, 23, 27,
33, 37, 43, 49
VDDx
X1
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
6
7
IN
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
X2
OUT
8, 13, 18, 22, 26,
32, 36, 42, 48, 52
GNDx
PWR Ground pins for 3.3V supply
12, 11, 10
21
3V66 (2:0)
FS0
OUT 3.3V Fixed 66MHz clock outputs for HUB
IN
Function Select pin. Determines CPU frequency, all output functionality.
20, 19, 16, 15, 14 PCICLK (4:0)
TRISTATE#
OUT 3.3V PCI clock outputs
At power up the TRISTATE#/PD# pin defaults to the TRISTATE#
IN
IN
input function to enable the TRISTATE# and TEST modes. (see Shared
Pin Operation for full description).
30
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
PD#
24
25
SCLK
IN
IN
Clock input of I2C input
SDATA
Data input for I2C serial input.
29, 28
48MHz (1:0)
OUT 3.3V Fixed 48MHz clock outputs.
31, 34, 35, 38,
39, 40, 41, 44,
45, 46, 47, 50, 51
SDRAM
[12:0]
3.3V output running 100MHz and 133MHz. All SDRAM outputs can
OUT
be turned off through I2C
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS pins.
53, 54
CPUCLK (1:0)
OUT
2
ICS9250-29
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the
output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
Max 3.3V supply consumption
Max discrete cap loads,
Vddq3 = 3.465V
Solano
Condition
All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND
Powerdown Mode
2mA
35mA
50mA
60mA
60mA
2mA
(PWRDWN# = 0)
Full Active 66MHz
FS(1:0) = 00
440mA
430mA
440mA
500mA
Full Active 100MHz
FS(1:0) = 01
Full Active 133MHz
FS(1:0) = 11
Full Active 133MHz
FS(1:0) = 10
Clock Enable Configuration
REF,
48MHz
PD# CPUCLK SDRAM IOAPIC
3V66
PCICLK
Osc VCOs
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
3
ICS9250-29
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0) through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
Dummy Byte Count
Byte 0
Note: This clock does not support Read Back. Doing a
read back will lock up the PIIX-4 system.
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C (SMB) component. It is only a "write" mode SMB device, no readback on
this part. Read-Back will lock up the PIIX-4 due to the Byte count of 00H.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
2.
3.
4.
5.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The
data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
4
ICS9250-29
Truth Table
Tristate FS0 FS1
CPU
SDRAM
Tristate
TCLK/2
3V66
Tristate
TCLK/3
PCI
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
IOAPIC
Tristate
TCLK/6
0
0
1
1
1
1
0
1
0
1
0
1
X
X
0
Tristate
Tristate
TCLK/6
Tristate
TCLK
TCLK/2
66.6 MHz
100 MHz
133 MHz
133 MHz
100 MHz 66.6 MHz 33.3 MHz
100 MHz 66.6 MHz 33.3 MHz
133 MHz 66.6 MHz 33.3 MHz
100 MHz 66.6 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
0
1
1
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
-
-
-
-
-
29
28
-
Name
(Reserved ID)
(Reserved ID)
(Reserved ID)
(Reserved ID)
Spread Spectrum
48MHz_1
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
1
1
0
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(1=On / 0=Off )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
48MHz_0
(Reserved ID)
Note:
Reserved ID bits must be written with "0"
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
40
41
44
45
46
47
50
51
Name
SDRAM7
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
5
ICS9250-29
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
12
31
34
35
38
39
15
-
Name
3V66_2 (AGP)
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
PCICLK1
Undefined bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
0
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bits can be written with either "1" or "0"
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Description
PWD
Bit 7 ICS Reserved bit (Note 2)
Bit 6 ICS Reserved bit (Note 2)
Bit 5 ICS Reserved bit (Note 2)
Bit 4 ICS Reserved bit (Note 2)
0
0
0
0
0
1
1
Bit 3 5% overclock mode (1 = 5% / 0= normal )
Bit 2 Undefined bit (note 3)
Bit 1 Tristate#/PWRDN# ( 1 = PWRDN# / 0 = Tristate# ) see pin description
CPUCLK SDRAM 3V66 PCICLK IOAPIC
Bit 0
FS1
FS0
MHz
MHz
100.0
100.0
133.32
100.0
100.0
100.0
133.32
133.32
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
66.66
100.0
133.32
133.32
66.66
0
Bit 0
Note 1
100.0
133.32
133.32
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS1 for the appropriate CPU speed, always with
SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to 1
to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the
133MHz FSB speed as shown in this table. The CPU, 3V66, PCI and IOAPIC clocks will be glitch free during this
transition, and only SDRAM will change.
Note 2: Must be written with "0"
Note 3: Undefined bits can be written with either "1" or "0"
6
ICS9250-29
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
-
-
-
-
-
20
19
16
Name
(Reserved)
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Reserved)
(Reserved)
(Reserved)
(Reserved)
PCICLK4
PCICLK3
PCICLK2
Byte 5: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
(Reserved)
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Active / Inactive )
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
7
ICS9250-29
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Group Timing Relationship Table1
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset
-2.5ns
7.5ns
0.0ns
Tolerance
500ps
Offset
5.0ns
5.0ns
0.0ns
Tolerance
500ps
Offset
0.0ns
0.0ns
0.0ns
Tolerance
500ps
Offset
3.75ns
0.0ns
Tolerance
500ps
CPU to SDRAM
CPU to 3V66
500ps
500ps
500ps
500ps
SDRAM to 3V66
500ps
500ps
500ps
-3.75ns
500ps
3V66 to PCI
PCI to IOAPIC
USB & DOT
1.5-3.5ns
0.0ns
500ps
1ns
1.5-3.5ns
0.0ns
500ps
1ns
1.5-3.5ns
0.0ns
500ps
1ns
1.5 -3.5ns
0.0ns
500ps
1ns
Asynch
N/A
Asynch
N/A
Asynch
N/A
Asynch
N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
A
IIH
VIN = VDD
µ
A
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
-5
µ
A
IIL2
-200
µ
IDD3.3OP
100
600
mA
Supply Current
Power Down
A
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
µ
Supply Current
Input frequency
Pin Inductance1
Fi
VDD = 3.3 V;
14.318
MHz
nH
pF
Lpin
CIN
7
5
Logic Inputs
Input Capacitance1
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
pF
13.5
22.5
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
ms
ms
3
TSTAB
3
t
PZH,tPZH output enable delay (all outputs)
1
1
10
10
Delay1
tPLZ,tPZH
output disable delay (all outputs)
1Guarenteed by design, not 100% tested in production.
8
ICS9250-29
Electrical Characteristics - CPU
TA = 0 - 70C, VDD=3,3V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
45
45
Ω
Ω
V
1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
IOL = 1 mA
0.4
-27
30
V
mA
mA
ns
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
-27
27
1
tr2B
0.4
0.4
45
1.10
1.26
53.6
1.6
1.6
55
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
%
1
Skew
tsk2B
VT = 1.25 V
175
250
ps
1
tjcyc-cyc
VT = 1.25 V
Jitter
ps
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%;CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
Ω
1
RDSN1
12
55
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
IOL = 1 mA
0.4
-33
38
2
V
mA
mA
ns
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
1.46
1.47
50.2
1
Fall Time
tf1
2
ns
1
Duty Cycle
dt1
55
175
500
%
1
Skew
tsk1
VT = 1.5 V
ps
1
tjcyc-cyc
VT = 1.5 V
Jitter
ps
1Guarenteed by design, not 100% tested in production.
9
ICS9250-29
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
1
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
9
9
2
30
Ω
1
RDSN4B
30
Ω
V
VOH4B
VOL4B
IOH4B
IOL4B
IOL = 1 mA
0.4
-27
30
V
mA
mA
ns
VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
VOL@ MIN = 1.2 V, VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
-27
27
1
tr4B
0.4
0.4
45
1.09
1.22
50.2
1.6
1.6
55
1
Fall Time
tf4B
ns
1
Duty Cycle
dt4B
%
1
tjcyc-cyc
VT = 1.25 V
Jitter
500
ps
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%, CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
RDSP3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
Ω
1
RDSN3
10
24
Ω
V
VOH3
VOL3
IOH3
IOL3
2.4
IOL = 1 mA
0.4
-46
53
V
mA
mA
ns
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-54
49
1
tr3
0.4
0.4
45
1.19
1.43
54.9
1.6
1.6
55
1
Fall Time
tf3
ns
1
Duty Cycle
dt3
%
1
Skew
tsk3
VT = 1.5 V
250
250
ps
tjcyc-cyc1 VT = 1.5 V
Jitter
ps
1Guarenteed by design, not 100% tested in production.
10
ICS9250-29
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
12
12
2.4
55
55
Ω
Ω
V
1
RDSN1
VOH1
VOL1
IOH1
IOL1
IOL = 1 mA
0.4
-33
38
2
V
mA
mA
ns
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
1
tr1
0.5
0.5
45
1.43
1.63
51.9
1
Fall Time
tf1
2
ns
1
Duty Cycle
dt1
55
500
500
%
1
Skew
tsk1
VT = 1.5 V
ps
1
tjcyc-cyc
VT = 1.5 V
Jitter
ps
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0
TA = 0 - 70C; VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5%, CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output LowCurrent
Rise Time
SYMBOL
CONDITIONS
MIN
20
TYP MAX UNITS
1
RDSP5
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = 1 mA
60
Ω
1
RDSN5
20
60
Ω
V
VOH5
VOL5
IOH5
IOL5
2.4
IOL = -1 mA
0.4
-23
27
V
mA
mA
ns
VOH @MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
1
1
tr5
1.53
1.76
53.6
4
1
Fall Time
tf5
1
4
ns
1
Duty Cycle
dt5
45
55
%
1
tjcyc-cyc
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
500
1000
ps
Jitter
1
tjcyc-cyc
ps
1Guarenteed by design, not 100% tested in production.
11
ICS9250-29
Electrical Characteristics - 48MHz_1
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 15 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
RDSP3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
Ω
1
RDSN3
10
24
Ω
V
VOH3
VOL3
IOH3
IOL3
2.4
IOL = 1 mA
0.4
-33
38
V
mA
mA
ns
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
1
tr3
0.5
0.5
45
0.81
0.95
53.1
2.0
2.0
55
1
Fall Time
tf3
ns
1
Duty Cycle
dt3
%
tjcyc-cyc1 VT = 1.5 V
Jitter
500
ps
1Guarenteed by design, not 100% tested in production.
12
ICS9250-29
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.3V 66MHz
PCI 33MHz
IOAPIC 33MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
13
ICS9250-29
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9250-29
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5-
bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
modethepinsproducethespecifiedbufferedclockstoexternal
loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either theVDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
TRISTATE#/PD# pin description:
TheTRISTATE#/PD# pin provides the capability of invoking
Tristate mode during board level testing.
At power up the TRISTATE#/PD# pin defaults to the
TRISTATE# input function to enable the TRESTATE# and
TEST modes.
Approximately1.5msto3msafterpoweron, theTRISTATE#/
PD# changes to the PD# input function and the TRISTATE#
functionality is disabled (if TRISTATE# is not active).
14
ICS9250-29
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.720
MAX
.730
56
18.288
18.542
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS9250yF-29-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
15
相关型号:
ICS9250YF-50-T
Processor Specific Clock Generator, 133.33MHz, PDSO56, 0.300 INCH, MO-118, SSOP-56
IDT
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