ICS932S202 [ICSI]
Frequency Timing Generator for Differential PIIIType Dual-CPU Systems; 频率时序发生器差分PIIIType双CPU系统
| 型号： | ICS932S202 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for Differential PIIIType Dual-CPU Systems |
| 文件： | 总14页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS932S202
Integrated
Circuit
Systems, Inc.
Frequency Timing Generator for Differential PIII Type
Dual-CPU Systems
RecommendedApplication:
KeySpecifications:
Serverwork HE-T, HE-SL & LE-T Chipsets
•
•
•
•
•
•
•
•
•
CPU Output Jitter: <150ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
OutputFeatures:
•
•
•
•
•
•
2 - CPUs @ 2.5V, up to 180MHz
2 - CPU chipset @ 2.5V, up to 180MHz
3 - IOAPIC @ 2.5V
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <500ps
3 - 3V66MHz @ 3.3V
11 - PCIs @ 3.3V
1 - 48MHz, @ 3.3V fixed
3V66 Output Skew <250ps
•
•
1 - 24/48MHz, @ 3.3V
2 - REF @ 3.3V
CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ =
1.3ns)
Features:
•
•
CPU to PCI Output Offset: 0.0 - 1.5ns (typ =
0.9ns)
•
•
Up to 180MHz frequency support
Support power management:Power down Mode
from I2C programming.
CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ =
2.0ns)
•
Spread spectrum for EMI control
± 0.25% center spread).
•
•
Uses external 14.318MHz crystal
5 - FS pins for frequency select
Block Diagram
Pin Configuration
GNDREF
REF0
*SEL24_48#/REF1
VDDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC0
IOAPIC1
GNDLAPIC
IOAPIC2
VDDLCPU
CPUCLK0
GNDLCPU
CPUCLK1
VDDLCPU
CPU_CSCLK0
CPU_CSCLK1
GNDLCPU
VDD66
3V66_0
3V66_1
3V66_2
GND66
SDATA
SCLK
VDD48
PLL2
48MHz
24_48MHz
/ 2
X2
GNDPCI
X1
X2
XTAL
OSC
REF (1:0)
*FS0/PCICLK0
*FS1/PCICLK1
VDDPCI
*FS2/PCICLK2
*FS3/PCICLK3
GNDPCI
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLK (1:0)
CPU_CSCLK (1:0)
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PCICLK8
PCICLK9
PCICLK10
VDDPCI
IOAPIC
DIVDER
IOAPIC (2:0)
SEL24_48#
Control
Logic
PCI
DIVDER
PCICLK (10:0)
SDATA
SCLK
FS (4:0)
PD#
Config.
Reg.
48MHz/FS4*
24_48MHz
GND48
3V66
DIVDER
3V66 (2:0)
PD#
48-pin SSOP
*120Kohmpull-uptoVDDonindicatedinputs.
0600A—08/04/03
ICS932S202
General Description
The ICS932S202 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs.This
chip provides all the clocks required for such a system.
Spread Spectrum may be enabled through I2C.Spread spectrum typically reduces system EMI by 8dB to 10dB.This
simplifies EMI qualification without resorting to board design iterations or costly shielding.The ICS932S202 employs
a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Pin Descriptions
Pin number
1, 7, 13, 19, 25,
31, 36, 41, 45
2
Pin name
Type
Description
GND
PWR
Ground pins
REF0
REF1
OUT
OUT
IN
14.318MHz reference clock outputs at 3.3V
14.318MHz reference clock outputs at 3.3V
Logic input to select 24 or 48MHz for pin 26 output
3
SEL24_48
4, 10, 16, 23,
VDD
PWR
Power pins 3.3V
28, 35
5
6
X1
IN
OUT
OUT
IN
XTAL_IN 14.318MHz crystal input
X2
XTAL_OUT Crystal output
PCICLK0
FS0
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
8
9
PCICLK1
FS1
OUT
IN
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCICLK2
FS2
OUT
IN
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
11
12
PCICLK3
FS3
OUT
IN
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
22, 21, 20, 18,
17, 15, 14
PCICLK (10:4)
OUT
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the
output clocks are held at a Low state.
24
PD#
IN
24 or 48MHz output selectable by
SEL24_48# (0=48MHz 1=24MHz)
OUT/IN Fixed 48MHz clock output. 3.3V
26
27
24_48MHz
OUT
48MHz
FS4
IN
IN
Logic - input for frequency selection
Clock input of I2C input
Data pin for I2C circuitry 5V tolerant
3.3V clock outputs. These outputs are stopped when
CPU_STOP# is driven active..
29
30
SCLK
SDATA
I/O
34, 33, 32
3V66 (2:0)
OUT
38, 37
40, 42
39, 43
44, 46, 47
48
CPU_CSCLK (1:0)
CPUCLK (1:0)
VDDLCPU
OUT
OUT
PWR
OUT
PWR
Chipset clock outputs @ 2.5V
CPU clock outputs @ 2.5V.
Power pins for CPUCLKs. 2.5V
IOAPIC (2:0)
VDDLAPIC
IOAPIC clocks @ 2.5V. Synchronous with CPUCLKs.
Power pin for the IOAPIC outputs. 2.5V.
0600A—08/04/03
2
ICS932S202
Functionality
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
103.0
100.0
100.45
100.9
107.1
109.0
112.0
114.00
116.00
118.00
133.30
120.00
122.00
125.00
50.0
PCI
3V66
68.67
66.67
66.97
67.27
71.40
72.67
74.67
57.00
58.00
59.00
66.65
60.00
61.00
62.50
33.33
33.33
66.67
66.95
69.00
71.00
73.00
75.00
76.50
78.00
79.55
81.00
83.33
84.00
85.50
87.00
88.50
90.00
IOAPIC
17.17
16.67
16.74
16.82
17.85
18.17
18.67
14.25
14.50
14.75
16.66
15.00
15.25
15.63
8.33
34.33
33.33
33.48
33.63
35.70
36.33
37.33
28.50
29.00
29.50
33.33
30.00
30.50
31.25
16.67
16.67
33.33
33.48
34.50
35.50
36.50
37.50
38.25
39.00
39.78
40.50
41.67
42.00
42.75
43.50
44.25
45.00
66.7
8.33
133.3
133.9
138.0
142.0
146.0
150.0
153.0
156.0
159.1
162.0
166.7
168.0
171.0
174.0
177.0
180.0
16.67
16.74
17.25
17.75
18.25
18.75
19.13
19.50
19.89
20.25
20.83
21.00
21.38
21.75
22.13
22.50
0600A—08/04/03
3
ICS932S202
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit
Description
PWD
Bit 2
FS4
Bit 7
FS3
Bit 6
FS2
Bit 5
FS1
Bit 4
FS0
CPU
PCI
3V66 IOAPIC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
103.0
100.0
34.33 68.67
33.33 66.67
17.17
16.67
16.74
16.82
17.85
18.17
18.67
14.25
14.50
14.75
16.66
15.00
15.25
15.63
8.33
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
100.45 33.48 66.97
100.9
107.1
109.0
112.0
33.63 67.27
35.70 71.40
36.33 72.67
37.33 74.67
114.00 28.50 57.00
116.00 29.00 58.00
118.00 29.50 59.00
133.30 33.33 66.65
120.00 30.00 60.00
122.00 30.50 61.00
125.00 31.25 62.50
50.0
66.7
16.67 33.33
16.67 33.33
33.33 66.67
33.48 66.95
34.50 69.00
35.50 71.00
36.50 73.00
37.50 75.00
38.25 76.50
39.00 78.00
39.78 79.55
40.50 81.00
41.67 83.33
42.00 84.00
42.75 85.50
43.50 87.00
44.25 88.50
Bit
(2, 7:4)
Reserved
Note 1
8.33
133.3
133.9
138.0
142.0
146.0
150.0
153.0
156.0
159.1
162.0
166.7
168.0
171.0
174.0
177.0
16.67
16.74
17.25
17.75
18.25
18.75
19.13
19.50
19.89
20.25
20.83
21.00
21.38
21.75
22.13
1
1
1
1
1
180.0
45.00 90.00
22.50
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
1
0
0 - Normal
1 - Spread spectrum enabled
0 - Running
1 - Tristate all outputs
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed byBit 3.
0600A—08/04/03
4
ICS932S202
Byte 1: CPU, Active/Inactive
Register (1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive
Register (1 = enable, 0 = disable)
Bit
Pin # PWD
Description
PCICLK7
Bit
Pin #
40
38
37
42
47
46
44
-
PWD
1
1
1
1
1
1
1
X
Description
CPUCLK 1
CPUCSCLK0
CPUCSCLK1
CPUCLK 0
IOAPIC0
IOAPIC1
IOAPIC2
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
18
17
15
14
12
11
9
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
8
Notes:
Notes:
1. InactivemeansoutputsareheldLOWandaredisabled
from switching.
1. InactivemeansoutputsareheldLOWandaredisabled
from switching.
Byte3:3V66Active/InactiveRegister
(1 = enable, 0 = disable)
Byte4:PCIActive/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin #
PWD
1
1
1
X
1
1
X
X
Description
Bit
Pin #
26
27
-
PWD
1
1
X
1
1
1
1
X
Description
24_48MHz
48MHz
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
34
33
32
-
2
3
3V66_0
3V66_1
3V66_2
FS1#
REF0
REF1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS0#
-
(Reserved)
PCICLK10
PCICLK9
PCICLK8
FS4#
22
21
20
-
-
-
FS3#
FS2#
Notes:
Notes:
1. InactivemeansoutputsareheldLOWandaredisabled
from switching.
1. Inactive means outputs are held LOW and are
disabled from switching.
Byte5: Active/InactiveRegister
(1= enable, 0 = disable)
Byte6: Active/InactiveRegister
(1= enable, 0 = disable)
Bit
Pin #
PWD
Description
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit
Pin # PWD
Description
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Note: Don’t write into this register, writing into this
Notes:
register can cause malfunction
1. InactivemeansoutputsareheldLOWandaredisabled
from switching.
0600A—08/04/03
5
ICS932S202
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
CaseTemperature . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN
2
VSS - 0.3
TYP
MAX
VDD + 0.3
0.8
UNITS
VIH
VIL
IIH
V
V
VIN = VDD
5
µA
VIN = 0V; Inputs with no pull-up
IIL1
IIL2
Input Low Current
Input Low Current
-5
µA
µA
resistors
VIN = 0V; Inputs with pull-up
-200
resistors
IDD3.3OP100 CL = 30 pF; Select @ 100 MHz
137
143
160
160
mA
mA
Operating Supply Current
IDD3.3OP133 CL = 30 pF; Select @ 133 MHz
IDD3.3PD
Fi
CL =30 pF; PWRDWN#=0
VDD = 3.3 V
Powerdown Current
Input Frequency
220
600
16
5
µA
MHz
pF
11
27
14.318
CIN
Logic Inputs
Input Capacitance1
CINX
X1 & X2 pins
To 1st crossing of target
frequency
45
pF
Transition time1
Settling Time1
Ttrans
Ts
3
3
3
ms
ms
ms
From 1st crossing to 1 % target
frequency.
From VDD = 3.3 V to 1% target
Clk Stabilization1
TSTAB
frequency
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; VDD = 3.3 V +/- 5%, VDDL = 2.5V +/- 5% (unless otherwise stated).
PARAMETER
SYMBOL
IDD2.5OP100
IDD2.5OP133
IDD2.5PD
CONDITIONS
CL = 30 pF; Select @ 100 MHz
CL = 30 pF; Select @ 133 MHz
CL = 30 pF; PWRDWN# = 0
MIN
TYP
MAX
75
UNITS
mA
34
58
3
Operating Supply Current
Power Down Supply Current
90
mA
100
mA
0600A—08/04/03
6
ICS932S202
Group Offset
Group
Offset
0.8 to 1.8ns CPU leads CPU @ 20pF, 3V66 @ 30pF
0 to 1.5ns CPU leads CPU @ 20pF, PCI @ 30pF
Measurement Loads
Measure Points
CPU @1.25V, 3V66 @ 1.5V
CPU @ 1.25V, PCI @ 1.5V
CPU to 3V66
CPU to PCI
CPU to IOAPIC 1.5 to 4.0ns CPU leads CPU @ 20pF, IOAPIC @ 20pF CPU @ 1.25V, IOAPIC @ 1.25V
Note: 1. All offsets are to be measured at rising edges.
Electrical Characteristics - CPUCLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/- 5 %; CL = 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
CONDITIONS
MIN
2
TYP
2.3
MAX UNITS
V
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.3
0.4
-19
V
mA
mA
ns
IOH2B
-35
IOL2B
19
0.4
0.4
45
26
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.73
0.76
50.6
0.9
0.9
55
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
%
Cpu0:1
VT=1.25 to 1.5V @ all frequency
-2
175
175
175
175
175
250
ps
ps
ps
ps
ps
ps
CPU0:3 VT=1.25 to 1.5V @ 66MHz
VT=1.25 to 1.5V @ 100MHz
140
165
155
70
Skew
VT=1.25 to 1.5V @ 133MHz
VT=1.25 to 1.5V @ 200MHz
VT = 1.25 V
1
tjcyc-cyc2B
Jitter, Cycle-to-cycle
108
1Guaranteed by design, not 100% tested in production.
0600A—08/04/03
7
ICS932S202
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
MIN
2.4
TYP
2.9
MAX UNITS
V
IOH = -25 mA
IOL = 20 mA
VOH = 2.0 V
VOL = 0.8 V
0.32
-73
50
0.4
-40
V
mA
mA
ns
ns
%
IOL1
41
0.5
0.5
45
Tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.31
1.39
49
2
2
Fall Time
Tf1
Duty Cycle
Dt1
55
1
Skew
Tsk1
VT = 1.5 V
VT = 1.5 V
85
250
500
ps
ps
1
tjcyc-cyc1
Jitter, Cycle-to-cycle
163
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
MIN
2.4
TYP
3.1
MAX UNITS
V
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
0.17
-62
0.4
-22
V
mA
mA
ns
ns
%
IOL1
25
0.5
0.5
45
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.42
1.54
50.8
266
133
2.5
2.5
55
Fall Time1
tf1
Duty Cycle1
dt1
tsk1
VT = 1.5 V
500
500
ps
ps
Skew
Jitter, Cycle-to-cycle1
tjcyc-cyc1
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
0600A—08/04/03
8
ICS932S202
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70°C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; CL = 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
2.9
MAX UNITS
V
IOH = -12 mA
IOL = 9 mA
VOL5
0.3
0.4
-22
V
mA
mA
ns
ns
%
IOH5
VOH = 2.0 V
VOL = 0.8 V
-27
22
IOL5
16
45
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4V, VOL = 0.4 V
VT = 1.5 V
1.9
4
4
1
Fall Time
tf5
2.10
50.9
303
1
Duty Cycle
dt5
55
500
1
tjcyc-cyc5
VT = 1.5 V
Jitter, Cycle-to-Cycle
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; CL = 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
2.9
MAX UNITS
V
IOH = -12 mA
IOL = 9 mA
VOL5
0.3
0.4
-22
V
mA
mA
ns
IOH5
VOH = 2.0 V
VOL = 0.8 V
-27
22
IOL5
16
45
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4V, VOL = 0.4 V
VT = 1.5 V
1.9
4
4
1
Fall Time
tf5
2.00
52.6
850
ns
1
Duty Cycle
dt5
55
%
1
tjcyc-cyc5
VT = 1.5 V
Jitter, Cycle-to-Cycle
1Guaranteed by design, not 100% tested in production.
1000
ps
0600A—08/04/03
9
ICS932S202
Electrical Characteristics - CPU_CSCLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/- 5 %; CL = 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
CONDITIONS
MIN
2
TYP
2.3
0.3
-35
26
MAX UNITS
V
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
ns
%
IOH2B
IOL2B
19
0.4
0.4
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.9
0.8
54
1.6
1.6
55
1
Fall Time
tf2B
1
Duty Cycle
dt2B
Cpu_CS0:1 VT=1.25 to 1.5V @ all frequency
34
175
250
ps
ps
Skew
1
tjcyc-cyc2B
VT = 1.25 V
Jitter, Cycle-to-cycle
119
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH4B
VOL4B
CONDITIONS
MIN
2
TYP
2.3
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.31
-33
27
0.4
-19
V
mA
mA
ns
IOH4B
IOL4B
19
0.5
0.5
45
1
tr4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.8
2
2
1
Fall Time
tf4B
1.8
ns
1
Duty Cycle
dt4B
49.3
95
55
%
tsk4B1
Skew
VT = 1.25 V
VT = 1.25 V
250
500
1
tjcyc-cyc4B
Jitter, Cycle-to-cycle
112
ps
1Guaranteed by design, not 100% tested in production.
0600A—08/04/03
10
ICS932S202
Power Management Features:
REF.
48MHz
PD# CPUCLK IOAPIC 3V66
PCI
LOW
ON
PCI_F
LOW
ON
Osc
OFF
ON
VCOs
OFF
ON
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Latency
Signal
Signal State
No. of rising edges
of PCICLK
1 (normal operation)
0 (power down)
3mS
PD#
2max.
Note:
1. Clockon/offlatencyisdefinedinthenumberofrisingedgesoffreerunningPCICLKsbetweentheclockdisablegoes
low/high to the first valid clock comes out of the device.
2.Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
0600A—08/04/03
11
ICS932S202
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0600A—08/04/03
12
ICS932S202
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input.This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internalclocksarenotrunningafterthedeviceisputinpowerdown.WhenPD#isactivelowallclocksneedtobedriven
to a low value and held prior to turning off the VCOs and crystal.The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the
internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle
to complete.
PD#
CPUCLK
3V66
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS932S202device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0600A—08/04/03
13
ICS932S202
300 mil SSOP
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
SYMBOL
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
SEE VARIATIONS
.395
.291
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
c
INDEX
AREA
D
E
E1
e
SEE VARIATIONS
10.03
7.40
10.68
7.60
.420
.299
0.635 BASIC
0.025 BASIC
h
L
N
a
0.38
0.50
0.64
1.02
.015
.020
.025
.040
1
2
α
h x 45°
SEE VARIATIONS
0°
SEE VARIATIONS
0°
D
8°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
MAX
A
48
15.75
16.00
.620
.630
A1
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
- CC --
e
SEATING
PLANE
b
.10 (.004)
C
Ordering Information
ICS93S202yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0600A—08/04/03
14
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