ICS932S825 [ICSI]
Low Power Clock Chip for Serverworks HT2400 Servers; 低功耗时钟芯片的ServerWorks HT2400服务器
| 型号： | ICS932S825 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Power Clock Chip for Serverworks HT2400 Servers |
| 文件： | 总20页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS932S825
Integrated
Circuit
Systems, Inc.
Low Power Clock Chip for Serverworks HT2400 Servers
Pin Configuration
RecommendedApplication:
Serverworks HT2400-based systems using AMD Opteron
processors
X1 1
X2 2
64 VDD25MHz
63 FS0/25MHz_0_2x
62 25MHz_1_2x
61 GND25MHz
60 SPREAD_EN
59 CPUK8GT_L6
58 CPUK8GC_L6
57 CPUK8GT_L5
56 CPUK8GC_L5
55 VDDCPU
VDDREF_STB 3
REF0_RUN_2x 4
FS1/REF1_2x 5
FS2/REF2_2x 6
GNDREF 7
OutputFeatures:
•
7 - Pairs of AMD Low Power K8 Greyhound
compliant clocks
•
•
•
•
•
7 - Pair of SRC/PCI Express* Gen 2 clocks
3 - 14.318 MHz REF clocks including 1 free-running
2 - 48MHz clocks
2 - PCI 33 MHz clocks
2 - 25MHz clocks
VDD48 8
48MHz_0_2x 9
48MHz_1_2x 10
GND48 11
SCLK 12
SDATA 13
VDDPCI 14
PCICLK0_2x 15
54 GND
53 CPUK8GT_L4
52 CPUK8GC_L4
51 CPUK8GT_L3
50 CPUK8GC_L3
Features:
PCICLK1_2x 16
49 CPUK8GT_L2
•
•
•
•
•
Spread Spectrum for EMI reduction
GNDPCI 17
CLKPWRGD/PD# 18
GND 19
48 CPUK8GC_L2
47 VDDCPU
46 GND
45 CPUK8GT_L1
44 CPUK8GC_L1
43 CPUK8GT_L0
42 CPUK8GC_L0
41 GND
40 PCIeT_L6
39 PCIeC_L6
38 PCIeT_L5
37 PCIeC_L5
36 VDDPCIe
35 GND
Outputs may be disabled via SMBus
M/N programming via SMBus
PCIe clocks meet PCIe Gen 2.
Low Power differential outputs
VDDA 20
GNDA 21
GND 22
PCIeT_L0 23
PCIeC_L0 24
PCIeT_L1 25
PCIeC_L1 26
GND 27
VDDPCIe 28
PCIeT_L2 29
PCIeC_L2 30
PCIeT_L3 31
PCIeC_L3 32
Functionality
FS2 FS1 FS0
CPU
(MHz)
Hi-Z
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X/6
180.00
220.00
100.00
133.33
Reserved
200.00
34 PCIeT_L4
33 PCIeC_L4
64-TSSOP
Power Groups
Pin Number
Description
VDD
8
64
GND
11
61
48MHz Clocks
25MHz Clocks
14
20
17
21
33 MHz PCI Clocks
Analog Core
36, 28
55, 47
3
35, 27
54, 46
7
PCIe clocks
K8G CPU Clocks
REF Clocks, Xtal Osc.
1276D—10/25/07
*Other names and brands may be claimed as the property of others.
ICS932S825
Pin Description
PIN #
PIN NAME
TYPE
IN
DESCRIPTION
Crystal input, Nominally 14.318MHz.
1
2
3
X1
X2
OUT
PWR
Crystal output, Nominally 14.318MHz
VDDREF_STB
Ref, XTAL power supply, nominal 3.3V standby power
14.318MHz Free Running XTAL Output. This output runs as long as
standby VDD is applied to the part. Default drive is 2 loads.
Frequency select latch input pin / 14.318 MHz reference clock. Default 2
load drive.
4
5
6
REF0_RUN_2x
FS1/REF1_2x
FS2/REF2_2x
OUT
I/O
Frequency select latch input pin / 14.318 MHz reference clock. Default 2
load drive.
I/O
7
GNDREF
VDD48
PWR
PWR
OUT
OUT
PWR
IN
Ground pin for the REF outputs.
8
Power pin for the 48MHz output.3.3V
9
48MHz_0_2x
48MHz_1_2x
GND48
48MHz clock output. Default 2 load drive strength
48MHz clock output. Default 2 load drive strength
Ground pin for the 48MHz outputs
10
11
12
13
14
15
16
17
SCLK
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Power supply for PCI clocks, nominal 3.3V
3.3V PCI clock output. Default 2 load drive strength.
3.3V PCI clock output. Default 2 load drive strength.
SDATA
I/O
VDDPCI
PWR
OUT
OUT
PWR
PCICLK0_2x
PCICLK1_2x
GNDPCI
Ground pin for the PCI outputs
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active high
input. / Asynchronous active low input pin used to power down the device
into a low power state.
18
CLKPWRGD/PD#
IN
19
20
21
22
GND
PWR
PWR
PWR
PWR
Ground pin.
VDDA
GNDA
GND
3.3V power for the PLL core.
Ground pin for the PLL core.
Ground pin.
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
23
24
25
26
PCIeT_L0
PCIeC_L0
PCIeT_L1
PCIeC_L1
OUT
OUT
OUT
OUT
27
28
GND
PWR
PWR
Ground pin.
VDDPCIe
Power supply for PCI Express clocks, nominal 3.3V
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
29
30
31
32
PCIeT_L2
PCIeC_L2
PCIeT_L3
PCIeC_L3
OUT
OUT
OUT
OUT
1276D—10/25/07
2
ICS932S825
Pin Description (continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
33
PCIeC_L4
PCIeT_L4
OUT
34
OUT
35
36
GND
PWR
PWR
Ground pin.
VDDPCIe
Power supply for PCI Express clocks, nominal 3.3V
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
37
38
39
PCIeC_L5
PCIeT_L5
PCIeC_L6
OUT
OUT
OUT
Complement clock of 0.8V differential push-pull PCI_Express pair. (no
50ohm resistor to GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm
resistor to GND needed)
Ground pin.
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
40
41
42
43
44
PCIeT_L6
GND
OUT
PWR
OUT
OUT
OUT
CPUK8GC_L0
CPUK8GT_L0
CPUK8GC_L1
45
46
47
CPUK8GT_L1
GND
OUT
PWR
PWR
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Ground pin.
VDDCPU
Supply for CPU clocks, 3.3V nominal
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
48
49
50
51
52
CPUK8GC_L2
CPUK8GT_L2
CPUK8GC_L3
CPUK8GT_L3
CPUK8GC_L4
OUT
OUT
OUT
OUT
OUT
53
54
55
CPUK8GT_L4
GND
OUT
PWR
PWR
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Ground pin.
VDDCPU
Supply for CPU clocks, 3.3V nominal
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Complementary signal of low-power differential push-pull AMD K8
"Greyhound" clock
56
57
58
CPUK8GC_L5
CPUK8GT_L5
CPUK8GC_L6
OUT
OUT
OUT
59
60
61
62
CPUK8GT_L6
SPREAD_EN
GND25MHz
25MHz_1_2x
OUT
IN
True signal of low-power differential push-pull AMD K8 "Greyhound" clock
Asynchronous, active high input to enable spread spectrum functionality.
PWR
OUT
Ground pin for the 25Mhz outputs
25MHz clock output, 3.3V. Default 2 load drive
Frequency select latch input pin / Fixed 25MHz 3.3V clock output. Default 2
load drive
63
64
FS0/25MHz_0_2x
VDD25MHz
I/O
PWR
Power supply for 25MHz clocks, 3.3V nominal.
1276D—10/25/07
3
ICS932S825
General Description
The ICS932S825 is a main clock synthesizer chip that all clocks required by Serverworks HT2400-based servers.
An SMBus interface allows full control of the device.
Block Diagram
REF(2:1), REF0_RUN
X1
XTAL
OSC.
48MHz(1:0)
25MHz(1:0)
FIXED PLL
25MHz PLL
X2
25M
DIV
CPU/SRC/
PCI PLL
CPU
DIV
CPUK8G(6:0)
PCICLK(1:0)
FS(2:0)
CKPWRGD/PD#
SPREAD_EN
CONTROL
LOGIC
PCI33
DIV
SDATA
SCLK
SRC
DIV
PCIe(6:0)
Single-ended Terminations (All Single-Ended Outputs)
Single-ended
Number of
Series Resistor for Proper Termination
Zo = 50 ohms
Output Strength Loads on Board
1 Load
2 Load
(Default)
1
1
2
33
39
22
Differential Terminations
Differential
Output
Number of
Loads on Board
Series Resistor for Proper Termination
Zo = 50 ohms
CPUK8Gx
PCIe_Lx
1
1
33
33
1276D—10/25/07
4
ICS932S825
Frequency Selection Table
Byte 0
Bit 4 Bit 3 Bit2 Bit1 Bit0
CPU
SRC
PCI
Spread OverClock
SS_EN FS3 FS2 FS1 FS0 (MHz)
(MHz)
(MHz)
%
Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Hi-Z
X/4
180.00
220.00
100.00
133.33
Hi-Z
X/8
90.00
110.00
100.00
100.00
Hi-Z
x/24
N/A
N/A
0
N/A
N/A
0.90
1.10
1.00
1.00
30.00
36.67
33.33
33.33
Reserved
33.33
30.67
31.33
32.00
32.67
34.00
34.67
35.33
36.00
Hi-Z
0
0
0
0
200.00
184.00
188.00
192.00
196.00
204.00
208.00
212.00
216.00
Hi-Z
100.00
92.00
94.00
96.00
98.00
102.00
104.00
106.00
108.00
Hi-Z
1.00
0.92
0.94
0.96
0.98
1.02
1.04
1.06
1.08
N/A
0
0
0
0
0
0
0
0
N/A
N/A
-0.5%
-0.5%
-0.5%
-0.5%
X/4
X/8
x/24
N/A
180.00
220.00
100.00
133.33
90.00
110.00
100.00
100.00
30.00
36.67
33.33
33.33
Reserved
33.33
30.67
31.33
32.00
32.67
34.00
34.67
35.33
36.00
1.00
1.00
1.00
1.00
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
200.00
184.00
188.00
192.00
196.00
204.00
208.00
212.00
216.00
100.00
92.00
94.00
96.00
98.00
102.00
104.00
106.00
108.00
1.00
0.92
0.94
0.96
0.98
1.02
1.04
1.06
1.08
1276D—10/25/07
5
ICS932S825
CPU Divider Ratios
Divider (3:2)
Bit
00
01
10
11
00
0000
0001
0010
0011
01
0100
0101
0110
0111
10
1000
1001
1010
1011
11
1100
1101
1110
1111
MSB
16
24
40
120
Div
2
3
5
15
Div
4
6
10
30
Div
8
12
20
60
Div
Address
Address
Address
Address
LSB
PCI Divider Ratios
Divider (3:2)
Bit
00
01
00
0000
0001
01
0100
0101
10
1000
1001
11
1100
1101
MSB
32
24
4
3
8
6
16
12
0010
0011
Address
0110
0111
Address
1010
1011
Address
1110
1111
Address
10
11
LSB
5
15
Div
10
30
Div
20
60
Div
40
120
Div
SRC Divider Ratios
Divider (3:2)
Bit
00
01
10
11
00
0000
0001
0010
0011
01
0100
0101
0110
0111
10
1000
1001
1010
1011
11
1100
1101
1110
1111
MSB
16
24
40
56
2
3
5
7
Div
4
6
10
14
Div
8
12
20
28
Div
Address
Address
Address
Address
Div
LSB
1276D—10/25/07
6
ICS932S825
Absolute Maximum Ratings
Parameter
Symbol
VDDA
VDD
Min
Max
GND + 4.5V
GND +4.5V
150
Units Notes
V
1
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
V
1
Ts
-50
0
°C
°C
Tambient
70
Ambient Operating Temp
ESD prot
2000
V
1
Input ESD protection human body model
1Operation at these extremes is neither implied nor guaranteed
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
Conditions
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS NOTES
VIH
VIL
IIH
2
VSS - 0.3
-5
V
V
1
1
1
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
5
uA
IIL1
IIL2
-5
uA
uA
1
1
Input Low Current
-200
Operating Current
Powerdown Current
Input Frequency3
Pin Inductance1
IDD3.3OP
IDD3.3PD
Fi
all outputs driven
all diff pairs Low/Low
VDD = 3.3 V
250
15
mA
mA
MHz
nH
14.318
3
1
1
1
1
Lpin
7
5
6
5
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
pF
Input Capacitance1
COUT
CINX
pF
pF
From VDD Power-Up or de-assertion
of PD# to 1st clock
Clk Stabilization1,2
TSTAB
3
ms
1,2
Modulation Frequency
SMBus Voltage
Triangular Modulation
30
2.7
33
5.5
0.4
kHz
V
1
1
1
VDD
VOL
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
@ IPULLUP
V
IPULLUP
TRI2C
4
mA
ns
1
1
1
SCLK/SDATA
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
300
Clock/Data Rise Time3
SCLK/SDATA
(Min VIH + 0.15) to
(Max VIL - 0.15)
TFI2C
ns
Clock/Data Fall Time3
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
1276D—10/25/07
7
ICS932S825
AC Electrical Characteristics - Low Power Differential PCIe Outputs
Ω
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2
PARAMETER
SYMBOL
CONDITIONS
MIN
0.5
TYP
MAX
2
UNITS NOTES
Rising Edge Slew Rate
tSLR
Differential Measurement
V/ns
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
Single-ended Measurement
0.5
2
V/ns
%
1,2
1
Slew Rate Variation
Maximum Output
Voltage
tSLVAR
20
VHIGH
VLOW
Includes overshoot
Includes undershoot
1150
mV
mV
mV
1
1
1
Minimum Output Voltage
-300
Differential Voltage
Swing
Crossing Point Voltage
VSWING
Differential Measurement
400
300
VXABS
VXABSVAR
DCYC
Single-ended Measurement
Single-ended Measurement
Differential Measurement
550
140
55
mV
mV
%
1,3,4
1,3,5
1
Crossing Point Variation
Duty Cycle
45
PCIe Jitter - Cycle to
Cycle
PCIeJC2C
Differential Measurement
Differential Measurement
125
250
ps
ps
1
1
PCIe[6:0] Skew
PCIeSKEW
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling.
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
PCIe Phase Jitter Impact
Parameter
Conditions
Min
0
Typical
Max
108
Units
ps
Notes
Output phase jitter
impact – PCIe* Gen1
(including PLL BW 1.5-22 MHz, z =
0.54, Td=10 ns, Ftrk=1.5 MHz )
θPCIe1
1,2,3,4
Output phase jitter
impact - PCIe Gen2
(including PLL BW5-16 MHz,
8 – 16 MHz, z = 0.54, Td=10 ns)
ps
RMS
θPCIe2
0
3.1
1,2,3,4
NOTES:
Post processed evaluation through Intel supplied Matlab scripts.
1.
2.
3.
PCIe* Gen2 filter characteristics are subject to final ratification by PC ISIG. Please check the PCI* SIG for the latest specification.
These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be extrapolated to this BER target.
4. Guaranteed by design and characterization, not 100% tested in production.
1276D—10/25/07
8
ICS932S825
AC Electrical Characteristics - Low Power Differential CPU Outputs
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load
PARAMETER
Crossing Point Variation
Frequency
SYMBOL
∆VCROSS
f
CONDITIONS
Single-ended Measurement
MIN
TYP
MAX
140
200
300
UNITS NOTES
mV
MHz
ppm
1
2
3
198.8
-300
Long Term Accuracy
ppm
tSLR
tFLR
Rising Edge Slew Rate
Differential Measurement
Differential Measurement
0.5
0.5
10
10
V/ns
V/ns
4,5
4,5
Falling Edge Slew Rate
CPU Jitter - Cycle to
Cycle
CPUJC2C
CPUJACC
VHIGH
Differential Measurement
Over a 10 uS period
150
1
ps
ns
6
7
1
1
CPU Jitter - Accumulated
Maximum Output Voltage
Minimum Output Voltage
-1
Includes overshoot, single-ended
measurement
Includes undershoot, single-ended
1150
mV
mV
VLOW
-300
400
measurement
Differential Voltage Swing
Peak-to-Peak
VDPK-PK
Differential Measurement
2400
mV
8
VD
Differential Voltage
Change in VD DC cycle-to-
cycle
Differential Measurement
Single-ended Measurement
200
-75
45
1200
75
mV
mV
9
∆VD
10
11
DCYC
CPUSKEW10
Duty Cycle
CPU[6:0] Skew
Differential Measurement
Differential Measurement
55
250
%
ps
Notes on Electrical Characteristics (Guaranteed by design and characterization, not 100% tested in production):
1Single-ended measurement at crossing point. Value is max-min over all time. DC value of common mode is not important due to
the blocking cap.
2 Minimum frequency results from 0.5% down spread.
3 Measured with spread spectrum off.
4 This parameter is intended to give guidance for simulation.
5 Differential measurement through the range of +/-100mV
6 Between any two adjacent cycles.
7 Accumulated over a 10 uS time periode, measured with JIT2 TIE at 50ps interval.
8 VDPK-PK is the overall magnitude of the differential signal.
9 VDMIN is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V
VD. VDMAX is the largest amplitude allowed.
10 The difference in magnitude of two adjacent VDDC measurements. VDDC is the stable post overshoot and ring-back part
11 Defined as tHIGH/tCYCLE
1276D—10/25/07
9
ICS932S825
Electrical Characteristics - 33 MHz PCICLK, 25MHz Outputs
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 5 pF (unless otherwise specified)
PARAMETER
PCI Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
see Tperiod min-max values
25MHz output nominal
IOH = -1 mA
MIN
-300
29.9910
29.9910
-50
TYP
40
MAX
300
30.0090
30.1598
50
UNITS Notes
ppm
1,2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
ns
ns
ns
ns
Tperiod
PCI Clock period
25MHz Long Accuracy
25MHz Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
2.4
-33
30
V
V
VOL
IOL = 1 mA
0.55
-33
V
OH @MIN = 1.0 V
OH@ MAX = 3.135 V
OL @ MIN = 1.95 V
mA
mA
mA
mA
V/ns
V/ns
%
IOH
IOL
Output High Current
Output Low Current
V
V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VT = 1.5 V
38
4
4
Edge Rate
Edge Rate
Duty Cycle
δV/δt
δV/δt
dt1
tsk1
tsk1
1
1
45
55
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
PCI Skew
25MHz Skew
Jitter, Cycle to cycle
250
250
250
ps
ps
ps
tjcyc-cyc
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
Electrical Characteristics - 48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
Tperiod
CONDITIONS
see Tperiod min-max values
48.00MHz output nominal
IOH = -1 mA
MIN
-100
20.8257
2.4
TYP
MAX
100
20.8340
UNITS Notes
ppm
ns
1,2
2
VOH
VOL
Output High Voltage
Output Low Voltage
V
1
IOL = 1 mA
V OH @ MIN = 1.0 V
0.55
-33
V
1
-33
30
mA
mA
mA
mA
V/ns
V/ns
%
1
1
1
1
1
1
1
IOH
IOL
Output High Current
Output Low Current
V
OH@ MAX = 3.135 V
V
V
OL @MIN = 1.95 V
OL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VT = 1.5 V
38
2
2
55
250
250
Edge Rate
Edge Rate
Duty Cycle
δV/δt
δV/δt
dt1
tsk1
tjcyc-cyc
1
1
45
VT = 1.5 V
VT = 1.5 V
Group Skew
Jitter, Cycle to cycle
ps
1
ps
1
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
1276D—10/25/07
10
ICS932S825
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
Tperiod
CONDITIONS
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V,
MIN
-300
69.8270
2.4
TYP
MAX
300
69.8550
UNITS Notes
ppm
ns
V
1
2
1
1
VOH
VOL
Output High Voltage
Output Low Voltage
0.4
-23
V
V
IOH
IOL
Output High Current
Output Low Current
-29
29
mA
mA
1
1
OH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL
27
@MAX = 0.4 V
Edge Rate
Edge Rate
Skew
δV/δt
δV/δt
tsk1
dt1
tjcyc-cyc
Rising edge rate
Falling edge rate
VT = 1.5 V
1
1
2
2
500
55
V/ns
V/ns
ps
%
ps
1
1
1
1
1
VT = 1.5 V
VT = 1.5 V
Duty Cycle
45
Jitter, Cycle to cycle
1000
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
1276D—10/25/07
11
ICS932S825
General SMBus serial interface information
How to Read:
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
1276D—10/25/07
12
ICS932S825
SMBus Table: Frequency Select and Spread Control Register
Byte 0
Bit 7
Pin #
Name
Reserved
Reserved
Reserved
SS_EN
FS3
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
0
0
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Spread Spectrum Enable
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
Latched
0
Latched
Latched
Latched
See CPU Frequency Select
Table
FS2
FS1
FS0
SMBus Table: Output Control Register
Byte 1
Bit 7
Pin #
Name
REF2
REF1
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Reserved
Type
RW
RW
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
0
Hi-Z
Hi-Z
1
PWD
6
5
4
Enable
Enable
Enable
Enable
Enable
Reserved
Enable
Enable
1
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF0_RUN
PCICLK1
PCICLK0
Reserved
48MHz_1
48MHz_0
17
16
-
10
9
RW
Reserved
Output Enable
Output Enable
RW Disable (Low)
RW Disable (Low)
SMBus Table: Output Control Register
Byte 2
Bit 7
Pin #
Name
Reserved
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
Reserved
Reserved
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Reserved
Enable
Enable
Enable
Enable
Enable
Enable
Enable
0
1
1
1
1
1
1
1
59/58
57/56
53/52
51/50
47/46
45/44
43/42
CPUK8G_L(6)
CPUK8G_L(5)
CPUK8G_L(4)
CPUK8G_L(3)
CPUK8G_L(2)
CPUK8G_L(1)
CPUK8G_L(0)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output Enable
When Disabled
CPUK8GT_L = 0
CPUK8GC_L = 0
SMBus Table: Output Control Register
Byte 3
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
Reserved
PCIe_L6
PCIe_L5
PCIe_L4
PCIe_L3
PCIe_L2
PCIe_L1
PCIe_L0
Reserved
Reserved
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Reserved
Enable
Enable
Enable
Enable
Enable
Enable
Enable
0
1
1
1
1
1
1
1
40/39
38/37
33/34
31/32
29/30
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output Enable
When Disabled
PCIeT_L = 0
PCIeC_L = 0
25/26
23/24
1276D—10/25/07
13
ICS932S825
SMBus Table: Drive Strength Control Register
Byte 4
Bit 7
Pin #
Name
REF2
REF1
Control Function
Drive Strength Select
Drive Strength Select
Drive Strength Select
Drive Strength Select
Drive Strength Select
Drive Strength Select
Drive Strength Select
Drive Strength Select
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
6
5
4
1 Load
1 Load
1 Load
1 Load
1 Load
1 Load
1 Load
1 Load
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
1
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF0_RUN
PCICLK1
PCICLK0
48MHz_2
48MHz_1
48MHz_0
17
16
11
10
9
SMBus Table: Drive Strength Control Register
Byte 5
Bit 7
Pin #
62
63
62
63
-
-
-
-
Name
Control Function
Output Enable
Output Enable
Drive Strength Select
Drive Strength Select
Reserved
VDIFF MSB
VDIFF Select Bit 0
VDIFF LSB
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Low
Hi-Z
1
PWD
25MHz_1
25MHz_0
25MHz_1
25MHz_0
Reserved
VDIFF2
Enable
Enable
2 Loads
2 Loads
Reserved
1
1
1
1
0
1
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1 Load
1 Load
Reserved
See VDIFF Select Table
VDIFF1
VDIFF0
SMBus Table: Device ID Register
Byte 6
Bit 7
Pin #
Name
Control Function
Device ID MSB
Device ID 6
Device ID 5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID LSB
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
DevID 7
DevID 6
DevID 5
DevID 4
DevID 3
DevID 2
DevID 1
DevID 0
0
0
1
0
0
1
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Vendor ID Register
Byte 7
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
1
0
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID
VENDOR ID
(0001 = ICS)
1276D—10/25/07
14
ICS932S825
SMBus Table: Byte Count Register
Byte 8
Bit 7
Pin #
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register will
configure how many bytes
will be read back, default is
9 bytes.
Byte Count Programming
b(7:0)
SMBus Table: Reserved Register
Byte 9
Bit 7
Pin #
Name
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: M/N Programming Enable
Byte 10
Pin #
Name
Control Function
CPU PLL M/N Programming
Enable
Type
0
1
PWD
-
M/N_EN
RW
Disable
Enable
0
Bit 7
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1276D—10/25/07
15
ICS932S825
Bytes 11:14 are Reserved Registers
SMBus Table: CPU Frequency Control Register
Byte 15
Bit 7
Pin #
Name
N Div8
Control Function
N Divider Prog bit 8
Type
RW
0
1
PWD
X
-
-
-
-
-
-
-
-
The decimal representation
of M and N Divier in Byte 11
and 12 will configure the
CPU VCO frequency.
Default at power up = latch-
in or Byte 0 Rom table. VCO
Frequency = 14.318 x
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Prog bit 9
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M Divider Programming
bit (5:0)
[NDiv(9:0)+8] / [MDiv(5:0)+2]
SMBus Table: CPU Frequency Control Register
Byte 16
Bit 7
Pin #
Name
N Div7
Control Function
Type
RW
0
1
PWD
X
-
-
-
-
-
-
-
-
The decimal representation
of M and N Divier in Byte 11
and 12 will configure the
CPU VCO frequency.
Default at power up = latch-
in or Byte 0 Rom table. VCO
Frequency = 14.318 x
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Divider Programming
Byte12 bit(7:0) and Byte11
bit(7:6)
[NDiv(9:0)+8] / [MDiv(5:0)+2]
SMBus Table: CPU Spread Spectrum Control Register
Byte 17
Bit 7
Pin #
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits
in Byte 13 and 14 will
program the spread
Spread Spectrum
Programming bit(7:0)
pecentage of CPU
1276D—10/25/07
16
ICS932S825
SMBus Table: CPU Spread Spectrum Control Register
Byte 18
Bit 7
Pin #
Name
Reserved
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
Control Function
Type
R
0
-
1
-
PWD
0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
Reserved
RW
RW
RW
RW
RW
RW
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits
in Byte 13 and 14 will
program the spread
Spread Spectrum
Programming bit(14:8)
pecentage of CPU
SSP8
SMBus Table: Programmable Output Divider Register
Byte 19
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
R
R
R
R
0
1
PWD
-
-
-
-
-
-
-
-
CPUDiv3
CPUDiv2
CPUDiv1
CPUDiv0
Reserved
Reserved
Reserved
Reserved
X
X
X
X
0
0
0
0
CPU Divider Ratio
Programming Bits
See CPU Divider Ratios
Table
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
SMBus Table: Programmable Output Divider Register
Byte 20
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
33MHzDiv3
33MHzDiv2
33MHzDiv1
33MHzDiv0
SRC_Div3
SRC_Div2
SRC_Div1
SRC_Div0
33MHz Divider Ratio
Programming Bits
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
33MHz Divider Ratio Table
SRC_ Divider Ratio
Programming Bits
SRC Divider Ratio Table
SMBusTable: Reserved Regsiter
Byte 21 is reserved do not write this register!
1276D—10/25/07
17
ICS932S825
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) on the
ICS932S825 serve as dual signal functions to the device.
During initial power-up, they act as input pins. The logic
level (voltage) that is present on these pins at this time
is read and stored into a 5-bit internal data latch. At the
end of Power-On reset, (see AC characteristics for timing
values), the device changes the mode of operations for
these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
1276D—10/25/07
18
ICS932S825
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
SYMBOL
L
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
2
E1
e
L
6.00
0.50 BASIC
0.45
6.20
.236
.244
0.020 BASIC
.030
SEE VARIATIONS
D
0.75
.018
N
SEE VARIATIONS
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A
A2
VARIATIONS
A1
D mm.
D (inch)
N
- C -
MIN
16.90
MAX
17.10
MIN
.665
MAX
.673
64
e
SEATING
PLANE
b
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
aaa
C
Ordering Information
ICS932S825yGLFT
Example:
ICS XXXX y G - LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
1276D—10/25/07
19
ICS932S825
Revision History
Rev.
Issue Date Description
Page #
1. Updated Electrical Characteristics.
2. Going to Preliminary.
A
B
C
02/28/07 3. Updated Idd to reflect low power outputs
09/11/07 1. Updated pin description
09/12/07 1. Updated quantity of PCIEX outputs listed under "Output Features"
Various
2, 3
1
1. Corrected CPU/SRC/PCI PLL control bytes to B(15:18) from B(11:14)
2. Changed pin names to indicate default drive strength. NO silicon changes.
3. Corrected Byte 0 SS_EN and FS3 reference in FS table.
4. Simplified the Terminations Table..
1, 2, 3, 4, 5,
16,17
D
10/25/07 5. Release to Final
1276D—10/25/07
20
相关型号：
ICS932S825YGT
Processor Specific Clock Generator, 220MHz, PDSO64, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64
IDT
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