ICS93732 [ICSI]
Low Cost DDR Phase Lock Loop Zero Delay Buffer; 低成本DDR锁相环零延迟缓冲器
| 型号： | ICS93732 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Cost DDR Phase Lock Loop Zero Delay Buffer |
| 文件： | 总8页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS93732
Integrated
Circuit
Systems,Inc.
LowCostDDRPhaseLockLoopZeroDelayBuffer
Recommended Application:
DDR Zero Delay Clock Buffer
PinConfiguration
DDRC0
DDRT0
VDD
DDRT1
DDRC1
GND
SCLK
CLK_INT
N/C
1
2
3
4
5
6
7
8
9
28 GND
27 DDRC5
26 DDRT5
25 DDRC4
24 DDRT4
23 VDD
22 SDATA
21 N/C
20 FB_INT
19 FB_OUT
18 N/C
ProductDescription/Features:
•
•
•
•
Low skew, low jitter PLL clock driver
Max frequency supported = 266MHz (DDR 533)
I2C for functional and output control
Feedback pins for input to output synchronization
•
•
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT input
VDDA 10
GND 11
Switching Characteristics:
•
•
•
•
•
CYCLE - CYCLE jitter (66MHz): <120ps
CYCLE - CYCLE jitter (>100MHz): <65ps
CYCLE - CYCLE jitter (>200MHz): <75ps
OUTPUT - OUTPUT skew: <100ps
DUTY CYCLE: 49.5% - 50.5%
VDD 12
DDRT2 13
DDRC2 14
17 DDRT3
16 DDRC3
15 GND
28-Pin 209mil SSOP
28-Pin 173mil TSSOP
BlockDiagram
Functionality
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLKT CLKC FB_OUTT
FB_OUTT
2.5V
(nom)
L
L
H
L
L
on
on
Control
SCLK
DDRT0
DDRC0
Logic
SDATA
2.5V
(nom)
H
H
H
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
FB_INT
PLL
DDRT4
DDRC4
CLK_INT
DDRT5
DDRC5
0578H—02/19/04
ICS93732
PinDescriptions
PIN # PIN NAME
PIN TYPE DESCRIPTION
1
2
3
4
5
6
7
8
DDRC0
DDRT0
VDD
DDRT1
DDRC1
GND
SCLK
CLK_INT
N/C
OUT
OUT
PWR
OUT
OUT
PWR
IN
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
Ground pin.
Clock pin of I2C circuitry 5V tolerant
"True" reference clock input.
IN
N/C
9
No Connection.
10
11
12
13
14
15
16
17
18
19
VDDA
GND
VDD
DDRT2
DDRC2
GND
DDRC3
DDRT3
N/C
PWR
PWR
PWR
OUT
OUT
PWR
OUT
OUT
N/C
2.5V power for the PLL core.
Ground pin.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
Ground pin.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
No Connection.
Feedback output, dedicated for external feedback.
True single-ended feedback input, provides feedback
signal to internal PLL for synchronization with CLK_INT
to eliminate phase error.
FB_OUT
OUT
20
FB_INT
IN
21
22
23
24
25
26
27
28
N/C
SDATA
VDD
DDRT4
DDRC4
DDRT5
DDRC5
GND
N/C
I/O
No Connection.
Data pin for I2C circuitry 5V tolerant
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
Ground pin.
PWR
OUT
OUT
OUT
OUT
PWR
0578H—02/19/04
2
ICS93732
AbsoluteMaximumRatings
Supply Voltage (VDD & AVDD) . . . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . 0°C to +85°C
Case Temperature . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Recommended Operation Conditions
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V 0.20V (unless otherwise stated)
PARAMETER
Analog / Core Supply Volta
Input Voltage Level
SYMBOL
AVDD
CONDITIONS
MIN
2.3
2
TYP MAX UNITS
2.5
2.5
2.7
3
V
V
VIN
Output Differential Pair
Crossing Voltage
VOC
66/100/133/166MHz, VDD=2.50V
1.23
1.25
1.32
V
Electrical Characteristics - Input / Supply / Common Output parameters
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
RT = 120W, CL = 12 pF at 100MHz
RT = 120W, CL = 12 pF at 133MHz
236
263
300
300
100
-29
37
IDD2.5
mA
Operating Supply Current
IDDPD
IOH
CL=0 pF
VDD = 2.5V, VOUT = 1V
VDD = 2.5V, VOUT = 1.2V
mA
mA
mA
Output High Current
Output Low Current
High Impedance
Ouptut Current
-48
29
-33
33
IOL
IOZ
VDD = 2.7V, VOUT = VDD or GND
10
mA
V
VDD = min to max, IOH = -1mA
VDD = 2.3V, IOH = -12mA
2
2.25
1.95
0.05
0.3
High-level Output Voltage
VOH
V
VDD = min to max, IOH = 1mA
0.1
0.4
Low-level Output Voltage
Output Capacitance1
VOL
V
DD = 2.3V, IOH = 12mA
pF
VI = VDD or GND
COUT
3
1. Guaranteed by design, not 100% tested in production.
0578H—02/19/04
3
ICS93732
Timing Requirements
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated)
PARAMETER
SYMBOL
freqop
dtin
CONDITIONS
MIN
22
TYP MAX UNITS
340
60
MHz
%
Operating Clock Frequency
Input Clock Duty Cycle1
Clock Stabilization1
Input Voltage level: 0-2.50V
40
50
µ
s
tSTAB
100
from VDD = 2.5V to 1% target frequency
1. Guaranteed by design, not 100% tested in production.
Switching Characteristics
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
66 MHz
100 / 125/ 133/167MHz
200/267MHz
MIN
TYP MAX UNITS
100
48
120
65
Cycle to cycle Jitter1,2
tc-c
ps
47
75
Phase Error1
Output to output Skew1
tpe
Tskew
-150
150
100
ps
ps
%
%
ps
20
50
49.4
579
66 MHz to 100MHz
101MHz to 267 MHz
Load=120Ω/14pF
49.5
49
50.5
51
950
Duty Cycle (Sign Ended)1,3
DC
Rise Time, Fall Time4
tR , tf
Notes:
1. Refers to transition on noninverting output.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula:duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
0578H—02/19/04
4
ICS93732
General I2Cserialinterfaceinformation
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) will send start bit.
• Controller (host) sends the write address D4(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• Controller (host) sends the read address D5(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
Address
ICS (Slave/Receiver)
Start Bit
D4(H)
Address
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
D5(H)
Dummy Command Code
Dummy Byte Count
Byte 0
ACK
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
forverification. Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0578H—02/19/04
5
ICS93732
Bytes 0 to 4 are reseved power up default = 1. This allows operation with main clock.
BYTE
5
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2, 1
4, 5
-
-
13, 14
17, 16
DDR0(T&C)
DDR1(T&C)
Output Control
Output Control
Reserved
RW DISABLE ENABLE
RW DISABLE ENABLE
1
1
1
1
1
1
1
1
-
-
X
X
-
-
-
-
Reserved
DDR2(T&C)
DDR3(T&C)
Output Control
Output Control
Reserved
RW DISABLE ENABLE
RW DISABLE ENABLE
-
-
-
-
X
X
-
-
-
-
Reserved
Note: PWD = Power Up Default
BYTE
6
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
-
-
-
0
-
1
-
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Output Control
Reserved
X
X
X
X
0
0
0
1
1
1
1
1
-
-
-
-
-
-
-
24, 25
DDR4(T&C)
RW DISABLE ENABLE
-
26, 27
-
-
X
-
-
DDR5(T&C)
-
Output Control
Reserved
RW DISABLE ENABLE
X
-
-
Note: PWD = Power Up Default
0578H—02/19/04
6
ICS93732
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
1.65
0.22
0.09
MAX
2.00
--
1.85
0.38
0.25
MIN
--
.002
.065
.009
.0035
MAX
.079
--
.073
.015
.010
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
7.40
5.00
8.20
5.60
.291
.197
.323
.220
1
22
0.65 BASIC
0.0256 BASIC
α
L
0.55
0.95
.022
.037
D
A
N
α
SEE VARIATIONS
SEE VARIATIONS
A2
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
9.90
MAX
10.50
MIN
.390
MAX
b
28
.413
Reference Doc.: JEDEC Publication 95, MO-150
.10 (.004) C
10-0033
209 mil SSOP
Ordering Information
ICS93732yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0578H—02/19/04
7
ICS93732
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.012
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
2
E1
e
L
4.30
0.65 BASIC
0.45
4.50
.169
0.0256 BASIC
.018
.177
α
D
0.75
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
VARIATIONS
A1
D mm.
D (inch)
N
- CC --
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
28
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
b
aaa
C
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256 Inch)
(173 mil)
OrderingInformation
ICS93732yG -T
Example:
ICS XXXX y G - T
Designationfortapeandreelpackaging
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0578H—02/19/04
8
相关型号：
ICS93732AF
PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.209 INCH, MO-150, SSOP-28
IDT
ICS93732AF-T
93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28, 0.209 INCH, MO-150, SSOP-28
IDT
ICS93732AFLF
PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.209 INCH, GREEN, MO-150, SSOP-28
IDT
ICS93732AFLF-T
93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28, 0.209 INCH, GREEN, MO-150, SSOP-28
IDT
ICS93732AFLFT
PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.209 INCH, GREEN, MO-150, SSOP-28
IDT
ICS93732AFT
PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 0.209 INCH, MO-150, SSOP-28
IDT
ICS93732AG
PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28
IDT
ICS93732AG-T
93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28
IDT
ICS93732AGT
PLL Based Clock Driver, 93732 Series, 6 True Output(s), 6 Inverted Output(s), PDSO28, 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28
IDT
©2020 ICPDF网 联系我们和版权申明