ICS93V857 [ICSI]
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz); 2.5V的宽范围频率时钟驱动器（为33MHz - 233MHz的）
| 型号： | ICS93V857 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz) |
| 文件： | 总10页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS93V857-XXX
Integrated
Circuit
Systems,Inc.
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
RecommendedApplication:
Pin Configuration
•
•
DDR Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
ProductDescription/Features:
•
•
•
•
•
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
PD#forpowermanagement
GND
GND
CLKC2
CLKT2
VDD
CLKC7
CLKT7
VDD
VDD
PD#
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
Spread Spectrum tolerant inputs
•
•
Auto PD when input signal removed
Choice of static phase offset available,
for easy board tuning;
-XXX = device pattern number for options listed
below.
-ICS93V857-025 ...... 0ps
-ICS93V857-125 +125ps
-ICS93V857-130 .. +40ps
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
SwitchingCharacteristics:
•
•
•
•
•
•
Period jitter (>66MHz):<40ps
CYCLE - CYCLE jitter (66MHz): <120ps
CYCLE - CYCLE jitter (>100MHz): <65ps
OUTPUT - OUTPUT skew: <60ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
Block Diagram
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
Functionality
Control
Logic
CLKT2
CLKC2
PD#
INPUTS
OUTPUTS
PLL State
CLKT3
CLKC3
AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND
GND
H
H
L
H
L
L
H
L
L
H
L
Bypassed/off
Bypassed/off
CLKT4
CLKC4
H
H
H
FB_INT
FB_INC
CLKT5
CLKC5
2.5V
(nom)
L
L
L
H
L
H
L
Z
Z
L
Z
Z
H
L
Z
Z
L
Z
Z
H
L
off
off
on
on
off
PLL
CLK_INC
CLK_INT
CLKT6
CLKC6
2.5V
(nom)
CLKT7
CLKC7
2.5V
(nom)
H
H
X
H
L
CLKT8
CLKC8
2.5V
(nom)
H
H
Z
H
Z
CLKT9
CLKC9
2.5V
(nom)
<20MHz)(1)
Z
Z
0693K—03/13/03
1
ICS93V857-XXX
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
4, 11, 12, 15, 21,
28, 34, 38, 45,
VDD
PWR Power supply 2.5V
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
GND
PWR Ground
16
17
AVDD
AGND
PWR Analog power supply, 2.5V
PWR Analog ground.
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
CLKT(9:0)
CLKC(9:0)
OUT
OUT
"True" Clock of differential pair outputs.
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
"Complementary" clocks of differential pair outputs.
14
13
CLK_INC
CLK_INT
IN
IN
"Complementary" reference clock input
"True" reference clock input
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
33
FB_OUTC
OUT
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
32
36
FB_OUTT
FB_INT
OUT
IN
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
35
37
FB_INC
PD#
IN
IN
Power Down. LVCMOS input
This PLL Clock Buffer is designed for a VDD of 2.5V, AVDD of 2.5V and differential data input and output levels.
ICS93V857-XXX is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC).The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD).When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs areTri-Stated.When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
WhentheinputfrequencyislessthantheoperatingfrequencyofthePLL, appproximately20MHz, thedevicewillenter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputswillbeenabledandPLLwillobtainphaselockbetweenthefeedbackclockpair(FB_INT, FB_INC) andtheinput
clock pair (CLK_INC, CLK_INT).
ThePLLinICS93V857-XXX clockdriverusestheinputclocks(CLK_INC, CLK_INT)andthefeedbackclocks(FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]).
ICS93V857-XXX is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS93V857-XXX is characterized for operation from 0°C to 85°C.
0693K—03/13/03
2
ICS93V857-XXX
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VDD + 0.5V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +85°C
StorageTemperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
SYMBOL
CONDITIONS
VI = VDD or GND
VI = VDD or GND
MIN
5
TYP
MAX
5
UNITS
µA
µA
mA
mA
V
IIH
IIL
Operating Supply
Current
IDD2.5 CL = 0pf @ 100MHz
IDDPD CL = 0pf
250
65
90
Input Clamp Voltage
VIK
VDDQ = 2.3V Iin = -18mA
-1.2
High-level output
voltage
I
I
I
I
OH = -1 mA
OH = -12 mA
OL=1 mA
VDD - 0.1
1.7
2.45
2.10
0.05
0.35
3
V
VOH
V
0.1
0.6
V
Low-level output voltage
VOL
OL=12 mA
V
Input Capacitance1
Output Capacitance1
1Guaranteed by design at 233MHz, not 100% tested in production.
CIN
VI = GND or VDD
pF
pF
COUT
VOUT = GND or VDD
3
0693K—03/13/03
3
ICS93V857-XXX
Recommended Operating Condition
(see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
V
VDDQ, AVDD
CLK_INT, CLK_INC, FB_INC,
FB_INT
PD#
CLK_INT, CLK_INC, FB_INC,
FB_INT
PD#
0.4
VDD/2 - 0.18
0.7
V
V
V
V
V
Low level input voltage
High level input voltage
VIL
-0.3
DD/2 + 0.18
1.7
V
2.1
VIH
VIN
V
DD + 0.6
DC input signal voltage
(note 2)
-0.3
VDD + 0.3
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.36
0.7
V
DD + 0.6
V
V
V
V
Differential input signal
voltage (note 3)
VID
VDD + 0.6
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
VOX
VIX
VDD/2 - 0.15
VDD/2 + 0.15
VDD/2 - 0.2 VDD/2 VDD/2 + 0.2
High level output current
IOH
IOL
-12
12
mA
mA
Low level output current
High Impedance
Output Current
Operating free-air
temperature
IOZ
TA
VDD=2.7V, VOUT=VDD or GND
0.1
±10
85
mA
°C
0
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDD and is the
voltage at which the differential signal must be crossing.
0693K—03/13/03
4
ICS93V857-XXX
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
freqop
MIN
33
MAX UNITS
Max clock frequency3
Application Frequency
Range3
233
MHz
2.5V+0.2V
freqApp
dtin
60
40
170
60
MHz
%
2.5V+0.2V
Input clock duty cycle
CLK stabilization
TSTAB
100
µs
Switching Characteristics
PARAMETER
Low-to high level
propagation delay time
High-to low level propagation
delay time
SYMBOL
CONDITION
MIN
TYP
5.5
MAX UNITS
ns
1
CLK_IN to any output
CLK_IN to any output
tPLH
1
5.5
ns
tPHL
Output enable time
Output disable time
ten
tdis
PD# to any output
PD# to any output
5
5
ns
ns
Period jitter
tjit (per)
tjit(hper)
tsl(I)
tsl(o)
66/100/125/133/167MHz
100 to <170MHz
≥170MHz to 233MHz
-40
-100
-120
1
40
100
50
4
ps
ps
ps
Half-period jitter
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter1
Phase error
v/ns
v/ns
66/100/133/167MHz
1
2
tcyc-tcyc
t(phase error)
tskew
66/100/125/133/167MHz
60
50
ps
ps
ps
ps
4
-50
0
Output to Output Skew
Rise Time, Fall Time
40
60
tr, tf
Load = 120Ω/16pF
650
800
950
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, were
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0693K—03/13/03
5
ICS93V857-XXX
Parameter Measurement Information
V
DD
V
(CLKC)
R = 60Ω
V
DD
/2
R = 60Ω
V
(CLKC)
ICS93V857
GND
Figure 1. IBIS Model Output Load
VDD/2
C = 14 pF
ICS93V857
-VDD/2
SCOPE
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 60Ω
R = 50Ω
(TT)
V
R = 10Ω
Z = 50Ω
R = 50Ω
C = 14 pF
-VDD/2
V
(TT)
-VDD/2
NOTE: V
(TT) = GND
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
t
t
c(n+1)
c(n)
t
= t
± t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
0693K—03/13/03
6
ICS93V857-XXX
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
( ) n
( ) n+1
n = N
t
1
( ) n
t
=
( )
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(skew)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
tC(n)
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
fO
t(jit_per) tc(n)
=
-
Figure 6. Period Jitter
0693K—03/13/03
7
ICS93V857-XXX
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
jit(hper_n+1)
jit(hper_n)
1
f
o
tjit(hper) = tjit(hper_n)
1
2xfO
-
Figure 7. Half-Period Jitter
80%
80%
V , V
ID OD
20%
20%
Clock Inputs
and Outputs
t
t
slf
slr
Figure 8. Input and Output Slew Rates
0693K—03/13/03
8
ICS93V857-XXX
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
a
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
MIN
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
b
48
12.40
Reference Doc.: JEDEC Publication 95, MO-153
aaa
C
10-0039
Choice of static phase offset available, for easy board tuning;
-XXX = device pattern number for options listed below.
-ICS93V857-025 ...... 0ps
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
-ICS93V857-125 +125ps
-ICS93V857-130 .. +40ps
Ordering Information
ICS93V857yG-025T ICS93V857yG-125T ICS93V857yG-130T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0693K—03/13/03
9
ICS93V857-XXX
c
N
In Millimeters
In Inches
L
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.13
0.09
MAX
1.20
0.15
1.05
0.23
0.20
MIN
--
.002
.032
.005
.0035
MAX
.047
.006
.041
.009
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
22
α
4.30
4.50
.169
.177
D
0.40 BASIC
0.016 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.08
0°
--
8°
.003
A
A2
A1
VARIATIONS
D mm.
D (inch)
- CC --
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
e
SEATING
PLANE
48
b
Reference Doc.: JEDEC Publication 95, MO-153
aaa
C
10-0037
Choice of static phase offset available, for easy board tuning;
-XXX = device pattern number for options listed below.
-ICS93V857-025 ...... 0ps
4.40 mm. Body, 0.40 mm. pitch TSSOP
(16 mil)
(173 mil)
-ICS93V857-125 +125ps
-ICS93V857-130 .. +40ps
Ordering Information
ICS93V857yL-025T ICS93V857yL-125T ICS93V857yL-130T
Example:
ICS XXXX y L - PPP - T
Designation for tape and reel packaging
Pattern Number
Package Type
L=TSSOP (TVSOP)
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS = Standard Device
0693K—03/13/03
10
相关型号：
ICS93V857YG-025LFT
PLL Based Clock Driver, 93V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
IDT
ICS93V857YG-025T
PLL Based Clock Driver, 93V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
IDT
ICS93V857YG-125LFT
PLL Based Clock Driver, 93V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
IDT
©2020 ICPDF网 联系我们和版权申明