ICS94229 [ICSI]
Programmable System Clock Chip for AMD - K7 processor; 可编程系统时钟芯片为AMD - K7处理器
| 型号： | ICS94229 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable System Clock Chip for AMD - K7 processor |
| 文件： | 总17页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS94229
Integrated
Circuit
Systems, Inc.
Advance Information
Programmable System Clock Chip forAMD - K7™ processor
Recommended Application:
VIA KT266 style chipset
Pin Configuration
Output Features:
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF0/FS0*
REF1/FS1*
REF_F
RATIO
AGP_STOP#*
GND
CPUCLKT0
CPUCLKC0
VDDL
CPUCLK_CST0
CPUCLK_CSC0
GND
CPU_STOP#*
PCI_STOP#*
PD#*
AVDD
AGND
SDATA
SCLK
GND
AGP2
AGP1
AGP0
VDDREF
GND
X1
X2
AVDD48
•
•
•
•
•
•
1 - Differential pair open drain CPU clocks @ 2.5V
1 - Differential pair push-pull CPU clocks @ 2.5V
11 - PCI including 1 free running and 1 early @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
*FS2/48MHz
*FS3/24_48MHz
GND
*WDEN/PCICLK_F
*SEL24_48#/PCICLK0
PCICLK1
GND
Features:
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
PCILCK8
PCICLK9_E
VDDPCI
•
•
•
Programmable output frequency.
Programmable output rise/fall time.
Programmable slew and skew control for CPUCLK,
PCICLK, AGP, REF, 48MHz and 24_48MHz.
•
•
Real time system reset output.
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage.
•
•
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
VDDAGP
SRESET#
48-Pin 300mil SSOP
*
Internal Pull-up Resistor of 120K to VDD
Skew Specifications:
•
•
•
•
CPU - CPU: <175ps
PCI - PCI: <500ps
CPU (early - PCI: min=1.0ns, max=2.0ns
CPU cycle to cycle jitter: <250ps
Functionality
Block Diagram
CPU
AGP
(MHz)
77.78
73.33
70.00
66.67
76.00
72.00
68.00
75.00
70.00
60.00
66.00
66.67
66.67
66.67
66.67
66.67
PCICLK
(MHz)
38.88
36.67
35.00
33.33
38.00
36.00
34.00
37.50
35.00
30.00
33.00
33.33
33.33
33.33
33.33
33.33
PLL2
48MHz (1:0)
24_48MHz
2
FS3
FS2
FS1
FS0
(MHz)
233.33
220.00
210.00
200.00
190.00
180.00
170.00
150.00
140.00
120.00
110.00
66.67
/ 2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X1
X2
XTAL
OSC
REF (1:0)
REF_F
2
PLL1
Spread
Spectrum
CPUCLKT0
CPUCLKC0
CPU
DIVDER
Stop
Stop
CPUCLK_CST0
CPUCLK_CSC0
CPU
DIVDER
SEL24_48#
PCICLK9_E
PCICLK (8:0)
PCICLK_F
AGP (2:0)
PCI
DIVDER
SDATA
SCLK
Stop
Stop
9
Control
Logic
FS (3:0)
200.00
166.67
100.00
133.33
AGP
DIVDER
3
PD#
PCI_STOP#
CPU_STOP#
AGP_STOP#
Config.
Reg.
SRESET#
RATIO
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
94229 Rev - 05/31/01
Third party brands and names are the property of their respective owners.
ICS94229
Advance Information
Pin Descriptions
PIN NUMBER
1, 15, 23, 25,
PIN NAME
VDD
TYPE
DESCRIPTION
PWR Power supply, nominal 3.3V
2, 8, 12, 19,
29, 37, 43
GND
PWR Ground
3
4
5
X1
IN
Crystal input, has internal load cap (36pF) and feedback resistor from X2
X2
OUT Crystal output, nominally 14.318MHz. Has internal load cap (36pF)
PWR Power supply, nominal 3.3V
AVDD48
FS21, 2
IN
Frequency select pin. Latched Input
6
7
48MHz
FS31, 2
OUT 48MHz output clock
IN
Frequency select pin. Latched Input
24_48MHz
WDEN
OUT 24 or 48MHz clock output
IN
OUT Free running PCI clock not affected by PCI_STOP# for power management.
IN Logic input to select 24 or 48MHz for pin 7 output
Hardware enable of watch dog circuit. Default safe frequency is 100MHz.
9
PCICLK_F
SEL24_48#1, 2
PCICLK0
10
OUT PCI clock output
21, 20, 18, 17,
16, 14, 13, 11
PCICLK (8:1)
OUT PCI clock outputs.
22
PCICLK9_E
SRESET#1
AGP (2:0)
SCLK
OUT Early PCI clock. Leads general PCI clocks by 2ns. Can be stopped by PCI_STOP#.
OUT Real time system reset signal for watchdog tmer timeout. This signal is active low.
OUT AGP clock outputs
24
28, 27, 26
30
31
32
33
IN
Clock input of I2C input, 5V tolerant input
Data pin for I2C circuitry 5V tolerant
SDATA
I/O
AGND
PWR Analog ground
AVDD
PWR Power supply, nominal 3.3V
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
34
PD#
IN
35
36
PCI_STOP#
IN
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low
This asynchronous input halts CPUCLKT, CPUCLKC & CUCLKC_CS clocks at logic "0"
level when driven low.
CPU_STOP#1, 2
"Complementary" clock of differential pair CPU output. These push-pull outputs need an
external 1.5V pull-up (push-pull)
"True" clock of differential pair CPU output. These push-pull outputs need an external 1.5V
pull-up (push-pull).
38
CPUCLK_CSC0
OUT
OUT
39
40
42
CPUCLK_CST0
VDDL
PWR Power supply for CPUCLKs, nominal 2.5V
"True" clock of differential pair CPU output. These open drain outputs need an external 1.5V
pull-up (open drain).
CPUCLKT0
OUT
"Complementary" clock of differential pair CPU output. These open drain outputs need an
external 1.5V pull-up (open drain).
41
CPUCLKC0
OUT
44
45
46
AGP_STOP#
RATIO
REF_F
FS11, 2
IN
Stops all AGP clocks at logic 0 level, when input low
OUT Outputs a "0" for 100MHz or "1" for 133MHz to the South Bridge
OUT 14.318 MHz free running reference clock., not afftected by REF_STOP#
IN
OUT 14.318 MHz reference clock.
IN Frequency select pin. Latched Input
OUT 14.318 MHz reference clock.
Frequency select pin. Latched Input
47
48
REF1
FS01, 2
REF0
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS94229
Advance Information
General Description
The ICS94229 is a main clock synthesizer chip for AMD-K7 based systems with VIA KT266 style chipset. This provides all
clocks required for such a system.
The ICS94229 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C
interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring
output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks.
This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system
become unstable from over clocking.
SRESET# Signal Description
The SRESET# signal from ICS94229 system clock generator is a real time active low pulse that can be used to reset the system.
The Open-Drain Nch output Reset# pin needs to be tied to the system reset line which has a pull-up resistor. When activated,
the SRESET# output will be driven to a low with a 288ms pulse width.
Third party brands and names are the property of their respective owners.
3
ICS94229
Advance Information
General I2C serial interface information
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 16
(see Note 2)
• ICS clock sends Byte 0 through byte 6 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 6).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address D3(H)
Address D2(H)
ACK
ACK
Dummy Command Code
Byte Count
ACK
ACK
Dummy Byte Count
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
ACK
ACK
ACK
ACK
ACK
ACK
If 7H has been written to B6
ACK
Byte 7
Byte 14
Byte 15
Byte 16
ACK
ACK
ACK
If 1AH has been written to B6
ACK
Byte 14
Byte 15
Byte 16
If 1BH has been written to B6
ACK
If 1CH has been written to B6
ACK
Stop Bit
Stop Bit
*See notes on the following page.
Third party brands and names are the property of their respective owners.
4
ICS94229
Advance Information
Brief I2C registers description for
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality & Frequency
Select Register
See individual
byte description
0
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Output Control Registers
1, 2, 3
5, 6, 7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
Vendor ID & Revision ID
Registers
See individual
byte description
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00H to this byte.
Byte Count
Read Back Register
8
4
08H
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
Watchdog Enable Register
Watchdog Control Registers
10H
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
VCO Control Selection Bit
4, 5
0
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
VCO Frequency Control
Registers
9, 10
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
These registers control the spread
percentage amount.
11, 12
Group Skews Control
Registers
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
13, 14
15, 16
Output Rise/Fall Time
Select Registers
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is
defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
5
ICS94229
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CPUCLK AGPCLK PCICLK
SSB1 SSB0 FS3 FS2 FS1 FS0
Spread Percentage
RATIO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
233.33
220.00
210.00
200.00
190.00
180.00
170.00
150.00
140.00
120.00
110.00
66.67
200.00
166.67
100.00
133.33
200.00
166.67
100.00
133.33
200.00
166.67
100.00
133.33
200.00
166.67
100.00
133.33
200.00
166.67
100.00
133.33
77.78
73.33
70.00
66.67
76.00
72.00
68.00
75.00
70.00
60.00
66.00
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
38.88 +/- 0.25% Center Spread
36.67 +/- 0.25% Center Spread
35.00 +/- 0.25% Center Spread
33.33 +/- 0.25% Center Spread
38.00 +/- 0.25% Center Spread
36.00 +/- 0.25% Center Spread
34.00 +/- 0.25% Center Spread
37.50 +/- 0.25% Center Spread
35.00 +/- 0.25% Center Spread
30.00 +/- 0.25% Center Spread
33.00 +/- 0.25% Center Spread
33.33 +/- 0.25% Center Spread
33.33 +/- 0.25% Center Spread
33.33 +/- 0.25% Center Spread
33.33 +/- 0.25% Center Spread
33.33 +/- 0.25% Center Spread
33.33 0 to -0.5% Down Spread
33.33 0 to -0.5% Down Spread
33.33 0 to -0.5% Down Spread
33.33 0 to -0.5% Down Spread
33.33 +/- 0.50% Center Spread
33.33 +/- 0.50% Center Spread
33.33 +/- 0.50% Center Spread
33.33 +/- 0.50% Center Spread
33.33 +/- 0.75% Center Spread
33.33 +/- 0.75% Center Spread
33.33 +/- 0.75% Center Spread
33.33 +/- 0.75% Center Spread
33.33 0 to +0.5% Up Spread
33.33 0 to +0.5% Up Spread
33.33 0 to +0.5% Up Spread
33.33 0 to +0.5% Up Spread
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
N/A
N/A
0
1
N/A
N/A
0
1
N/A
N/A
0
1
N/A
N/A
0
1
Bit 6: 0 = Hardware select; 1 = I2C select. Default is OFF.
Bit 7: 0 = Spread off; 1 = Spread spectrum enable. Default is OFF
Third party brands and names are the property of their respective owners.
6
ICS94229
Advance Information
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
PCICLK7
Bit 7 42, 41
Bit 6 39, 38
1
1
1
1
1
1
1
1
CPUCLKT0, CPUCLKC0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
18
17
16
14
13
11
10
1
1
1
1
1
1
1
1
CPUCLK_CST0, CPUCLK_CSC0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
7
48MHz
24_48MHz
FS0 (readback)
AGP2
-
28
27
26
AGP1
AGP0
Byte 4: Watch Dog Register
(1= enable, 0 = disable)
Byte 3: PCI, REF, Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN# PWD
DESCRIPTION
Watch dog enable
0: stop
1: start
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
PCICLK_F
9
22
-
1
1
1
1
1
1
1
1
Bit 7
-
0
PCICLK9_E
FS1 (readback)
PCICLK8
REF_F
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
0
0
0
0
1
0
0
M/N program enable
21
46
-
The decimal representation of
these 8 bits correspond to 290ms
or 1ms the watchdog timer will
wait before it goes to alarm mode
and reset the frequency to the safe
setting. Default at power up is 4X
580ms = 2.3 seconds.
FS2 (readback)
REF1
47
48
REF0
Byte 5: Vendor Specific Feature, Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Vendor ID1 , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
SEL24_48# (readback)
FS3 (readback)
Bit 7
Bit 6
-
-
0
0
BIT PIN# PWD
DESCRIPTION
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
1
0
0
0
1
Watchdog status:
0=Normal 1=Alarm
Bit 5
-
0
Device ID
Vendor ID
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
1
1
1
1
0
SSB1
FS3
FS2
FS1
FS0
Notes:
Note: Don’t write into this register, writing into this
register can cause malfunction
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Watch dog timer is enabled or disabled via latch input
WDEN during power up. User can change watch dog
state with Byte 4 bit 7 after power up condition is
established.
Third party brands and names are the property of their respective owners.
7
ICS94229
Advance Information
Byte 7: Vendor ID2, Active/Inactive Register
(1= enable, 0 = disable)
Byte 8: Byte Count Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
0
0
0
0
1
0
1
WDEN (readback)
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 9: VCO Frequency Control Register
(1= enable, 0 = disable)
Byte 10: VCO Frequency Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
VCO Divder Bit 0
REF Divder Bit 6
REF Divder Bit 5
REF Divder Bit 4
REF Divder Bit 3
REF Divder Bit 2
REF Divder Bit 1
REF Divder Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
VCO Divider Bit 8
VCO Divider Bit 7
VCO Divider Bit 6
VCO Divider Bit 5
VCO Divider Bit 4
VCO Divider Bit 3
VCO Divider Bit 2
VCO Divider Bit 1
Byte 11: VCO Spread Spectrum Control Register
(1= enable, 0 = disable)
Byte 12: VCO Spread Spectrum Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Spread Spectrum Bit 7
Spread Spectrum Bit 6
Spread Spectrum Bit 5
Spread Spectrum Bit 4
Spread Spectrum Bit 3
Spread Spectrum Bit 2
Spread Spectrum Bit 1
Spread Spectrum Bit 0
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
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8
ICS94229
Advance Information
Byte 13: Output Skew Control Register
(1= enable, 0 = disable)
Byte 14: Output Skew Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
1
0
0
0
0
0
CPUCLKC0/T0 Skew Control
PCICLK(8:0) Skew Control
AGP(2:0) Skew Control
CPUCLKC_CST/C Skew Control
PCICLK9_E: Slew Rate Control
Byte 15: Output Rise/Fall Time Select Register
(1= enable, 0 = disable)
Byte 16: Output Rise/Fall Time Select Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
CPUCLKT0
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
1
0
0
0
0
0
PCICLK(3:0): Slew Rate Control
CPUCLKC0
CPUCLKT_CST
CPUCLKC_CSC
PCICLK(8:4): Slew Rate Control
48MHz: Slew Rate Control
AGP(2:0): Slew Rate Control
REF(2:0): Slew Rate Control
24_48MHz: Slew Rate Control
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9
ICS94229
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
µA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
IDD3.3OP133 CL = 0 pF; Select @ 133MHz
PD
180
mA
Supply Current
600
16
5
Power Down
A
µ
Input frequency
Fi
VDD = 3.3 V;
12
27
14.318
MHz
pF
CIN
Logic Inputs
Input Capacitance1
Clk Stabilization1
CINX
X1 & X2 pins
45
3
pF
TSTAB
tCPU-PCI
tCPU-AGP
From VDD = 3.3 V to 1% target Freq.
ms
-100
-500
100
500
1Guaranteed by design, not 100% tested in production.
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10
ICS94229
Advance Information
Electrical Characteristics - REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
4
4
ns
ns
%
dt5
55
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
ZO
CONDITIONS
VO = VX
MIN
TYP
MAX
UNITS
Output Impedance
Ω
Termination to
Vpull-up(external)
Termination to
Vpull-up(external)
VOL = 0.3 V
Output High Voltage
Output Low Voltage
VOH2B
VOL2B
1
1.2
0.4
V
V
Output Low Current
Rise Time1
Fall Time1
IOL2B
tr2B
18
mA
ns
VOL = 0.3 V, VOH = 1.2 V
VOH = 1.2 V, VOL = 0.3 V
0.9
0.9
tf2B
ns
V
Vpullup(external)
+ 0.6
Differential voltage-AC1
Differential voltage-DC1
VDIF
Note 2
Note 2
Note 3
0.4
0.2
Vpullup(external)
+ 0.6
VDIF
VX
V
Differential Crossover
Voltage1
Duty Cycle1
Skew1
Jitter, Cycle-to-cycle1
Jitter, Absolute1
Notes:
550
45
1100
mV
dt2B
tsk2B
tjcyc-cyc2B
tjabs2B
VT = 50%
VT = 50%
VT = VX
55
200
250
+250
%
ps
ps
ps
VT = 50%
-250
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
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11
ICS94229
Advance Information
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.6
TYP MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-16
V
IOH1
mA
mA
IOL1
19
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
2
2
ns
ns
%
ps
dt1
55
500
Skew1(window)
1
Tsk
VT = 1.5V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.6
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-12
V
IOH1
mA
mA
IOL1
12
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
2
2
ns
ns
%
ps
dt1
55
200
Skew1(window)
1
Tsk
VT = 1.5V
1Guaranteed by design, not 100% tested in production.
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12
ICS94229
Advance Information
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
4
4
ns
ns
%
ns
ns
dt5
45
-1
55
0.5
1
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
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13
ICS94229
Advance Information
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output), serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
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14
ICS94229
Advance Information
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP clocks. for low power operation.
AGP_STOP# is synchronized by the ICS94229. The AGPCLKs will always be stopped in a low state and start in such a manner
that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and AGPCLK off latency is less
than 3 AGPCLKs. This function is available only with MODE pin latched low.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. AGP_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS4229.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS94229. All other clocks will continue to run while the CPUCLKs clocks are disabled.
The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full
pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PD# (High)
CPUCLKT
CPUCLKT_CST
CPUCLKC
CPUCLKC_CSC
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPUCLKs inside the ICS94229.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
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15
ICS94229
Advance Information
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94229 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94229. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94229 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high
pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PCICLK
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94229 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94229.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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16
ICS94229
Advance Information
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS94229yF-T
Example:
ICS XXXX y F -T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
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17
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