ICS948AI147L [ICSI]
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER; 低偏移， 1到12差分至LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS948AI147L |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER |
| 文件： | 总11页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS83948I-147 is a low skew, 1-to-12
• Twelve LVCMOS/LVTTL outputs
ICS
HiPerClockS™
Differential-to-LVCMOS/LVTTL Fanout Buffer and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS83948I-147 has two selectable clock inputs.
• Selectable LVCMOS/LVTTL clock
or differential CLK, nCLK inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
The CLK, nCLK pair can accept most standard differential
input levels. The LVCMOS_CLK can accept LVCMOS or
LVTTL input levels.The low impedance LVCMOS/LVTTL out-
puts are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased
from 12 to 24 by utilizing the ability of the outputs to drive two
series terminated lines.
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Output frequency: 350MHz (maximum)
• Output skew (at 3.3V 5ꢀ): 100ps (maximum)
• Part-to-part skew (at 3.3V 5ꢀ): 1ns (maximum)
• Full 3.3V or full 2.5V operating supply
The ICS83948I-147 is characterized at full 3.3V or full 2.5V
operating supply modes. Guaranteed output and part-to-part
skew characteristics make the ICS83948I-147 ideal for those
clock distribution applications demanding well defined per-
formance and repeatability.
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
LE
32 31 30 29 28 27 26 25
LVCMOS_CLK
1
0
GND
Q4
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK_SEL
LVCMOS_CLK
CLK
Q0
CLK
nCLK
VDDO
Q5
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
nCLK
CLK_SEL
ICS83948I-147
GND
Q6
CLK_EN
OE
VDDO
Q7
VDD
GND
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
TopView
OE
83948AYI-147
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REV.B NOVEMBER 21, 2005
1
ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Clock select input. Selects LVCMOS_CLK input when HIGH.
Selects CLK, nCLK inputs when LOW.
1
CLK_SEL
Input
Pullup
LVCMOS/LVTTL interface levels
2
3
4
5
6
7
LVCMOS_CLK
CLK
Input
Input
Pullup
Pullup
Clock input. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
nCLK
Input Pulldown Inverting differential clock input.
CLK_EN
OE
Input
Input
Pullup
Pullup
Clock enable. LVCMOS/ LVTTL interface levels.
Output enable. LVCMOS/LVTTL interface levels.
Power supply pin.
VDD
Power
8, 12, 16,
20, 24, 28, 32
9, 11, 13, 15,
17, 19, 21, 23
25, 27, 29, 31
10, 14, 18,
GND
Power
Output
Power
Power supply ground.
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Clock outputs. LVCMOS/LVTTL interface levels.
Output supply pins.
VDDO
22, 26, 30
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
12
pF
RPULLUP
Input Pullup Resistor
51
51
7
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
5
12
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
0
1
CLK, nCLK inputs selected
LVCMOS_CLK input selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
CLK
nCLK
Q0:Q11
LOW
0
0
0
0
0
0
1
1
—
—
—
—
—
—
0
0
1
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
0
1
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
LOW
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
HIGH
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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REV.B NOVEMBER 21, 2005
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ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
55
Units
V
VDD
VDDO
IDD
Power Supply Voltage
Output Supply Voltage
Power Supply Current
3.135
3.3
V
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD =VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
52
Units
V
VDD
VDDO
IDD
Power Supply Voltage
Output Supply Voltage
Power Supply Current
2.375
2.5
V
mA
TABLE 4C. DC CHARACTERISTICS, VDD =VDDO = 3.3V 5ꢀ, TA = -40° TO 85°
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIN
Input High Voltage
LVCMOS
LVCMOS
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
Input Current
VIN = VDD or VIN = GND
IOH = -24mA
300
µA
V
VOH
Output High Voltage; NOTE 1
2.4
IOL = 24mA
0.55
0.30
1.3
V
VOL
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
IOL = 12mA
V
VPP
CLK, nCLK
CLK, nCLK
0.15
V
Input Common Mode Voltage;
NOTE 2, 3
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2.
See Parameter Measurement section, "3.3V Output Load AC Test Circuit".
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 3: Common mode voltage is defined as VIH.
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REV.B NOVEMBER 21, 2005
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ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4D. DC CHARACTERISTICS, VDD =VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS
LVCMOS
1.7
VDD + 0.3
0.7
V
V
Input Low Voltage
-0.3
IIN
Input Current
VIN = VDD or VIN = GND
IOH = -15mA
300
µA
V
VOH
VOL
VPP
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
1.8
IOL = 15mA
0.6
1.3
V
CLK, nCLK
CLK, nCLK
0.15
V
Input Common Mode Voltage;
NOTE 2, 3
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2.
See Parameter Measurement section, "2.5V Output Load AC Test Circuit".
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 3: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
MHz
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
IJ 350MHz
IJ 350MHz
2
2
4
ns
Propagation
Delay;
tPD
4
ns
ps
Measured on
rising edge @VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
100
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
1
ns
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.8V to 2V
0.2
45
1.0
55
5
ns
ꢀ
IJ 150MHz, Ref = CLK, nCLK
50
tPZL, tPZH Output Enable Time; NOTE 5
tPLZ, tPHZ Output Disable Time; NOTE 5
ns
ns
5
CLK_EN to
CLK, nCLK
1
0
0
1
ns
ns
ns
ns
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
CLK, nCLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
83948AYI-147
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REV.B NOVEMBER 21, 2005
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ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
MHz
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
f ≤ 350MHz
f ≤ 350MHz
1.5
1.7
4.2
ns
Propagation
Delay;
tPD
4.4
ns
ps
Measured on
rising edge @VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
160
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
2
ns
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.6V to 1.8V
0.1
40
1.0
60
5
ns
ꢀ
IJ 150MHz, Ref = CLK, nCLK
tPZL, tPZH Output Enable Time; NOTE 5
tPLZ, tPHZ Output Disable Time; NOTE 5
ns
ns
5
CLK_EN to
CLK, nCLK
1
0
0
1
ns
ns
ns
ns
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
CLK, nCLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
83948AYI-147
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REV.B NOVEMBER 21, 2005
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ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD
,
VDD
,
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
VDDO
Qx
2
nCLK
VPP
VCMR
Cross Points
VDDO
CLK
Qy
2
tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
VDDO
PART 1
VDDO
2
Q0:Q11
Qx
2
tPW
tPERIOD
PART 2
Qy
VDDO
2
tPW
x 100ꢀ
tsk(pp)
odc =
tPERIOD
odc & tPERIOD
PART-TO-PART SKEW
VDD
2V
2V
2
LVCMOS_CLK
VDD = VDDO = 3.3V
0.8V
0.8V
Clock
Outputs
nCLK
CLK
tR
tF
1.8V
tF
1.8V
tR
VDDO
2
VDD = VDDO = 2.5V
Q0:Q11
0.6V
0.6V
➤
Clock
Outputs
tPD
➤
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
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ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUT:
CLK INPUT:
All unused LVCMOS output can be left floating. We
For applications not requiring the use of a clock input, it can recommend that there is no trace attached.
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
83948AYI-147
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REV.B NOVEMBER 21, 2005
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ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOWTABLE FOR 32 LEAD LQFP
θ
JA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83948I-147 is: 1040
Pin compatible with the MPC9448
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REV.B NOVEMBER 21, 2005
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ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE -Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
REFERENCE DOCUMENT:JEDEC PUBLICATION 95, MS-026
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REV.B NOVEMBER 21, 2005
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ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS83948AYI-147
ICS83948AYI-147T
ICS83948AYI-147LF
ICS83948AYI-147LFT
ICS83948AI147
ICS83948AI147
ICS948AI147L
ICS948AI147L
32 Lead LQFP
tray
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
32 Lead LQFP
1000 tape & reel
tray
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83948AYI-147
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REV.B NOVEMBER 21, 2005
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ICS83948I-147
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
1
2
Description of Change
Features Sectiton - added Lead-Free bullet.
Pin Chararcteristics Table - changed CIN from 4pF max. to 4pF typical; and
added 5Ω min. and 12Ω max to ROUT
Updated Single Ended Signal Driving Differential Input diagram
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number, marking, and note.
Date
T2
.
B
11/21/05
7
T8
10
83948AYI-147
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REV.B NOVEMBER 21, 2005
11
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