ICS950818 [ICSI]
Frequency Generator with 200MHz Differential CPU Clocks; 频率发生器，差分200MHz的CPU时钟
| 型号： | ICS950818 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator with 200MHz Differential CPU Clocks |
| 文件： | 总20页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS950818
Integrated
Circuit
Systems,Inc.
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
Pin Configuration
CK-408 clock for Brookdale/Odem/Montara-GM for P4/Banias
processor.
X1 1
48 VDDREF
X2 2
47 REF
GND 3
46 FS1
Output Features:
PCICLK_F0/PCICLK6 4
PCICLK_F1/PCICLK7 5
PCICLK_F2/PCICLK8 6
GND 7
45 CPU_STOP#
44 VDDCPU
43 CPUCLKT0
42 CPUCLKC0
41 GND
•
•
2 - Differential CPU Clock Pairs @ 3.3V
8 - PCI (3.3V) @ 33.3MHz including 2 1x/2x
selectable PCI clocks
•
•
•
•
•
3 - PCI_F/PCI selectable (3.3V) @ 33.3MHz
1 - USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
1 - REF (3.3V) @ 14.318MHz
PCICLK0 8
PCICLK1 9
40 VDDCPU
39 CPUCLKT1
38 CPUCLKC1
37 IREF
*PCICLK2 10
VDDPCI 11
4 - 3V66 (3.3V) @ 66.6MHz
1 - VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
*PCICLK3 12
PCICLK4 13
PCICLK5 14
VDD3V66 15
GND 16
Features:
36 FS0
35 48MHz_USB
34 48MHz_DOT
33 VDD48
•
Selectable 1X or 2X strength for REF and PCI via
SMBus interface
•
•
•
Programmable group to group skew
Linear programmable frequency and spreading %
3V66_2 17
32 GND
3V66_3 18
31 3V66_1/VCH_CLK
30 PCI_STOP#
29 PCICLK10
28 VDD3V66
27 GND
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
3V66_4 19
PCICLK9 20
PD# 21
•
•
Uses external 14.318MHz crystal
Stop clocks and functional control available through
SMBus interface.
VDDA 22
GND 23
26 SCLK
Key Specifications:
Vtt_PWRGD# 24
25 SDATA
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
48-Pin 6.10 mm. Body, 0.50 mm. pitch TSSOP
*These outputs have selectable 1X/2X strength via SMBus
Block Diagram
Frequency Select Table 1
Freq
48MHz_USB
48MHz_DOT
Sel
PLL2
3V66(4:1)
MHz
USB/DOT
MHz
CPU MHz
PCI MHz
REF MHz
FS FS
1
0
X1
X2
XTAL
OSC
0
0
1
1
0
1
0
1
100.00
166.67
133.33
200.00
66.66
66.66
66.66
66.66
33.33
33.33
33.33
33.33
14.318
14.318
14.318
14.318
48.008
48.008
48.008
48.008
3V66 (4:2)
REF
PLL1
Spread
Spectrum
CPUCLKT (1:0)
CPUCLKC (1:0)
CPU
DIVDER
3
3
Stop
Stop
PCI
DIVDER
PCICLK (10:0)
PCICLK_F (2:0)
Vtt_PWRGD#
PD#
7
3
Control
Logic
3V66
DIVDER
CPU_STOP#
PCI_STOP#
FS (1:0)
3V66_1/VCH_CLK
I REF
Config.
Reg.
SDATA
SCLK
0825F—11/19/03
ICS950818
Pin Description
PIN # PIN NAME
PIN TYPE
IN
DESCRIPTION
1
X1
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
2
X2
OUT
PWR
OUT
OUT
OUT
PWR
OUT
OUT
OUT
PWR
I/O
3
GND
4
PCICLK_F0/PCICLK6
PCICLK_F1/PCICLK7
PCICLK_F2/PCICLK8
GND
Free running/Non-Free running PCI clock selected by SMBus.
Free running/Non-Free running PCI clock selected by SMBus.
Free running/Non-Free running PCI clock selected by SMBus.
Ground pin.
5
6
7
8
PCICLK0
PCICLK1
*PCICLK2
VDDPCI
PCI clock output.
9
PCI clock output.
10
11
12
13
14
15
16
17
18
19
20
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
*PCICLK3
PCICLK4
PCICLK5
VDD3V66
GND
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PCI clock output.
PCI clock output.
Power pin for the 3V66 clocks.
Ground pin.
3V66_2
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
PCI clock output.
3V66_3
3V66_4
PCICLK9
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal
are stopped.
21
PD#
IN
22
23
VDDA
GND
PWR
PWR
3.3V power for the PLL core.
Ground pin.
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.
24
Vtt_PWRGD#
IN
0825F—11/19/03
2
ICS950818
Pin Description (Continued)
PIN # PIN NAME
PIN TYPE
DESCRIPTION
25
26
27
28
29
SDATA
SCLK
I/O
IN
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Ground pin.
GND
PWR
PWR
OUT
VDD3V66
PCICLK10
Power pin for the 3V66 clocks.
PCI clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input
low
30
PCI_STOP#
IN
31
32
33
34
35
36
3V66_1/VCH_CLK
GND
OUT
PWR
PWR
OUT
OUT
IN
3.3V 66.66MHz clock output / 48MHz VCH clock output.
Ground pin.
VDD48
Power pin for the 48MHz output.3.3V
48MHz clock output.
48MHz clock output.
Frequency select pin.
48MHz_DOT
48MHz_USB
FS0
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
37
IREF
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
38
39
CPUCLKC1
CPUCLKT1
OUT
OUT
40
41
VDDCPU
GND
PWR
PWR
Ground pin.
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
42
43
CPUCLKC0
CPUCLKT0
OUT
OUT
44
45
46
47
48
VDDCPU
CPU_STOP#
FS1
PWR
IN
Stops all CPUCLK besides the free running clocks
Frequency select pin.
IN
REF
OUT
PWR
14.318 MHz reference clock.
VDDREF
Ref, XTAL power supply, nominal 3.3V
Power Supply
Pin Number
Description
VDD
48
GND
3
Xtal, Ref
PCICLK outputs
3V66
11
7
15, 28
22
16, 27
23
Master clock, CPU Analog
48MHz, Fix Digital, Fix Analog
Inputs
33
32
41
40, 44
41
CPUCLK clocks
0825F—11/19/03
3
ICS950818
Default Setup of Byte 11-17
Bytes
14
17
17
17
18
18
18
CPU (MHz)
100.00
100.00
100.00
100.00
SS%
0
11
8E
8D
90
8E
8E
8E
12
B7
9A
ED
B7
B7
B7
13
F8
F2
EE
0A
06
15
15
94
94
94
94
94
94
16
95
95
95
95
95
95
17
0F
0F
0F
0F
0F
0F
0 to -0.5%
0 to -1%
+/- 0.25%
+/- 0.50%
+/- 1.0%
100.00
100.00
Bytes
14
27
27
27
28
28
28
CPU (MHz)
166.66
166.66
166.66
166.66
SS%
0
11
87
87
86
87
87
87
12
9B
9A
6B
9B
9B
9B
13
F8
EE
E5
15
10
28
15
A4
A4
A4
A4
A4
A4
16
A6
A6
A6
A6
A6
A6
17
0F
0F
0F
0F
0F
0F
0 to -0.5%
0 to -1%
+/- 0.25%
+/- 0.50%
+/- 1.0%
166.66
166.66
Bytes
14
1F
1F
1F
20
20
20
CPU (MHz)
133.33
133.33
133.33
133.33
SS%
0
11
86
8B
87
86
86
86
12
22
DB
46
22
22
22
13
F9
F0
EB
10
0C
1F
15
C4
C4
C4
C4
C4
C4
16
C8
C8
C8
C8
C8
C8
17
0F
0F
0F
0F
0F
0F
0 to -0.5%
0 to -1%
+/- 0.25%
+/- 0.50%
+/- 1.0%
133.33
133.33
Bytes
14
2F
2F
2F
30
30
30
CPU (MHz)
200.00
200.00
200.00
200.00
SS%
0
11
86
86
84
86
86
86
12
B7
B6
46
B7
B7
B7
13
FB
F0
E4
1D
17
34
15
D4
D4
D4
D4
D4
D4
16
D9
D9
D9
D9
D9
D9
17
0F
0F
0F
0F
0F
0F
0 to -0.5%
0 to -1%
+/- 0.25%
+/- 0.50%
+/- 1.0%
200.00
200.00
0825F—11/19/03
4
ICS950818
BYTE
0
Affected Pin
Name
Bit Control
Control Function
Type
RW
Pin #
-
0
1
PWD
0
Bit 7
Spread Enabled
Spread Spectrum Control
Power down mode output level
0= CPU driven in power down
1= undriven
OFF
ON
Bit 6
-
CPUCLKT(1:0)
RW
x2 IREF
Hi-Z
0
Bit 5
Bit 4
31
44
3V66_1/VCH_CLK
CPU_STOP#
VCH/66.66 Select
RW
R
66.66
Stop
48.00
Active
0
X
Reflects value of pin
Reflects value of pin at power up.
Also can be set.
Bit 3
30
PCI_STOP#
RW
Stop
Active
X
Bit 2
Bit 1
Bit 0
-
46
36
-
(Reserved)
Frequency Selection
Frequency Selection
R
R
R
-
-
-
-
-
-
X
X
X
FS1
FS0
Note: For PCI_STOP# function, refer to table 2.
BYTE
1
Affected Pin
Name
Bit Control
Control Function
Type
R
Pin #
-
0
-
1
-
PWD
X
Bit 7
-
(Reserved)
CPU_Stop mode output level
0= CPU driven when stopped
1 = undriven
Bit 6
-
CPUCLKT(1:0)
RW
x2 IREF
Hi-Z
0
CPUCLKT1, CPUCLKC1
(see note)
CPUCLKT0, CPUCLKC0
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
(Reserved)
Not
Freerun
Not
Freerun
-
Bit 5
Bit 4
39, 38
43, 42
RW
RW
Freerun
0
0
Freerun
-
(see note)
Bit 3
Bit 2
Bit 1
Bit 0
-
-
R
X
1
1
X
39, 38
43, 42
-
CPUCLKT1, CPUCLKC1
CPUCLKT0, CPUCLKC0
-
Output control
Output control
(Reserved)
RW
RW
R
Disable Enable
Disable Enable
-
-
Note: CPUCLK(1:0) can be turned on/off by CPU_STOP#. Refer to table 3.
BYTE
2
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
47
14
13
12
-
10
9
8
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF
1X or 0.5X Strength control
Output control
Output control
Output control
Reserved
RW
RW
RW
RW
X
RW
RW
RW
1X
0.5X
0
1
1
1
1
1
1
1
PCICLK5
PCICLK4
*PCICLK3
-
*PCICLK2
PCICLK1
PCICLK0
Disable Enable
Disable Enable
Disable Enable
-
-
Output control
Output control
Output control
Disable Enable
Disable Enable
Disable Enable
Note: PCICLK(5:0) can be turned on/off by PCI_STOP#. Refer to table 2.
0825F—11/19/03
5
ICS950818
BYTE
3
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
34
35
0
1
PWD
Bit 7
Bit 6
48MHz_DOT
48MHz_USB
Output control
Output control
RW
RW
Disable Enable
Disable Enable
1
1
PCICLK_F2/PCICLK8 (see
note)
PCICLK_F1/PCICLK7 (see
note)
PCICLK_F0/PCICLK6 (see
note)
Allow control of output with
assertion of PCI_STOP#.
Allow control of output with
assertion of PCI_STOP#.
Allow control of output with
assertion of PCI_STOP#.
Output control
Not
Freerun
Not
Freerun
Not
Freerun
Bit 5
Bit 4
Bit 3
6
5
4
RW
RW
RW
Freerun
0
0
0
Freerun
Freerun
Bit 2
Bit 1
Bit 0
6
5
4
PCICLK_F2/PCICLK8
PCICLK_F1/PCICLK7
PCICLK_F0/PCICLK6
RW
RW
RW
Disable Enable
Disable Enable
Disable Enable
1
1
1
Output control
Output control
Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 4.
BYTE
4
Affected Pin
Name
*PCICLK2
*PCICLK3
PCICLK10
3V66_1/VCH_CLK
PCICLK9
Bit Control
Control Function
Type
Pin #
10
12
29
31
20
19
18
17
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output strength (1X/2X)
Output strength (1X/2X)
Output control
R/W
R/W
RW
RW
RW
RW
RW
RW
2X
2X
1X
1X
1
1
1
1
1
1
1
1
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Output control
Output control
Output control
Output control
3V66_4
3V66_3
3V66_2
Output control
BYTE
5
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
X
0
OFF
-
1
PWD
Allow Iref Mirror to be ON during
Power Down Mode
Bit 7
Bit 6
Bit 5
PD Mode Iref Mirror Enable
Reserved
RW
X
ON
0
0
0
X
Reserved
-
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
00 = Medium (default), 01 = Low,
11,10 =High
Not
Freerun
X
3V66(4:2) (See table 6)
X
Freerun
Not
Freerun
Bit 4
X
3V66(1) (See table 7)
X
Freerun
0
Bit 3
Bit 2
Bit 1
RW
RW
RW
-
-
-
-
-
-
0
0
0
34
48MHz_DOT Slew Control
00 = Medium (default), 01 = Low,
11,10 =High
35
48MHz_USB Slew Control
Bit 0
RW
-
-
0
Functions in Byte 5 of CK408 were intended as a test and debug byte only.
Note:
0825F—11/19/03
6
ICS950818
BYTE
6
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
X
X
X
X
X
X
X
X
0
1
-
-
-
-
-
-
-
-
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
1
Revision ID Value Based on
Device Revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
BYTE
7
Affected Pin
Bit Control
Control Function
Type
Pin #
X
X
X
X
Name
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
0
X
X
X
X
BYTE
8
Affected Pin
Bit Control
Control Function
(Reserved)
Type
X
Pin #
X
Name
-
0
-
1
-
PWD
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
X
X
X
X
X
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
X
X
X
R
R
-
-
-
-
-
-
-
-
-
-
0
0
0
1
1
Readback Byte Count
Bit 1
Bit 0
X
X
-
-
R
R
-
-
-
-
1
1
Note: Byte 8 is for ICS test only. Do not write as system damage may occur. Bit(3:0) contain the readback Byte count.
BYTE
9
Affected Pin
Name
Bit Control
Control Function
Type
Pin #
X
0
1
-
PWD
Bit 7
Bit 6
Bit 5
-
-
-
(Reserved)
(Reserved)
(Reserved)
X
X
X
-
-
-
0
0
0
X
X
-
-
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0825F—11/19/03
7
ICS950818
BYTE
10
Affected Pin
Name
Bit Control
Control Function
Type
RW
Pin #
X
0
1
PWD
0
M/N Enable (Enable access to
Byte 11 - 14)
(Reserved)
Byte
(11-14)
Bit 7
-
HW/B0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
X
X
X
X
X
X
-
-
-
-
-
-
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
0
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Bit 0
X
-
(Reserved)
X
-
-
0
BYTE
11
Bit 7
Affected Pin
Bit Control
Control Function
VCO Divider Bit8
Type
RW
Pin #
X
Name
-
0
-
1
-
PWD
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Note: The decimal representation of these 7 bits (Byte 11 bit[6:0]) + 2 is equal to the REF divider value.
BYTE
12
Affected Pin
Name
Bit Control
Control Function
VCO Divider Bit7
Type
RW
Pin #
X
0
-
1
-
PWD
X
Bit 7
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
VCO Divider Bit0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Note: The decimal representation of these 9 bits (Byte 12 bit[7:0]) and Byte 11 bit [7]) + 8 is equal to the VCO divider value.
BYTE
13
Affected Pin
Name
Bit Control
Control Function
Type
RW
Pin #
X
0
1
-
PWD
X
Bit 7
-
Spread Spectrum Bit7
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread
percentage may cause system failure.
0825F—11/19/03
8
ICS950818
BYTE
14
Affected Pin
Name
Bit Control
Control Function
(Reserved)
Type
RW
Pin #
X
0
1
-
PWD
X
Bit 7
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
-
-
-
-
-
-
-
(Reserved)
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Spread Spectrum Bit13
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bit9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread
percentage may cause system failure.
0825F—11/19/03
9
ICS950818
Table 2
PCI_STOP# SMBus Control Table-Byte 0, Bit 3
PCI_STOP#
(Pin 30)
Byte 0 Bit 3
Write Bit
Byte 0, Bit 3 Read Bit
(Internal Status)
0
0
1
1
0
1
0
1
0
0
0
1`
When this Byte 0, Bit 3 is low (0), all PCI clocks are stopped.
Note:
Table 3
CPUCLKT/C (1:0) Outputs SMBus Control Table
CPU_STOP#
(Pin 45)
Byte 1
Bit 4, 5
CPUCLKT/C (1:0) Outputs
0
0
1
1
0
1
0
1
Stop
Running
Running
Running
Individual CPUCLK outputs are controlled by Byte 1, Bit 4, and 5.
Note:
Table 4
PCICLK_F (2:0) Outputs SMBus Control Table
PCI_STOP#
(Pin 30)
Byte 3
Bit 3, 4, 5
PCICLK (2:0) Outputs
0
0
Stop
0
1
1
1
0
1
Running
Running
Running
Individual PCICLK outputs are controlled by Byte 3, Bit 3, 4, and 5.
Note:
Table 5
3V66 (4:2) SMBus Control Table
CPU_STOP#
(Pin 45)
Byte 5
Bit 5
3V66 (4:2)
0
0
1
1
0
1
0
1
Running
Stopped
Running
Running
Activating Byte 5, Bit 5 will allow CPU_STOP# to control stop of pins 17, 18, and 19
Note:
Table 6
3V66 (1) SMBus Control Table
CPU_STOP#
(Pin 45)
Byte 5
Bit 4
3V66 (1)
0
0
1
1
0
1
0
1
Running
Stopped
Running
Running
Activating Byte 5, Bit 4 will allow CPU_STOP# to control stop of pins 31.
Note:
0825F—11/19/03
10
ICS950818
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +90°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 90°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
V
VIL
VSS-0.3
VIN = VDD; Inputs with no pull-down
resistors
IIH
IIH
5.75
200
mA
Input High Current
Input Low Current
VIN = VDD; Inputs with pull-down
resistors
µA
VIN = 0 V; Inputs with no pull-up
resistors
IIL1
-5.75
-200
mA
µA
VIN = 0 V; Inputs with pull-up
resistors
IIL2
IDD3.3OP
IDD3.3OP
CL = Full load; Select @ 100 MHz
182
189
280
280
mA
mA
Operating Supply Current
Powerdown Current
CL =Full load; Select @ 133 MHz
IREF=5 mA
IDD3.3PD
IDD3.3PDHIz
Fi
14
9
52
mA
mA
MHz
nH
0.5
Input Frequency
Pin Inductance
VDD = 3.3 V
14.32
Lpin
7
5
CIN
Logic Inputs
pF
Input Capacitance1
COUT
CINX
Output pin capacitance
6
pF
X1 & X2 pins
27
45
pF
From PowerUp or deassertion of
PowerDown to 1st clock.
Clk Stabilization1,2
Delay1
TSTAB
2.1
ms
tPZH,tPZL
Output enable delay (all outputs)
1
1
12
12
ns
ns
t
PHZ,tPLZ
Output disable delay (all outputs)
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
0825F—11/19/03
11
ICS950818
Electrical Characteristics - CPU (0.7V Select) 100MHz
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP MAX UNITS
VO = Vx
3000
-
Ω
ns
Average Period
Voltage High
Voltage Low
Max Voltage
Min Voltage
TPERIOD
VHigh
VLow
Vovs
Fig. 1
10.00 10.02 10.20
Statistical measurement on single ended signal
using oscilloscope math function.
Measurement on single ended signal using
absolute value.
660 757.1
-150 9.067
850
150
mV
774.7 1150
3
mV
Vuds
-450
Crossing Voltage (abs) Vcross(abs)
Fig. 3
250 386.1
41.57
550
140
810
mV
mV
ps
Crossing Voltage (var)
Rise Time
d-Vcross
Variation of crossing over all edges (Fig. 4)
VOL = 0.175V, VOH = 0.525V (Fig. 3)
tr
175 552.8
Fall Time
tf
VOH = 0.525V VOL = 0.175V (Fig. 3)
175 558.7
34.25
810
125
125
55
ps
ps
ps
%
Rise Time Variation
Fall Time Variation
Duty Cycle
d-tr
d-tf
dt3
tsk3
45.5
Measurement from differential wavefrom (Fig 1)
VT = 50%
45
50.58
60.5
Skew
100
175
ps
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 50% (Fig. 1)
65.25
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU (0.7V Select) 133.33MHz
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP MAX UNITS
VO = Vx
3000
-
Ω
ns
Average Period
Voltage High
Voltage Low
Max Voltage
Min Voltage
TPERIOD
VHigh
VLow
Vovs
Fig. 1
7.50
660
-150
7.58
757
9
7.65
850
150
Statistical measurement on single ended signal
using oscilloscope math function.
Measurement on single ended signal using
absolute value.
mV
775
3
1150
mV
Vuds
-450
250
Crossing Voltage (abs) Vcross(abs)
Crossing Voltage (var)
Fig. 3
386
42
550
140
mV
mV
d-Vcross
Variation of crossing over all edges (Fig. 4)
Rise Time
tr
VOL = 0.175V, VOH = 0.525V (Fig. 3)
VOH = 0.525V VOL = 0.175V (Fig. 3)
175
175
553
559
810
810
ps
ps
Fall Time
tf
Rise Time Variation
Fall Time Variation
d-tr
d-tf
34
46
125
125
ps
ps
Duty Cycle
dt3
Measurement from differential wavefrom (Fig 1)
45
51
55
%
Skew
tsk3
VT = 50%
61
65
100
175
ps
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 50% (Fig. 1)
1Guaranteed by design, not 100% tested in production.
0825F—11/19/03
12
ICS950818
Electrical Characteristics - 3V66
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Average Period
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
12
TYP
64.50
MAX UNITS
1
65
RDSP1
TPERIOD
Ω
ns
V
Fig. 8
15.00 15.01 15.30
1
IOH = -1 mA
Output High Voltage
Output Low Voltage
2.05
3.24
0.06
-90
VOH
1
IOL = 1 mA
0.65
-33
V
VOL
V OH = 1.0 V
1
Output High Current
Output Low Current
IOH
V OH = 3.135 V
-33
26
-14
mA
VOL = 1.95 V
35
1
IOL
VOL = 0.4 V
103
38
2.3
2.3
55
1
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
Rise Time
Fall Time
Duty Cycle
Skew
0.5
0.5
45
1.74
1.45
52.05
13.50
ns
ns
%
tr1
1
tf1
1
dt1
1
VT = 1.5 V
250
ps
ps
tsk1
1
VT = 1.5 V (Fig. 8)
Jitter
158.75 290
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
Fig. 8
MIN
TYP
48.008
52.50
3.24
0.06
-53
MAX UNITS
MHz
1
VO = VDD*(0.5)
20
70
RDSP1
Ω
V
V
1
IOH = -1 mA
2.05
VOH
1
IOL = 1 mA
0.5
-29
VOL
V OH = 1.0 V
1
Output High Current
Output Low Current
mA
mA
IOH
V OH = 3.135 V
-20
-7
VOL = 0.4 V
21
27
1
IOL
VOL 1.95 V
25
0.5
0.5
1
60
1
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
48DOT Rise Time
48DOT Fall Time
0.86
0.86
1.37
1.37
51.10
52.80
1.15
1.15
2.3
2.3
55
ns
ns
ns
ns
%
tr1
1
tf1
1
VCH 48 USB Rise Time
VCH 48 USB Fall Time
48 DOT Duty Cycle
VCH 48 USB Duty Cycle
48 DOT Jitter
tr1
1
1
tf1
1
45
45
dt1
1
VT = 1.5 V (Fig. 8)
VT = 1.5 V (Fig. 8)
55
%
dt1
1
182.63 410
0.13
153.25 410
ps
ns
ps
tjcyc-cyc
1
VT = 1.5 V (0 OR 180 degrees)
USB to DOT Skew
1
tsk1
1
VT = 1.5 V (Fig. 8)
VCH Jitter
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0825F—11/19/03
13
ICS950818
Electrical Characteristics - PCICLK_F, PCICLK 1X
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Average Period
SYMBOL
CONDITIONS
VO = VDD*(0.5)
Fig. 8
MIN
12
TYP
52.50
MAX UNITS
1
65
RDSP1
TPERIOD
Ω
ns
V
30.00 30.03
1
IOH = -1 mA
IOL = 1 mA
Output High Voltage
Output Low Voltage
2.05
3.24
0.06
-90
VOH
1
0.65
-33
V
VOL
V OH = 1.0 V
V OH = 3.135 V
1
Output High Current
Output Low Current
IOH
-33
26
-14
mA
VOL = 1.95 V
35
1
IOL
VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
103
1.79
1.82
51.57
38
2.3
2.3
55
1
Rise Time
Fall Time
0.5
0.5
45
ns
ns
%
tr1
1
tf1
1
Duty Cycle
Skew
dt1
1
VT = 1.5 V
136.00 500
ps
ps
tsk1
1
VT = 1.5 V (Fig. 8)
Jitter,cycle to cyc
1Guaranteed by design, not 100% tested in production.
151.5
290
tjcyc-cyc
Electrical Characteristics - PCICLK (3:2) 2X
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Average Period
SYMBOL
CONDITIONS
VO = VDD*(0.5)
Fig. 8
MIN
TYP
52.5
30.03
3.24
0.06
-100
-17
MAX UNITS
1
RDSP1
TPERIOD
Ω
ns
1
IOH = -1 mA
IOL = 1 mA
Output High Voltage
Output Low Voltage
2.7
-60
60
V
V
VOH
1
0.4
-28
VOL
V
OH = 1.0 V
OH = 3.135 V
OL = 1.95 V
OL = 0.4 V
1
Output High Current
Output Low Current
IOH
V
mA
V
44
1
IOL
V
26
0.5
0.5
45
100
1
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V (Fig. 8)
Rise Time
Fall Time
1.75
1.80
51.95
136
2.3
2.3
55
ns
ns
%
tr1
1
tf1
1
Duty Cycle
Skew
dt1
1
VT = 1.5 V
500
290
ps
ps
tsk1
1
VT = 1.5 V (Fig. 8)
Jitter,cycle to cyc
1Guaranteed by design, not 100% tested in production.
151.5
tjcyc-cyc
0825F—11/19/03
14
ICS950818
Electrical Characteristics - REF (1X select)
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
Fig. 8
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
V OH = 1.0 V
MIN
TYP
MAX UNITS
MHz
14.318
52.50
3.24
0.06
-70
1
20
70
Ω
V
V
RDSP1
1
2.05
VOH
1
0.45
-29
VOL
1
Output High Current
Output Low Current
IOH
V
OH = 3.135 V
VOL = 0.4 V
-25
-12
mA
30
38
1
IOL
VOL 1.95 V
26
1
60
1
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V
Rise Time
Fall Time
Duty Cycle
Jitter
-
2.3
2.3
ns
ns
%
tr1
1
1
1.98
54.50
242
tf1
1
45
55
dt1
1
VT = 1.5 V (Fig. 8)
1200
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF (2X select)
TA = 0 - 90°C; VDD=3.3V +/-5%; CL = 20-40 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
Fig. 8
MIN
2.7
TYP
14.318
52.5
3.24
0.06
-100
-17
MAX UNITS
MHz
Ω
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
RDSP1
1
V
VOH
1
0.4
-60
V
VOL
V
OH = 1.0 V
OH = 3.135 V
OL = 0.4 V
OL 1.95 V
1
Output High Current
Output Low Current
IOH
V
-28
mA
V
44
60
1
IOL
V
26
1
100
1
VOL = 0.4 V, VOH = 2.4 V (Fig. 7)
VOH = 2.4 V, VOL = 0.4 V (Fig. 7)
VT = 1.5 V
Rise Time
Fall Time
Duty Cycle
Jitter
-
2.3
2.3
ns
ns
%
tr1
1
1
1.98
54.70
tf1
1
45
55
dt1
1
VT = 1.5 V (Fig. 8)
242
1200
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0825F—11/19/03
15
ICS950818
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[10:0] and stoppable PCI_F clocks will latch
low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the
next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the SMBus configuration to be stoppable
via assertion of CPU_STOP# are to be stopped after their next transition. When the SMBus Bit 6 of Byte 1 is
programmed to '0' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change
to the output drive current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the
CPU# signal will not be driven . When the SMBus Bit 6 of Byte 1 is programmed to '1' then final state of the stopped
CPU signals is Low, both CPU and CPU# outputs will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT
CPUCLKC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
Group to Group Skews at Common Transition Edges: Unbuffered Mode
GROUP
3V66 to PCI1,2
SYMBOL
CONDITIONS
MIN
TYP MAX
UNITS
ns
S3V66-PCI
3V66 (4:1) leads 33MHz PCI
1.5
2.765 3.5
1Guaranteed by design, not 100% tested in production.
2500ps Tolerance
0825F—11/19/03
16
ICS950818
CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from
the de-assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the
SMBus Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop#
de-assertion.
De-assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUCLKT(2:0)
Tdrive_CPU_STOP# <10ns @ 200mV
*CPUCLKT(2:0)TS
CPUCLKC(2:0)
*Signal TS is CPUCLKT in Tri-State mode
PD# - Assertion (transition from logic "1" to logic "0")
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU
clocks must be held low on their next high to low transitions. When the SMBUS Bit 6 of Byte 0 is programmed to '0'
CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of
Byte 0 is '1' then both CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte
0 = '0', this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than
one clock cycle to complete.
Power Down Assertion of Waveforms
0ns
25ns
50ns
PD#
CPUCLKT 100MHz
CPUCLKC 100MHz
3V66MHz
PCICLK 33MHz
USB 48MHz
REF 14.318MHz
PD# Functionality
PD#
PCICLK_F USB/DOT
CPUCLKT CPUCLKC
3V66
PCICLK
48MHz
33MHz
1
0
Normal
Normal
Float
66MHz
Low
48MHz
Low
iref * Mult
Low
0825F—11/19/03
17
ICS950818
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the
ramping of the power supply until the time that stable clocks are output from the clock chip. If the SMBus Bit 6 of Byte
0 is programmed to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
Test Configuration Diagram
Rs=33 Ohms
5%
TLA
CLK408
CPUCLKT test
point
Rs=33 Ohms
5%
TLB
CPUCLKC test
point
Rp=49.9 Ohms
1%
Rp=49.9 Ohms
1%
Rset=475 Ohms
1%
2pF
5%
2pF
5%
MULTSEL Pin must be High
CPU 0.7V Configuration test load board termination
0825F—11/19/03
18
ICS950818
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0825F—11/19/03
19
ICS950818
6.10 mm. Body, 0.50 mm. Pitch TSSOP
c
N
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
2
E1
e
6.00
6.20
.236
.244
a
0.50 BASIC
0.020 BASIC
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
VARIATIONS
A1
D mm.
D (inch)
N
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
- CC --
48
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-153
b
10-0039
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(20 mil)
(240 mil)
Ordering Information
ICS950818yGT
Example:
ICS95 XXXX y G - T
Designation for tape and reel packaging
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0825F—11/19/03
20
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