ICS951411 [ICSI]
System Clock Chip for ATI RS400 P4TM-based Systems; 系统时钟芯片ATI RS400 P4TM的系统
| 型号： | ICS951411 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | System Clock Chip for ATI RS400 P4TM-based Systems |
| 文件： | 总19页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS951411
Systems, Inc.
System Clock Chip for ATI RS400 P4TM-based Systems
Recommended Application:
Features/Benefits:
ATI RS400 systems using Intel P4TM processors
•
•
•
•
•
2- Programmable Clock Request pins for SRC clocks
Supports CK410 or CK409 frequency table mapping
Spread Spectrum for EMI reduction
Outputs may be disabled via SMBus
External crystal load capacitors for maximum
frequency accuracy
Output Features:
•
•
•
•
•
•
6 - Pairs of SRC/PCI-Express clocks
2 - Pairs of ATIG (SRC/PCI Express*) clocks
3 - Pairs of Intel P4 clocks
3 - 14.318 MHz REF clocks
1 - 48MHz USB clock
1 - 33 MHz PCI clock seed
Key Specifications:
•
•
•
•
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter <125ps
PCI outputs cycle-cycle jitter < 250ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Pin Configuration
Functionality - (CK410# = 0)
CPU
FS_C1 FS_B1 FS_A1
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
X1 1
X2 2
VDD48 3
56 VDDREF
55 GND
0
1
0
1
0
1
0
1
266.66 100.00 33.33 14.318 48.000
133.33 100.00 33.33 14.318 48.000
200.00 100.00 33.33 14.318 48.000
166.66 100.00 33.33 14.318 48.000
333.33 100.00 33.33 14.318 48.000
100.00 100.00 33.33 14.318 48.000
400.00 100.00 33.33 14.318 48.000
0
1
0
1
54 **FS_A/REF0
53 **FS_B/REF1
52 **TEST_SEL/REF2
51 VDDPCI
50 **CK410#/PCICLK0
49 GNDPCI
0
USB_48MHz 4
GND 5
VTT_PWRGD#/PD 6
SCLK 7
1
RESERVED
14.318 48.000
SDATA 8
**FS_C 9
48 *CPU_STOP#
47 CPUCLKT0
46 CPUCLKC0
45 VDDCPU
Functionality - (CK410# = 1)
**CLKREQA# 10
**CLKREQB# 11
SRCCLKT7 12
SRCCLKC7 13
VDDSRC 14
GNDSRC 15
SRCCLKT6 16
SRCCLKC6 17
SRCCLKT5 18
SRCCLKC5 19
GNDSRC 20
VDDSRC 21
SRCCLKT4 22
SRCCLKC4 23
SRCCLKT3 24
SRCCLKC3 25
GNDSRC 26
ATIGCLKT1 27
ATIGCLKC1 28
FS_C1
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
Byte6 FS_B1 FS_A1
bit5
44 GNDCPU
100.00 100.00 33.33 14.318 48.000
200.00 100.00 33.33 14.318 48.000
133.33 100.00 33.33 14.318 48.000
166.67 100.00 33.33 14.318 48.000
200.00 100.00 33.33 14.318 48.000
400.00 100.00 33.33 14.318 48.000
266.67 100.00 33.33 14.318 48.000
333.33 100.00 33.33 14.318 48.000
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
43 CPUCLKT1
42 CPUCLKC1
41 CPUCLKT2_ITP
40 CPUCLKC2_ITP
39 VDDA
38 GNDA
37 IREF
36 GNDSRC
35 VDDSRC
34 SRCCLKT0
33 SRCCLKC0
32 VDDATI
31 GNDATI
30 ATIGCLKT0
29 ATIGCLKC0
0
1
1. FS_C, FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Note: Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor
Pins preceeded by '*' have a 120 Kohm Internal Pull Up resistor
56-pin SSOP & TSSOP
0891E—03/07/05
*Other names and brands may be claimed as the property of others.
Integrated
Circuit
ICS951411
Systems, Inc.
Pin Description
PIN
TYPE
PIN #
PIN NAME
DESCRIPTION
1
2
3
4
5
X1
X2
VDD48
USB_48MHz
GND
IN Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Power pin for the 48MHz output.3.3V
OUT 48.00MHz USB clock
PWR Ground pin.
Vtt_PwrGd# is an active low input used to determine when latched inputs are
ready to be sampled. PD is an asynchronous active high input pin used to put
the device into a low power state. The internal clocks, PLLs and the crystal
oscillator are stopped.
6
VTT_PWRGD#/PD
IN
7
8
9
SCLK
SDATA
**FS_C
IN Clock pin of SMBus circuitry, 5V tolerant.
I/O Data pin for SMBus circuitry, 5V tolerant.
IN Frequency select latch input pin
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
10
11
**CLKREQA#
**CLKREQB#
IN are controlled.
0 = enabled, 1 = tri-stated
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
IN are controlled.
0 = enabled, 1 = tri-stated
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SRCCLKT7
SRCCLKC7
VDDSRC
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR Supply for SRC clocks, 3.3V nominal
PWR Ground pin for the SRC outputs
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR Ground pin for the SRC outputs
PWR Supply for SRC clocks, 3.3V nominal
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR Ground pin for the SRC outputs
GNDSRC
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
GNDSRC
VDDSRC
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
GNDSRC
ATIGCLKT1
ATIGCLKC1
OUT True clock of differential SRC clock pair.
OUT Complementary clock of differential SRC clock pair.
0891E—03/07/05
2
Integrated
Circuit
ICS951411
Systems, Inc.
Pin Description (Continued)
PIN
TYPE
PIN #
PIN NAME
DESCRIPTION
29
30
31
32
33
34
35
36
ATIGCLKC0
ATIGCLKT0
GNDATI
OUT Complementary clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
PWR Ground for ATI Gclocks, nominal 3.3V
PWR Power supply ATI Gclocks, nominal 3.3V
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
PWR Supply for SRC clocks, 3.3V nominal
PWR Ground pin for the SRC outputs
VDDATI
SRCCLKC0
SRCCLKT0
VDDSRC
GNDSRC
This pin establishes the reference current for the differential current-mode
OUT output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
37
IREF
38
39
GNDA
VDDA
PWR Ground pin for the PLL core.
PWR 3.3V power for the PLL core.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
40
41
42
43
CPUCLKC2_ITP
CPUCLKT2_ITP
CPUCLKC1
OUT
OUT
OUT
CPUCLKT1
OUT
44
45
GNDCPU
VDDCPU
PWR Ground pin for the CPU outputs
PWR Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
46
47
CPUCLKC0
CPUCLKT0
OUT
OUT
48
49
*CPU_STOP#
GNDPCI
IN Stops all CPUCLK, except those set to be free running clocks
PWR Ground pin for the PCI outputs
FS Table select latch input pin / 3.3V PCI clock output.
0 = CK410 FS Table, 1 = CK409 FS Table
PWR Power supply for PCI clocks, nominal 3.3V
50
51
**CK410#/PCICLK0
VDDPCI
I/O
TEST_SEL: latched input to select TEST MODE / 14.318 MHz reference clock.
I/O 1 = All outputs are CK410 REF/N test mode
52
**TEST_SEL/REF2
0 = All outputs behave normally.
53
54
55
56
**FS_B/REF1
**FS_A/REF0
GND
I/O Frequency select latch input pin / 14.318 MHz reference clock.
I/O Frequency select latch input pin / 14.318 MHz reference clock.
PWR Ground pin.
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
0891E—03/07/05
3
Integrated
Circuit
ICS951411
Systems, Inc.
General Description
ICS951411 provides a single-chip clocking solution for the ATI RS400-based systems using the latest Intel P4 processors.
ICS951411 is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and also provides highly accurate
SRC clocks for PCI Express support. Two Clock Request pins are provided for Express-CardTM support.
Block Diagram
REF(2:0)
X1
USB_48MHz
XTAL
OSC.
FIXED PLL
DIVIDER
X2
PCICLK0
ATIGCLK(1:0)
SRCCLK(7:3,0)
CPUCLK(2:0)
MAIN PLL
DIVIDERS
CK410#
FS(C:A)
CLKREQA#
CLKREQB#
CONTROL
LOGIC
CPU_STOP#
VTT_PWRGD#/PD
SDATA
SCLK
IREF
Power Groups
Pin Number
Description
VDD
GND
55
56
51
45
Xtal, REF
PCICLK output
49
44
CPUCLK Outputs
SRCCLK outputs
ATIGCLK outputs
Analog, CPU PLL
USB_48MHz output
14, 21, 35 15, 20, 26, 36
32
39
3
31
38
5
0891E—03/07/05
4
Integrated
Circuit
ICS951411
Systems, Inc.
General SMBus serial interface information for the ICS951411
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
starT bit
T
T
starT bit
Slave Address D2(H)
Slave Address D2(H)
WR
WR
WRite
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0891E—03/07/05
5
Integrated
Circuit
ICS951411
Systems, Inc.
Table1: CPU Frequency Selection Table
Bit 4
Bit 3
Bit2 Bit1
FSC FSB
Bit0
FSA
CPU
(MHz)
PCI33
(MHz)
Spread
%
CPU FS4 CPU FS3
(CK410#) (SS_EN)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
266.6667 33.3333
133.3333 33.3333
200.0000 33.3333
166.6668 33.3334
333.3335 33.3334
100.0000 33.3333
400.0000 33.3333
Reserved
266.6667 33.3333
133.3333 33.3333
200.0000 33.3333
166.6668 33.3334
333.3335 33.3334
100.0000 33.3333
400.0000 33.3333
Reserved
No Spread
C
K
4
1
0
-0.5%
100.0000 33.3333
133.3333 33.3333
200.0000 33.3333
166.6668 33.3334
200.0000 33.3333
266.6667 33.3333
400.0000 33.3333
333.3335 33.3334
100.0000 33.3333
133.3333 33.3333
200.0000 33.3333
166.6668 33.3334
200.0000 33.3333
266.6667 33.3333
400.0000 33.3333
333.3335 33.3334
No Spread
C
K
4
0
9
-0.5%
0891E—03/07/05
6
Integrated
Circuit
ICS951411
Systems, Inc.
Table2: SRC & ATIG Frequency Selection Table
SRC(7:3,0),
SRC FS4 SRC Bit2 Bit1 Bit0
(SS_EN) FS3 FS2 FS1 FS0
Spread
SRC
OverClock
ATIG(1:0)
(MHz)
%
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00
100.00
100.00
100.00
101.00
101.00
101.00
101.00
102.00
102.00
102.00
102.00
104.00
104.00
104.00
104.00
100.00
100.00
100.00
100.00
101.00
101.00
101.00
101.00
102.00
102.00
102.00
102.00
104.00
104.00
104.00
104.00
1.00
1.00
1.00
1.00
1.01
1.01
1.01
1.01
1.02
1.02
1.02
1.02
1.04
1.04
1.04
1.04
1.00
1.00
1.00
1.00
1.01
1.01
1.01
1.01
1.02
1.02
1.02
1.02
1.04
1.04
1.04
1.04
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
-0.5%
0891E—03/07/05
7
Integrated
Circuit
ICS951411
Systems, Inc.
SMBus Table: Frequency Select Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
Latched Input or SMBus
Frequency Select
Latched
Inputs
-
Bit 7
FS Source
RW
SMBus
0
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SS_EN
Reserved
CK410#
CPU FS3
CPU FS_C
CPU FS_B
CPU FS_A
Spread Enable
Reserved
CPU Freq Select Bit 4
CPU SS_EN
CPU Freq Select Bit 2
CPU Freq Select Bit 1
CPU Freq Select Bit 0
RW
RW
RW
RW
RW
RW
RW
OFF
Reserved
ON
Reserved
0
X
Latched
0
Latched
Latched
Latched
See Table 1: CPU
Frequency Selection Table
NOTE: Byte 0 bit 6 and Byte 0 bit 3 must BOTH be '1' to enable spread for the PCI $ CPU clocks.
Byte 5 bit 4 must be set to 1 to enable spread for the SRC & ATIGCLKS.
SMBus Table: Output Control Register
Byte 1
Bit 7
Pin #
Name
PCICLK0
CPUCLK2
USB_48MHz
REF0
REF1
REF2
CPUCLK0
CPUCLK1
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
50
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
41,40
4
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
54
53
52
47,46
43,42
SMBus Table: CLKREQB# Output Control Register
Byte 2
Pin #
Name
Control Function
CLKREQB# Controls
SRC7
Type
0
1
PWD
Does not
control
12,13
Bit 7
REQBSRC7
RW
Controls
0
CLKREQB# Controls
Does not
control
Does not
control
Does not
control
16,17
18,19
22,23
24,25
Bit 6
Bit 5
Bit 4
Bit 3
REQBSRC6
REQBSRC5
REQBSRC4
REQBSRC3
RW
RW
RW
RW
Controls
Controls
Controls
Controls
0
0
0
0
SRC6
CLKREQB# Controls
SRC5
CLKREQB# Controls
SRC4
CLKREQB# Controls
SRC3
Does not
control
-
-
Bit 2
Bit 1
Reserved
Reserved
Reserved
Reserved
CLKREQB# Controls
SRC0
RW
RW
Reserved
Reserved
Does not
control
Reserved
Reserved
X
X
34,33
Bit 0
REQBSRC0
RW
Controls
0
NOTE: CPU0_Stop_En (Byte2, bit 2) only exists in devices with REV ID = 2 or higher
0891E—03/07/05
8
Integrated
Circuit
ICS951411
Systems, Inc.
SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register
Byte 3
Bit 7
Pin #
12,13
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
0
1
PWD
SRCCLK7
SRCCLK6
SRCCLK5
SRCCLK4
SRCCLK3
SRCCLK0
Disable
Disable
Disable
Disable
Disable
Disable
Does not
control
Does not
control
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
Master Output control.
Enables or disables
output, regardless of
CLKREQ# inputs.
16,17
18,19
22,23
24,25
34,33
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CLKREQA# Controls
SRC3
CLKREQA# Controls
SRC0
24,25
34,33
REQASRC3
REQASRC0
RW
RW
Controls
Controls
0
0
Bit 1
Bit 0
SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register
Byte 4
Pin #
Name
Control Function
CLKREQA# Controls
SRC7
Type
0
1
PWD
Does not
control
12,13
REQASRC7
RW
Controls
0
Bit 7
CLKREQA# Controls
SRC6
CLKREQA# Controls
SRC5
CLKREQA# Controls
SRC4
Output Enable
These outputs cannot be
controlled by CLKREQ#
pins.
Does not
control
Does not
control
Does not
control
16,17
18,19
22,23
27,28
30,29
REQASRC6
REQASRC5
REQASRC4
ATIGCLK1
ATIGCLK0
RW
RW
RW
RW
RW
Controls
Controls
Controls
Enabled
Enabled
0
0
0
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Disabled
Disabled
CPU, SRC, Differential Output
Hi-Z or driven when
disabled
RW
Driven
1X
Hi-Z
2X
0
1
Bit 1
Bit 0
ATIG
Disable Mode
4
USB_48Str
48MHz Strength Control RW
Note: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output.
Behavior of the device is undefined under these conditions.
SMBus Table: Output Drive and ATIG Frequency Control Register
Byte 5
Bit 7
Bit 6
Bit 5
Pin #
52
41,40
43,42
Name
REF2Str
CPU2_Stop_En
Control Function
REF2 Strength Control RW
0 = CPU is free-run RW
Type
0
1X
Free-Run
Free-Run
1
2X
Stoppable
Stoppable
PWD
1
1
1
CPU1_Stop_En 1 = CPU is stopped by RW
SRCFS4
(SS_EN)
SRCFS3
SRCFS2
SRCFS1
SRCFS0
Freq Select Bit 4
(SS_EN)
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
-
RW
0
Bit 4
See Table 2 SRC
Frequency Selection
-
-
-
-
RW
RW
RW
RW
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
NOTE: CPU(1:2)_Stop_En (Byte5, bit 6:5) only exist in devices with REV ID = 2 or higher
0891E—03/07/05
9
Integrated
Circuit
ICS951411
Systems, Inc.
SMBus Table: Device ID Register
Byte 6
Bit 7
Pin #
Name
Control Function
Device ID MSB
Device ID 6
Device ID 5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID LSB
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
DevID 7
DevID 6
DevID 5
DevID 4
DevID 3
DevID 2
DevID 1
DevID 0
0
0
0
1
0
0
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Vendor ID Register
Byte 7
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
X
X
X
X
0
0
0
1
Revision ID
Starts at 0 hex for A
revsion.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VENDOR ID
(0001 = ICS)
SMBus Table: Byte Count Register
Byte 8
Bit 7
Pin #
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
0
0
0
0
1
0
0
1
-
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register will
configure how many bytes
will be read back, default
is 9 bytes.
Byte Count Programming
b(7:0)
Bytes 9 through 21 are reserved
Test Clarification Table
Comments
HW
TEST_SEL/REF2
OUTPUT
HW PIN
1. Power-up w/ TEST_SEL/REF2 > 2.0V to enter test mode.
2. Cycle power to disable test mode
<0.8V
>2.0V
NORMAL
HI-Z
0891E—03/07/05
10
Integrated
Circuit
ICS951411
Systems, Inc.
Absolute Max
Symbol
VDD_A
VDD_In
Parameter
Min
Max
Units
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
V
V
DD + 0.5V
DD + 0.5V
V
V
°C
°C
°C
GND - 0.5
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
-65
0
150
70
115
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS Notes
VIH
VIL
IIH
V
DD + 0.3
Input High Voltage
Input Low Voltage
Input High Current
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
2
VSS - 0.3
-5
V
V
uA
1
1
1
0.8
5
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
IIL1
IIL2
-5
uA
uA
1
1
Input Low Current
-200
resistors
Low Threshold Input-
High Voltage
VIH_FS
V
DD + 0.3
3.3 V +/-5%
0.7
V
V
1
1
Low Threshold Input-
Low Voltage
Operating Current
VIL_FS
IDD3.3OP
IDD3.3PD
VSS - 0.3
3.3 V +/-5%
0.35
all outputs driven
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
400
70
12
mA
mA
mA
1
1
1
3
1
1
1
1
Powerdown Current
Fi
Lpin
CIN
COUT
CINX
Input Frequency
Pin Inductance
14.31818
MHz
7
5
6
5
nH
pF
pF
pF
Logic Inputs
Output pin capacitance
X1 & X2 pins
Input Capacitance
From VDD Power-Up or de-
TSTAB
Clk Stabilization
Modulation Frequency
Tdrive_PD#
1.8
33
ms
kHz
us
1,2
1
assertion of PD# to 1st clock
Triangular Modulation
CPU output enable after
PD# de-assertion
30
300
1
Tfall_Pd#
Trise_Pd#
SMBus Voltage
PD# fall time of
PD# rise time of
5
5
5.5
0.4
ns
ns
V
1
2
1
1
VDD
VOL
2.7
4
@ IPULLUP
Low-level Output Voltage
Current sinking at
V
IPULLUP
TRI2C
mA
ns
1
1
1
V
OL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1000
300
TFI2C
ns
Clock/Data Fall Time
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
0891E—03/07/05
11
Integrated
Circuit
ICS951411
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
VO = Vx
Zo
3000
Ω
1
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
1,3
1,3
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
see Tperiod min-max values
400MHz nominal
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
1
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
Tabsmin
Absolute min period
tr
tf
d-tr
d-tf
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
700
700
125
125
175
1
1
1
Measurement from differential
wavefrom
dt3
tsk3
tsk4
Duty Cycle
Skew
45
55
%
ps
ps
1
1
1
CPU(1:0), VT = 50%
CPU(1:0) to CPU2_ITP,
VT = 50%
100
150
Skew
Measurement from differential
wavefrom (CPU2_ITP)
Measurement from differential
wavefrom, (CPU(1:0))
tjcyc-cyc
tjcyc-cyc
Jitter, Cycle to cycle
Jitter, Cycle to cycle
125
85
ps
ps
1
1
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
0891E—03/07/05
12
Integrated
Circuit
ICS951411
Systems, Inc.
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Zo
CONDITIONS
VO = Vx
MIN
TYP
MAX UNITS Notes
Current Source Output
Impedance
3000
1
Ω
Statistical measurement
on single ended signal
Measurement on single
ended signal using
Voltage High
Voltage Low
Max Voltage
VHigh
VLow
Vovs
Vuds
660
-150
850
150
1150
1,3
1,3
1
mV
mV
mV
mV
ppm
Min Voltage
-300
250
1
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Vcross(abs)
d-Vcross
ppm
350
12
550
140
300
1
1
Variation of crossing over
all edges
see Tperiod min-max
-300
1,2
values
100.00MHz nominal
100.00MHz spread
100.00MHz
nominal/spread
VOL = 0.175V,
9.9970
9.9970
10.0030
10.0533
ns
ns
2
2
Average period
Tperiod
Tabsmin
Absolute min period
9.8720
ns
1,2
tr
tf
Rise Time
Fall Time
175
700
700
ps
1
V
OH = 0.525V
VOH = 0.525V
OL = 0.175V
175
45
ps
1
V
d-tr
d-tf
Rise Time Variation
Fall Time Variation
30
30
125
125
ps
ps
1
1
Measurement from
differential wavefrom
VT = 50%
Measurement from
differential wavefrom
dt3
tsk3
Duty Cycle
Skew
55
%
ps
ps
1
1
1
250
125
tjcyc-cyc
Jitter, Cycle to cycle
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
0891E—03/07/05
13
Integrated
Circuit
ICS951411
Systems, Inc.
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
CONDITIONS
MIN
TYP
MAX UNITS Notes
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
IOH = -1 mA
-300
29.9910
29.9910
2.4
300
ppm
1,2
2
2
30.0090 ns
30.1598 ns
V
Tperiod
VOH
VOL
Output High Voltage
Output Low Voltage
1
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
0.55
-33
38
V
1
1
1
1
1
-33
30
mA
mA
mA
mA
IOH
IOL
Output High Current
Output Low Current
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Jitter
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
0.5
0.5
45
4
4
2
2
55
250
V/ns
V/ns
ns
ns
%
1
1
1
1
1
1
tr1
tf1
dt1
tjcyc-cyc
VT = 1.5 V
ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Electrical Characteristics - 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS Notes
Long Accuracy
Clock period
Output High Voltage
ppm
Tperiod
VOH
see Tperiod min-max values
48.00MHz output nominal
IOH = -1 mA
-100
20.8313
2.4
100
20.8354 ns
ppm
1,2
2
1
V
VOL
IOL = 1 mA
V OH @ MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Output Low Voltage
0.55
-33
V
1
1
1
1
1
1
1
-33
30
mA
mA
mA
mA
V/ns
V/ns
IOH
Output High Current
IOL
Output Low Current
38
2
2
Edge Rate
Edge Rate
1
1
tr1
tf1
dt1
Rise Time
Fall Time
Duty Cycle
1
1
45
2
2
55
175
ns
ns
%
1
1
1
1
tjcyc-cyc
VT = 1.5 V
Jitter, Cycle to cycle
ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0891E—03/07/05
14
Integrated
Circuit
ICS951411
Systems, Inc.
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS Notes
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
-300
69.8270
2.4
300
69.8550
ppm
ns
V
1
1
1
1
VOL
IOL = 1 mA
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
0.4
-23
V
IOH
IOL
Output High Current
Output Low Current
-29
29
mA
mA
1
1
VOL @MIN = 1.95 V,
@MAX = 0.4 V
VOL
27
tr1
tf1
tsk1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Rise Time
Fall Time
Skew
1
1
2
2
500
55
ns
ns
ps
%
1
1,2
2
dt1
VT = 1.5 V
Duty Cycle
45
1,2
1
tjcyc-cyc
VT = 1.5 V
Jitter
1000
ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0891E—03/07/05
15
Integrated
Circuit
ICS951411
Systems, Inc.
SRC Reference Clock
Common Recommendations for Differential Routing
L1 length, Route as non -coupled 50 ohm trace.
Dimension or Value
Unit
inch
inch
inch
ohm
ohm
Figure
2, 3
2, 3
2, 3
2, 3
2, 3
0.5 max
0.2 max
0.2 max
33
L2 length, Route as non
-coupled 50 ohm trace.
-coupled 50 ohm trace.
L3 length, Route as non
Rs
Rt
49.9
Down Device Differential Routing
Dimension or Value
2 min to 16 max
Unit
inch
Figure
L4 length, Route as coupled
microstrip 100 ohm
2
2
differential trace.
L4 length, Route as coup
differential trace.
led stripline 100 ohm
1.8 min to 14.4 max
inch
Differential Routing to PCI Express Connector
Dimension or Value
0.25 to 14 max
Unit
inch
Figure
L4 length, Route as coupled
differential trace.
microstrip 100 ohm
3
3
L4 length, Rout e as coupled stripline 100 ohm
differential trace.
0.225 min to 12.6
max
inch
L1
L2
L4
L4’
Rs
L1’
L2’
Rs
Rt
Rt
Fig.1
HSCL Output
Buffer
PCI Ex
REF_CLK
L3’
L3
Test Load
L1
L2
L4
Rs
Rs
L4’
L1’
L2’
Fig.2
Rt
Rt
HSCL Output
Buffer
PCI Ex Board
Down Device
L3’
L3
REF_CLK Input
L1
L2
L4
L4’
Rs
Rs
L1’
L2’
Rt
Rt
Fig.3
HSCL Output
Buffer
PCI Ex
Add In Board
REF_CLK Input
L3’
L3
0891E—03/07/05
16
Integrated
Circuit
ICS951411
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS951416
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an output
function. In this mode the pins produce the specified buffered
clocks to external loads.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0891E—03/07/05
17
Integrated
Circuit
ICS951411
Systems, Inc.
c
56-Lead, 300 mil Body, 25 mil, SSOP
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS
COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
hh xx 45°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
a
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- C -
D mm.
D (inch)
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
e
SEATING
PLANE
56
b
.10 (.004) C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS951411yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0891E—03/07/05
18
Integrated
Circuit
ICS951411
Systems, Inc.
c
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
N
(240 mil)
(20 mil)
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
INDEX
AREA
c
1
2
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
A
A2
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A1
- C -
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
b
N
MIN
13.90
MAX
14.10
MIN
.547
MAX
.555
aaa
C
56
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS951411yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0891E—03/07/05
19
相关型号：
ICS951411YFT
Processor Specific Clock Generator, 400MHz, PDSO56, 0.300 INCH, 0.025 INCH PITCH, MO-118, SSOP-56
IDT
ICS951411YGT
Processor Specific Clock Generator, 400MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
IDT
ICS951412AGLF
Processor Specific Clock Generator, 220MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
IDT
©2020 ICPDF网 联系我们和版权申明