ICS952001 [ICSI]
Preliminary Product Previes; 初步产品Previes
| 型号： | ICS952001 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Preliminary Product Previes |
| 文件： | 总17页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Programmable Timing Control Hub for P4 processor
Recommended Application:
Pin Configuration
SIS 645/650 style chipsets.
VDDREF
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDSD
SDRAM
GNDSD
Output Features:
CPU_STOP#*
CPUCLKT_1
CPUCLKC_1
VDDCPU
GNDCPU
CPUCLKT_0
CPUCLKC_0
IREF
GNDA
VDDA
SCLK
SDATA
PD#*/Vtt_PWRGD
GNDAGP
AGPCLK0
AGPCLK1
VDDAGP
VDDA48
48MHz
24_48MHz/MULTISEL*
GND48
•
2 - Pairs of differential CPUCLKs (differential current mode)
•
•
1 - SDRAM @ 3.3V
8 - PCI @3.3V
X2
GNDZ
ZCLK0
ZCLK1
•
•
•
•
2 - AGP @ 3.3V
VDDZ
*PCI_STOP#
VDDPCI
2 - ZCLKs @ 3.3V
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
•
3- REF @3.3V, 14.318MHz.
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
Features/Benefits:
•
Programmable output frequency, divider ratios, output
rise/falltime, output skew.
48-Pin 300-mil SSOP and TSSOP
•
•
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
•
•
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
•
•
•
For PC133 SDRAM system use the ICS9179-06 as the
memory buffer.
For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
Block Diagram
Uses external 14.318MHz crystal.
Key Specifications:
PLL2
48MHz
•
•
•
PCI - PCI output skew: < 500ps
CPU - SDRAM output skew: < 1ns
AGP - AGP output skew: <150ps
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF (1:0)
2
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLKT (1:0)
CPUCLKC (1:0)
Stop
2
Functionality
2
B it 2 B it 7 B it 6 B it 5 B it 4
C P U
S D R A M Z C L K
A G P
ZCLK
ZCLK (1:0)
DIVDER
2
6
Control
Logic
F S 4 F S 3 F S 2 F S 1 F S 0 (M H z )
6 6 .6 7
(M H z )
6 6 .6 7
(M H z )
6 6 .6 7
6 6 .6 7
6 6 .6 7
6 6 .6 7
6 0 .0 0
6 2 .5 0
6 6 .6 7
8 0 .0 0
6 6 .6 7
6 2 .5 0
7 1 .4 3
6 6 .6 7
6 6 .6 7
6 3 .3 3
6 3 .3 3
5 0 .0 0
(M H z )
6 6 . 6 7
6 6 . 6 7
6 6 . 6 7
6 6 . 6 7
6 0 . 0 0
6 2 . 5 0
6 6 . 6 7
6 6 . 6 7
6 6 . 6 7
6 2 . 5 0
8 3 . 3 3
6 6 . 6 7
6 6 . 6 7
6 3 . 3 3
6 3 . 3 3
5 0 . 0 0
SDATA
SCLK
FS (4:0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PCI
DIVDER
Stop
PCICLK (9:0)
PCICLK_F (1:0)
AGP (1:0)
1 0 0 .0 0 1 0 0 . 0 0
1 0 0 .0 0 2 0 0 . 0 0
1 0 0 .0 0 1 3 3 . 3 3
1 0 0 .0 0 1 5 0 . 0 0
1 0 0 .0 0 1 2 5 . 0 0
1 0 0 .0 0 1 6 0 . 0 0
1 0 0 .0 0 1 3 3 . 3 3
1 0 0 .0 0 2 0 0 . 0 0
1 0 0 .0 0 1 6 6 . 6 7
1 0 0 .0 0 1 6 6 . 6 7
8 0 .0 0
8 0 .0 0
9 5 .0 0
9 5 .0 0
6 6 .6 7
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
2
2
Config.
Reg.
AGP
DIVDER
I REF
Power Groups
VDDCPU = CPU
1 3 3 . 3 3
1 3 3 . 3 3
9 5 .0 0
1 2 6 . 6 7
6 6 .6 7
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
Note: For additional margin testing frequencies, refer to Byte 4
VDDREF = Xtal, REF
VDDZ = ZCLK
952001 Rev
A 01/24/02
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
General Description
The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero
delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 11, 13, 19, 29,
42, 48
VDD
PWR
Power supply for 3.3V
FS0
REF0
FS1
IN
Frequency select pin.
2
3
4
14.318 MHz reference clock.
Frequency select pin.
OUT
IN
14.318 MHz reference clock.
Frequency select pin.
REF1
FS2
OUT
IN
14.318 MHz reference clock.
REF2
OUT
5, 8, 18, 24, 25,
32, 37, 41, 46
6
GND
PWR
Ground pin for 3V outputs.
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Hyperzip clock outputs.
7
OUT
OUT
10, 9
ZCLK(1:0)
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
MODE pin is in Mobile mode
Frequency select pin.
12
14
PCI_STOP#
IN
FS3
IN
PCICLK_F0
FS4
OUT
IN
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
15
PCICLK_F1
OUT
PCI clock output, not affected by PCI_STOP#
23, 22, 21, 20, 17,
16
PCICLK (5:0)
OUT
PCI clock outputs.
MULTISEL
24_48MHz
48MHz
IN
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Clock output for super I/O/USB default is 24MHz
48MHz output clock
26
OUT
OUT
PWR
OUT
27
28, 36
30, 31
AVDD
Analog power supply 3.3V
AGPCLK (1:0)
AGP outputs defined as 2X PCI. These may not be stopped.
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal.
When Vtt_PWRGD goes high the frequency select will be latched at
power on thereafter the pin is an asynchronous active low power down
pin.
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
PD#
IN
IN
33
Vtt_PWRGD
34
35
SDATA
SCLK
I/O
IN
This pin establishes the reference current for the CPUCLK
pairs. This pin requires a fixed precision resistor tied to ground
38
I REF
OUT
in order to establish the appropriate current.
"Complementary" clocks of differential pair CPU outputs. These clocks
are 180° out of phase with SDRAM clocks. These open drain outputs
need an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase
with SDRAM clocks. These open drain outputs need an external 1.5V pull-
up.
43, 39
44, 40
CPUCLKC (1:0)
CPUCLKT (1:0)
OUT
OUT
Stops all CPUCLKs clocks at logic 0 level, when MODE pin is in Mobile
mode
45
47
CPU_STOP#
SDRAM
IN
OUT
SDRAM clock output.
Third party brands and names are the property of their respective owners.
2
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
CPUCLK Swing Select Functions
Reference R,
Iref=
Vdd/(3*Rr)
Board Target
Trace/Term Z
Output
Current
Voh @ Z,
Iref=2.32mA
Byte 23
Bit 7
MULTSEL0
Rr = 475 1%
Iref = 2.32mA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.71V @ 60
0.59V @ 50
0.56V @ 60
0.47V @ 50
0.85V /2 60
0.71V @ 50
0.99V @ 60
0.82V @ 50
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.75V @ 30
0.62V @ 20
0.60 @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
0.5V @ 20
0.90V @ 30
0.75V @ 20
1.05V @ 30
0.84V @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Third party brands and names are the property of their respective owners.
3
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
General I2C serial interface information for the ICS952001
How to Write:
How to Read:
Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following pageꢀ
Third party brands and names are the property of their respective owners.
4
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Serial Configuration Command Bitmap
Bytes 0-3: Are reserved for external clock buffer.
Byte4: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4
FS4 FS3 FS2
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
SDRAM
ZCLK
66.67
66.67
66.67
66.67
60.00
62.50
66.67
80.00
66.67
62.50
71.43
66.67
66.67
63.33
63.33
50.00
70.00
67.27
72.00
67.27
74.67
66.67
66.67
66.67
80.00
80.00
83.33
80.00
100.00
100.00
100.00
100.00
AGP
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
70.00
67.27
72.00
67.27
74.67
66.67
66.67
66.67
66.67
66.67
62.50
66.67
66.67
66.67
62.50
66.67
PCI
Spread Precentage
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
66.67
66.67
100.00
200.00
133.33
150.00
125.00
160.00
133.33
200.00
166.67
166.67
133.33
133.33
95.00
33.33
33.33
33.33
33.33
30.00
31.25
33.33
33.33
33.33
31.25
41.67
33.33
33.33
31.67
31.67
25.00
35.00
33.63
36.00
33.63
37.33
33.33
33.33
33.33
33.33
33.33
31.25
33.33
33.33
33.33
31.25
33.33
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
80.00
80.00
95.00
00000
Note1
95.00
126.67
66.67
Bit 2
Bit 7:4
66.67
105.00
100.90
108.00
100.90
112.00
133.33
133.33
133.33
100.00
100.00
100.00
133.33
100.00
100.00
100.00
133.33
140.00
100.90
144.00
134.53
149.33
100.00
133.33
166.67
133.00
100.00
166.67
160.00
133.00
100.00
166.67
160.00
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit , 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Bit 3
Bit 1
Bit 0
0
0
0
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
Third party brands and names are the property of their respective owners.
5
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Byte 5: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Pin#
30
31
PWD
1
1
Description
AGPCLK1
AGPCLK1
SEL24_48MHz
Bit 5
26
0
(1=24MHz, 0=48MHz)
FS4 Read Back
FS3 Read Back
FS2 Read Back
FS1 Read Back
FS0 Read Back
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15
14
4
3
2
X
X
X
X
X
Byte 6: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Pin#
10
9
PWD
1
1
Description
ZCLK1
ZCLK0
PCICLK_F0 stop control
Bit 5
Bit 4
Bit 3
Bit 2
14
15
0
0
1
1
0 = Free Running; 1 = Stop
PCICLK_F1 stop control
0 = Free Running; 1 = Stop
CPUCLKT/C0 stop control
0 = Free Running; 1 = Stop
CPUCLKT/C1 stop control
0 = Free Running; 1 = Stop
40, 39
44, 43
Bit 1
Bit 0
39, 40
43, 44
1
1
CPUCLKT/C0 output control
CPUCLKT/C1 output control
Byte 7: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
15
14
23
22
21
20
17
16
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
PCICLK_F1
PCICLK_F0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 8: Byte Count Read Back Register
Bit
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
1
1
1
Note: Writing to this register will configure
byte count and how many bytes will be
read back, default is 0FH = 15 bytes.
Third party brands and names are the property of their respective owners.
6
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Byte 9: Watchdog Timer Count Register
Bit
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these 8 bits
correspond to X • 290ms the watchdog
timer will wait before it goes to alarm mode
and reset the frequency to the safe setting.
Default at power up is 16 • 290ms = 4.6
seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Description
Programming Enable bit
Program
Enable
0 = no programming. Frequencies are selected by
HW latches or Byte0
Bit 7
0
1 = enable all I2C programing.
Bit 6 WD Enable
Bit 5 WD Alarm
0
0
0
0
0
0
1
Watchdog Enable bit
Watchdog Alarm Status 0 = normal 1= alarm status
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SF4
SF3
SF2
SF1
SF0
Watchdog safe frequency bits. Writing to these bits
will configure the safe frequency corrsponding to
Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N divider bit 8
The decimal respresentation of Mdiv (6:0)
corresposd to the reference divider value.
Default at power up is equal to the latched
inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of Ndiv (8:0)
correspond to the VCO divider value.
Default at power up is equal to the latched
inputs selecton. Notice Ndiv 8 is located in
Byte 11.
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Integrated
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Systems, Inc.
ICS952001
Preliminary Product Preview
Byte 13: Spread Spectrum Control Register
Bit
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Spread Spectrum (12:0) bit will
program the spread precentage. Spread
precent needs to be calculated based on
the VCO frequency, spreading profile,
spreading amount and spread frequency. It
is recommended to use ICS software for
spread programming. Default power on is
latched FS divider.
Byte 14: Spread Spectrum Control Register
Bit
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Name
PWD
X
X
X
X
X
X
X
X
Description
SDRAM clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 1. Default at power up is latched
FS divider.
CPUCLKT/C clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 1. Default at power up is latched
FS divider.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SD Div 3
SD Div 2
SD Div 1
SD Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
Byte 16: Output Divider Control Register
Bit
Name
PWD
Description
AGP clock divider ratio can be
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AGP Div 3
AGP Div 2
AGP Div 1
AGP Div 0
ZCLK Div 3
ZCLK Div 2
ZCLK Div 1
ZCLK Div 0
X
X
X
X
X
X
X
X
configured via these 4 bits
individually. For divider selection
table refer to Table 1. Default at
power up is latched FS divider.
ZCLK clock divider ratio can be
configured via these 4 bits
individually. For divider selection
table refer to Table 1. Default at
power up is latched FS divider.
Third party brands and names are the property of their respective owners.
8
Integrated
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Systems, Inc.
ICS952001
Preliminary Product Preview
Byte 17: Output Divider Control Register
Bit
Name
PWD
0
0
0
0
X
X
X
X
Description
AGP Phase Inversion bit
ZCLK Phase Inversion bit
SDRAM Phase Inversion bit
CPUCLK Phase Inversion bit
PCI clock divider ratio can be
configured via these 4 bits
individually. For divider selection
table refer to table 2. Default at
power up is latched FS divider.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AGP_INV
ZCLK_INV
SD_INV
CPU_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
Table 1
Table 2
Div (3:2)
Div (3:2)
Div (1:0)
00
00
01
10
11
00
01
10
11
Div (1:0)
00
01
10
11
/2
/3
/5
/7
/4
/6
/8
/16
/24
/40
/56
/4
/3
/5
/7
/8
/6
/16
/12
/20
/28
/32
/24
/40
/56
/12
/20
/28
01
/10
/14
10
/10
/14
11
Byte 18: Group Skew Control Register
Bit
Name
PWD
Description
These 2 bits delay the CPUCLKT/C (1:0)
clocks with respect to all other clocks.
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
These 2 bits delay the SDRAM with respect to
CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Bit 7
CPU_Skew 1
1
Bit 6
Bit 5
Bit 4
CPU_Skew 0
SD_Skew 1
SD_Skew 0
0
0
1
Bit 3
Bit 2
Bit 1
Bit 0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
1
1
1
1
(Reserved)
Byte 19: Group Skew Control Register
Bit
Name
PWD
Programmable Delay Stop
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
1
0
0
0
1
0 0 0 0 1ꢀ85ns 1 0
0 0 0 1 2ꢀ00ns 1 0
0
0
0
3ꢀ05ns
1 3ꢀ20ns
These 4bits control
CPU-ZCLK(1:0)
0 0 1 0 2ꢀ15ns 1 0 1 0 3ꢀ35ns
0 0 1 1 2ꢀ30ns 1 0 1 3ꢀ50ns
3ꢀ65ns
1 0 1 3ꢀ80ns
1
0
0
0
0
1 0 0 2ꢀ45ns
1 0 1 2ꢀ60ns
1 1 0 2ꢀ75ns
1 1 1 2ꢀ90ns
1
1
1
1
1 0 0
Bit 2
Bit 1
Bit 0
0
0
0
These 4 bits control
CPU-AGP(1:0)
1
1
1 0 3ꢀ95ns
1 4ꢀ10ns
1
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Integrated
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ICS952001
Preliminary Product Preview
Byte 20: Group Skew Control Register
Bit
Name
PWD
Programmable Delay Stop
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
1
0
0
0
0 0 0 0 1ꢀ85ns 1 0
0 0 0 1 2ꢀ00ns 1 0
0
0
0
3ꢀ05ns
1 3ꢀ20ns
These 4bits control
CPU-PCICLK_F(1:0)
0 0 1 0 2ꢀ15ns 1 0 1 0 3ꢀ35ns
0 0 1 1 2ꢀ30ns 1 0 1 3ꢀ50ns
3ꢀ65ns
1 0 1 3ꢀ80ns
1
0
0
0
0
1 0 0 2ꢀ45ns
1 0 1 2ꢀ60ns
1 1 0 2ꢀ75ns
1 1 1 2ꢀ90ns
1
1
1
1
1 0 0
Bit 2
Bit 1
Bit 0
1
0
0
These 4 bits control
CPU-PCICLK(5:0)
1
1
1 0 3ꢀ95ns
1 4ꢀ10ns
1
Byte 21: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
24/48 MHz clock slew rate control bits.
01 = strong; 00, 11 = normal; 10 = weak
24/48_Slew
AGP clock slew rate control bits.
01 = strong; 00, 11 = normal; 10 = weak
AGP_Slew
ZCLK_Slew
REF_Slew
ZCLK clock slew rate control bits.
01 = strong; 00, 11 = normal; 10 = weak
REF clock slew rate control bits.
01 = strong; 00, 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
X
X
0
0
0
0
SDRAM clock slew rate control bits.
SDRAM Slew
01 = strong; 00, 11 = normal;10 = weak
(Reserved)
(Reserved)
PCICLK_F clock slew rate control bits.
01 = strong; 00, 11 = normal;10 = weak
PCICLK_F Slew
PCICLK Slew
PCICLK clock slew rate control bits.
01 = strong; 00, 11 = normal;10 = weak
Byte 23: Output Control Register
Bit
Pin#
-
-
47
27
26
4
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
1
1
1
1
1
1
Iref Output Control
MULITSEL Readback
SDRAM
48MHz
24_48MHz
REF2
REF1
REF0
3
2
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Integrated
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Systems, Inc.
ICS952001
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
VIL
VSS-0.3
-5
V
IIH
VIN = VDD
5
mA
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 30 pF; CPU @ 133 MHz
-5
IIL2
-200
IDD3.3OP
280
25
Supply Current
Power Down
IDD3.3PD
CL = 0 pF
mA
Supply Current
Input frequency
Pin Inductance
Input Capacitance1
Fi
Lpin
VDD = 3.3 V
14.32
MHz
nH
pF
7
5
CIN
Logic Inputs
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
Delay
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
mS
mS
mS
nS
3
TSTAB
3
t
t
PZH,tPZH output enable delay (all outputs)
PLZ,tPZH
1
1
10
10
output disable delay (all outputs)
nS
1Guaranteed by design, not 100% tested in production.
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Integrated
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Systems, Inc.
ICS952001
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
TYP MAX UNITS
1
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
13.5
13.5
2
45
45
Ω
Ω
RDSP2B
1
VO = VDD*(0.5)
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
IOH = -1 mA
V
IOL = 1 mA
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
ns
ps
ps
1
0.4
0.4
45
1.6
1.6
55
tr2B
1
Fall Time
tf2B
1
Duty Cycle
50
dt2B
1
Skew
VT = 1.25 V
175
250
tsk2B
1
Jitter
VT = 1.25 V
tjcyc-cyc
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
UNITS
Ω
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
TYP
MAX
55
1
RDSP1
12
12
1
RDSN1
VO = VDD*(0.5)
IOH = -18 mA
55
Ω
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 9.4 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
25
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.0
2.0
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
45.0
55.0
500
250
%
1
Skew Window
tsk1
VT = 1.5 V
ps
1
tj1s1
VT = 1.5 V
Jitter
ps
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
Integrated
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Systems, Inc.
ICS952001
Preliminary Product Preview
Electrical Characteristics - 24M, 48M, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
UNITS
Ω
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
20
TYP
MAX
60
1
RDSP5
1
RDSN5
VO = VDD*(0.5)
IOH = -14 mA
20
60
Ω
VOH5
VOL5
IOH5
IOL5
2.4
V
IOL = 6.0 mA
0.4
-20
V
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
10
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4.0
4.0
1
Fall Time
tf5
ns
1
Duty Cycle
dt5
45.0
55.0
500
%
1
tj1s5
VT = 1.5 V
Jitter
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD =VDDL 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
TYP
MAX UNITS
1
RDSP2A
10
10
20
20
Ω
Ω
1
RDSN2A
VO = VDD*(0.5)
IOH = -28 mA
VOH2A
VOL2A
IOH2A
IOL2A
2.4
V
IOL = 19 mA
0.4
-42
V
VOH = 2.0 V
mA
mA
ns
ns
%
VOL = 0.8 V
33
0.5
0.5
45
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.0
2
1
Fall Time
tf2A
1
Duty Cycle
Jitter1
dt2A
55
tcyc-cyc
VT = 1.5 V
250.0
ps
1Guarenteed by design, not 100% tested in production.
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13
Integrated
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Systems, Inc.
ICS952001
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming
resistors should be located close to the series termination
resistor to minimize the current loop area. It is more important
to locate the series termination resistor close to the driver
than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
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14
Integrated
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Systems, Inc.
ICS952001
Preliminary Product Preview
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
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15
Integrated
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Systems, Inc.
ICS952001
Preliminary Product Preview
In Millimeters
In Inches
c
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
h
L
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
0.635 BASIC
0.025 BASIC
h x 45°
D
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
A1
VARIATIONS
- C -
D mm.
D (inch)
N
MIN
15.75
MAX
16.00
MIN
.620
MAX
e
SEATING
PLANE
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS952001yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
16
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.27
0.20
MIN
-
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
E
E1
e
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.30
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
-
8°
0°
-
8°
aaa
0.10
.004
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.488
MAX
48
12.40
12.60
.496
7/6/00 Rev B
MO-153 JEDEC
Doc.# 10-0039
Ordering Information
ICS952001yFT
Example:
ICS XXXX y G - PPP
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
PackageType
G=TSSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Registered Company
9001
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http://www.icst.com
17
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