ICS952302YGLF-T [ICSI]
Frequency Generator for TransmetaTM; 频率发生器TransmetaTM
| 型号： | ICS952302YGLF-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator for TransmetaTM |
| 文件： | 总15页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS952302
Integrated
Circuit
Systems, Inc.
Frequency Generator for TransmetaTM EfficeonTM
RecommendedApplication:
Features:
•
Support I2C Index read/write and block read/write
operations.
Transmeta Efficion, ATi M6
•
•
Uses external 14.318MHz referience input or XTAL.
Full Load Power consumption reduced >10%
compared to reference device
OutputFeatures:
•
3 - CPUs @ 3.3V including 1 free running
CPUCLK_F
•
Power management via SMBus
•
7 - PCI @ 3.3V, including 4 free running PCICLK_F
•
•
1 - 27MHz clock @ 3.3V
2 - 48MHz clocks @ 3.3V
•
2 - REF clocks @3.3V
KeySpecifications:
•
•
•
•
•
CPU output jitter: < 250ps
PCI output skew: < 250ps
CPUT - PCI output skew: 1-3ns
27MHz Accuracy < 50ppm
48MHz Accuracy < 50ppm
Pin Configuration
Functionality
VDDREF 1
REF0 2
48 REF1
Spread
%
Byte 4b7
Byte 4b6
Byte 4b5
47 VDDCPU
46 N/C
GNDREF 3
X1 4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+/-0.3
45 CPUCLK0
44 GNDCPU
43 CPUCLK1
42 CPUCLK_F
41 CPU_STOP#
40 GND
+/-0.6
+/-0.25
+/-0.45
-0.60%
-1.20%
-0.50%
-0.90%
X2 5
CENTER
DOWN
VDDPCI 6
PCICLK_F0 7
PCICLK_F1 8
GNDPCI 9
PCICLK0 10
PCICLK1 11
PCICLK_F2 12
PCICLK_F3 13
VDDPCI 14
PCICLK2 15
GNDPCI 16
N/C 17
39 N/C
38 OE*
37 N/C
36 VDD
35 N/C
34 VDD27
33 GND
32 27MHZ
31 N/C
N/C 18
VDDCOR 19
PCI_STOP# 20
**PD# 21
30 N/C
29 N/C
28 GND48
27 VDD48
26 48MHZ_1
25 48MHZ_0
GND48 22
SDATA 23
SCLK 24
48-TSSOP
* Internal Pull-Up Resistor
**No Diode Clamp to VDD
0957B—10/05/04
ICS952302
Pin Descriptions
PIN
TYPE
PIN #
PIN NAME
DESCRIPTION
1
2
3
VDDREF
REF0
GNDREF
X1
PWR Ref, XTAL power supply, nominal 3.3V
OUT 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
4
IN
Crystal input, Nominally 14.318MHz.
5
X2
OUT Crystal output, Nominally 14.318MHz
6
7
8
9
VDDPCI
PCICLK_F0
PCICLK_F1
GNDPCI
PCICLK0
PCICLK1
PCICLK_F2
PCICLK_F3
VDDPCI
PCICLK2
GNDPCI
N/C
PWR Power supply for PCI clocks, nominal 3.3V
OUT Free running PCI clock not affected by PCI_STOP# .
OUT Free running PCI clock not affected by PCI_STOP# .
PWR Ground pin for the PCI outputs
OUT PCI clock output.
OUT PCI clock output.
OUT Free running PCI clock not affected by PCI_STOP# .
OUT Free running PCI clock not affected by PCI_STOP# .
PWR Power supply for PCI clocks, nominal 3.3V
OUT PCI clock output.
10
11
12
13
14
15
16
17
18
19
20
PWR Ground pin for the PCI outputs
N/C
N/C
No Connection.
No Connection.
N/C
VDDCOR
PCI_STOP#
PWR 3.3V power for the PLL core.
IN
IN
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input.
Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
21
**PD#
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
GND48
SDATA
SCLK
48MHZ_0
48MHZ_1
VDD48
GND48
N/C
N/C
N/C
27MHZ
GND
VDD27
N/C
PWR Ground pin for the 48MHz outputs
I/O
IN
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
OUT 48MHz clock output.
OUT 48MHz clock output.
PWR Power pin for the 48MHz output.3.3V
PWR Ground pin for the 48MHz outputs
N/C
N/C
N/C
No Connection.
No Connection.
No Connection.
OUT 27.0000MHz Video Clock for ATi Chipset
PWR Ground pin.
PWR Power pin for the 27MHz output.3.3V
N/C
No Connection.
VDD
N/C
PWR Power supply, nominal 3.3V
N/C
IN
No Connection.
Active high input for enabling Memory Channel outputs.
0 = tri-state outputs, 1= enable outputs
No Connection.
38
OE*
39
40
41
42
43
44
45
46
47
48
N/C
GND
N/C
PWR Ground pin.
CPU_STOP#
CPUCLK_F
CPUCLK1
GNDCPU
CPUCLK0
N/C
IN
Stops all CPUCLK, except those set to be free running clocks
OUT Free running CPU clock. Not affected by the CPU_STOP#.
OUT CPU clock outputs. 3.3V
PWR Ground pin for the CPU outputs
OUT CPU clock outputs. 3.3V
N/C
No Connection.
VDDCPU
REF1
PWR Supply for CPU clocks, 3.3V nominal
OUT 14.318 MHz reference clock.
** No diode clamp to VDD.
* Internal Pull-Up Resistor
0957B—10/05/04
2
ICS952302
General Description
Spread spectrum may be enabled through SMBus programming. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS952302 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process
and temperature variations.
Block Diagram
(1:0)
27MHz
1
(1:0)
1
(1:0)
(2:0)
(3:0)
4
PD#
OE
0957B—10/05/04
3
ICS952302
SMBus Table: Output Control Register
Control
Byte 0
Pin #
Name
Type
0
1
PWD
Function
Bit 7
42
CPUCLK_F
CPUCLK0
CPUCLK1
27MHZ
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
45
43
32
25
26
2
48MHZ_0
48MHZ_1
REF0
48
REF1
SMBus Table: Output Control Register
Control
Byte 1
Pin #
Name
Type
0
1
PWD
Function
Bit 7
7
8
PCICLK_F0
PCICLK_F1
PCICLK_F2
PCICLK_F3
PCICLK0
Test Mode
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Output Enable
Output Enable
Output Enable
Spread Control
Output Enable
Output Enable
12
13
10
11
15
PCICLK1
PCICLK2
Spread Spectrum
Mode
-
Bit 0
Spread Control for PLL1
RW
OFF
ON
0
SMBus Table: Output Control Register
Control
Byte 2
Bit 7
Pin #
42
Name
Type
0
1
PWD
Function
Allow assertion of
CPU_STOP# or setting of
CPU_STOP control bit in
SMBus register to stop
CPU clocks
CPUCLK_F
CPUCLK0
CPUCLK1
RW
RW
RW
Free Running
Free Running
Free Running
Stoppable
Stoppable
Stoppable
0
1
1
45
43
Bit 6
Bit 5
-
Bit 4
Bit 3
Bit 2
Bit 1
Reserved
Reserved
CPU_STOP
Reserved
Reserved
Reserved
Stop all CPU clocks
Reserved
RW
RW
RW
RW
-
-
-
-
x
x
1
x
-
(note)
-
Enable
-
Disable
-
CPU_STOP#
PCI_STOP#
20, 41
Bit 0
H/w or S/w Select
RW
H/W
I2C
1
Note: Byte2bit2=0 (Enable) to stop all CPUCLK's ONLY when Byte2 bit(5:7) at STOPPABLE MODE
SMBus Table: Output Control Register
Control
Byte 3
Pin #
Name
Type
0
1
PWD
Function
Bit 7
7
8
PCICLK_F0
PCICLK_F1
PCICLK_F2
PCICLK_F3
PCICLK0
RW
RW
RW
RW
RW
RW
RW
RW
Free Running
Free Running
Free Running
Free Running
Free Running
Free Running
Free Running
Enable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Disable
0
0
0
0
1
1
1
1
Bit 6
Bit 5
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop PCI
clocks
12
13
10
11
15
-
Bit 4
Bit 3
Bit 2
PCICLK1
Bit 1
PCICLK2
Bit 0
PCI_STOP
Stop all PCI clocks
0957B—10/05/04
4
ICS952302
SMBus Table: Spread Spectrum Control Register
Control
Function
Byte 4
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Spread Position
Center or Down SS
Spread Bit 1
Spread Bit 2
RW
RW
RW
Center
Down
1
0
0
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SS1
SS2
See SS Table
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
SMBus Table: Control Register
Byte 5 Pin #
Bit 7
Control
Name
Type
Type
Type
0
0
0
1
1
1
PWD
Function
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Control Register
Byte 6 Pin #
Bit 7
Control
Name
PWD
Function
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Vendor & Revision ID Register
Control
Byte 7
Pin #
Name
PWD
Function
-
-
-
-
-
-
-
-
Bit 7
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
x
0
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
0957B—10/05/04
5
ICS952302
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
CaseTemperature . . . . . . . . . . . . . . . . . . . . . 115°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
CONDITIONS
MIN
2
TYP
MAX
DD + 0.3
0.8
UNITS
V
VIH
VIL
IIH
V
VSS - 0.3
V
VIN = VDD
5
mA
mA
mA
IIL1
IIL2
IDD(op)
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
-200
CL = (full load); 66MHz
Operating Supply Current
102
150
600
mA
Power Down Supply
Current
IDDPD
CL = 0 pF; With input address to Vdd or GND
320
◊A
Fi
CIN
VDD = 3.3 V;
Input frequency
11
27
1
14.3132
16
5
MHz
pF
Logic Inputs
Input Capacitance1
CINX
X1 & X2 pins
45
5.5
4
pF
Clk Stabilization1
Skew1
TSTAB
TCPU-PCI
From VDD = 3.3 V to 1% target Freq.
3
ms
ns
VT = 1.5 V
1.5
1Guaranteed by design, not 100% tested in production.
0957B—10/05/04
6
ICS952302
Electrical Characteristics - CPU
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH2B
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
IOH = -20 mA
IOL = 12 mA
2.9
0.25
-67
-8
VOL2B
0.4
-29
V
VOUT = 1 V
IOH2B
IOL2B
Output High Current
mA
VOUT = 3.135V
-23
27
VOUT = 1.95 V
VOUT =0.4V
56
Output Low Current
mA
23
30
2
Rise Time1
Fall Time1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
1.4
1.4
51.5
60
ns
ns
%
2
Duty Cycle1
dt2B
45
55
175
250
Skew1
tsk2B
VT = 1.5 V
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = 1.5 V
175
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK, PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH2B
CONDITIONS
MIN
2.4
TYP
2.9
0.25
-67
-8
MAX UNITS
V
IOH = -20 mA
IOL = 12 mA
VOL2B
0.4
-29
V
V
OUT = 1 V
VOUT = 3.135V
OUT = 1.95 V
VOUT =0.4V
IOH2B
IOL2B
Output High Current
mA
-23
27
V
56
Output Low Current
mA
23
30
2
Rise Time1
Fall Time1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
1.3
1.2
50.5
68
ns
ns
%
2
Duty Cycle1
dt2B
45
55
250
250
Skew1
tsk2B
VT = 1.5 V
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = 1.5 V
100
1Guaranteed by design, not 100% tested in production.
0957B—10/05/04
7
ICS952302
Electrical Characteristics - 27MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
FACC
CONDITIONS
REF Out = 14.31818MHz
IOH = -20 mA
MIN
-50
2.4
TYP
0
MAX UNITS
Frequency Accuracy
Output High Voltage
Output Low Voltage
50
ppm
V
VOH2B
2.9
0.25
-67
-8
VOL2B
IOL = 12 mA
0.4
-29
V
VOUT = 1 V
IOH2B
IOL2B
Output High Current
mA
mA
VOUT = 3.135V
-23
27
V
OUT = 1.95 V
OUT =0.4V
56
Output Low Current
V
23
30
2
Rise Time1
Fall Time1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
1.1
1.2
51
ns
ns
%
2
Duty Cycle1
dt2B
45
55
400
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = 1.5 V
340
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
FACC
CONDITIONS
REF Out = 14.31818MHz
IOH = -20 mA
MIN
-50
2.4
TYP
0
MAX UNITS
Frequency Accuracy
Output High Voltage
Output Low Voltage
50
ppm
V
VOH2B
2.9
0.25
-67
-8
VOL2B
IOL = 12 mA
0.4
-29
V
VOUT = 1 V
IOH2B
IOL2B
Output High Current
mA
mA
V
OUT = 3.135V
VOUT = 1.95 V
OUT =0.4V
-23
27
56
Output Low Current
V
23
30
2
Rise Time1
Fall Time1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
1.1
1.5
52
ns
ns
%
2
Duty Cycle1
dt2B
45
55
350
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = 1.5 V
200
ps
1Guaranteed by design, not 100% tested in production.
0957B—10/05/04
8
ICS952302
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
FACC
CONDITIONS
REF Out = 14.31818MHz
IOH = -20 mA
MIN
-50
2.4
TYP
MAX UNITS
Frequency Accuracy
Output High Voltage
Output Low Voltage
0
2.9
0.25
-67
-8
50
ppm
V
VOH2B
VOL2B
IOL = 12 mA
0.4
-29
V
VOUT = 1 V
IOH2B
IOL2B
Output High Current
mA
mA
VOUT = 3.135V
-23
27
V
OUT = 1.95 V
OUT =0.4V
56
Output Low Current
V
23
30
2
Rise Time1
Fall Time1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
1.3
1.7
53
ns
ns
%
2
Duty Cycle1
dt2B
45
55
500
Jitter, Cycle-to-cycle1
tjcyc-cyc2B
VT = 1.5 V
270
ps
1Guaranteed by design, not 100% tested in production.
0957B—10/05/04
9
ICS952302
General SMBus serial interface information for the ICS952302
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1 (see Note 2)
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
• ICS clock will acknowledge each byte one at a time
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• Controller (host) sends a Stop bit
• ICS clock sends Byte 0 through byte X
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0957B—10/05/04
10
ICS952302
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used.With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low.If programmability is not
necessary, than only a single resistor is necessary.The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. Itismoreimportanttolocatetheseriestermination
resistorclosetothedriverthantheprogrammingresistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
boththesolidCMOSprogrammingvoltageneededduring
the power-up programming period and to provide an
insignificantloadontheoutputclockduringthesubsequent
operatingperiod.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0957B—10/05/04
11
ICS952302
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input.This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internalclocksarenotrunningafterthedeviceisputinpowerdown.WhenPD#isactivelowallclocksneedtobedriven
to a low value and held prior to turning off the VCOs and crystal.The power up latency needs to be less than 4 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PCI_STOP#andCLK_STOP#areconsideredtobedon'tcaresduringthepowerdownoperations.TheREFand48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952302 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
0957B—10/05/04
12
ICS952302
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation.CLK_STOP#issynchronizedbytheICS952302.TheminimumthattheCPUclockisenabled(CLK_STOP#
high pulse) is 100 CPU clocks.All other clocks will continue to run while the CPU clocks are disabled.The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CLK_STOP#
PCI_STOP# (High)
CPUCLK _F
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS952302.
3. CLK_STOP# signal.
4. All other clocks continue to run undisturbed.
0957B—10/05/04
13
ICS952302
PCI_STOP# Timing Diagram
PCI_STOP#isanasynchronousinputtotheICS952302.ItisusedtoturnoffthePCICLK clocksforlowpoweroperation.
PCI_STOP# is synchronized by the ICS952302 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is
one PCICLK clock.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCI_STOP#
PCICLK
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952302 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS952302.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
0957B—10/05/04
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ICS952302
c
In Millimeters
In Inches
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
6.00
6.20
.236
0.020 BASIC
.244
a
0.50 BASIC
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
MIN
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
b
48
12.40
Reference Doc.: JEDEC Publication 95, M O-153
aaa
C
10-0039
(0.020 mil)
(240 mil)
6.10 mm. Body, 0.50 mm. pitch TSSOP
Ordering Information
ICS952302yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0957B—10/05/04
15
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