ICS952601YGLFT [ICSI]
Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor; 可编程定时控制中心™的下一代P4 ™处理器
| 型号： | ICS952601YGLFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
| 文件： | 总24页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS952601
Systems, Inc.
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
Features/Benefits:
CK409 clock, Intel Yellow Cover part
•
•
Supports tight ppm accuracy clocks for Serial-ATA.
Supports spread spectrum modulation, 0 to -0.5%
down spread.
Output Features:
•
•
•
•
•
•
•
•
•
3 - 0.7V current-mode differential CPU pairs
1 - 0.7V current-mode differential SRC pair
7 - PCI (33MHz)
•
•
Supports CPU clks up to 400MHz in test mode.
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning.
3 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
•
Supports undriven differential CPU, SRC pair in PD#
and CPU_STOP# for power management.
1 - DOT, 48MHz
2 - REF, 14.318MHz
4 - 3V66, 66.66MHz
1 - VCH/3V66, selectable 48MHz or 66MHz
Key Specifications:
Pin Configuration
REF0
•
•
•
•
•
CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
PCI outputs cycle-cycle jitter < 250ps
CPU outputs skew: < 100ps
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
56 FS_B
55 VDDA
54 GNDA
53 GND
52 IREF
51 FS_A
50 CPU_STOP#
49 PCI_STOP#
REF1
VDDREF
X1
+/- 300ppm frequency accuracy on CPU & SRC clocks
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
Functionality
48
VDDCPU
CPU
B6b5 FS_A FS_B MHz
SRC
MHz
3V66 PCI
MHz MHz
REF USB/DOT
47 CPUCLKT2
46 CPUCLKC2
VDDPCI
GND
MHz
MHz
48.00
Ref/N5
48.00
48.00
48.00
Hi-Z
0
0
0
1
1
1
0
0
1
1
0
100 100/200 66.66 33.33 14.318
MID Ref/N0 Ref/N1 Ref/N2 Ref/N3 Ref/N4
45
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
GND
1
0
1
200 100/200 66.66 33.33 14.318
133 100/200 66.66 33.33 14.318
166 100/200 66.66 33.33 14.318
0
1
44 CPUCLKT1
43 CPUCLKC1
MID Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
42
VDDCPU
0
1
0
1
200 100/200 66.66 33.33 14.318
400 100/200 66.66 33.33 14.318
266 100/200 66.66 33.33 14.318
333 100/200 66.66 33.33 14.318
48.00
48.00
48.00
48.00
41 CPUCLKT0
40 CPUCLKC0
39 GND
38
37
SRCCLKT
SRCCLKC
PD# 21
36 VDD
22
23
24
25
26
27
28
35 Vtt_PWRGD#
3V66_0
3V66_1
VDD3V66
GND
3V66_2
3V66_3
SCLK
34
VDD48
33 GND
32
31
30
29
48MHz_DOT
48MHz_USB
SDATA
3V66_4/VCH
56-pin SSOP & TSSOP
0701G—10/13/04
Integrated
Circuit
ICS952601
Systems, Inc.
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
REF0
REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
OUT
OUT
PWR
IN
14.318 MHz reference clock.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
9
10
11
12
13
14
15
16
17
18
19
20
PCICLK4
PCICLK5
PCICLK6
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 1.8ms. Internal pull-up of 150K nominal.
21
PD#
IN
22
23
24
25
26
27
28
3V66_0
3V66_1
VDD3V66
GND
3V66_2
3V66_3
SCLK
OUT
OUT
PWR
PWR
OUT
OUT
IN
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
0701G—10/13/04
2
Integrated
Circuit
ICS952601
Systems, Inc.
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
Data pin for SMBus circuitry, 5V tolerant.
48MHz clock output.
48MHz clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
29
3V66_4/VCH
OUT
30
31
32
33
34
SDATA
I/O
48MHz_USB
48MHz_DOT
GND
OUT
OUT
PWR
PWR
VDD48
35
Vtt_PWRGD#
IN
36
37
VDD
PWR
OUT
Power supply for SRC clocks, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
SRCCLKC
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
38
39
SRCCLKT
GND
OUT
PWR
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
40
CPUCLKC0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
41
42
CPUCLKT0
VDDCPU
OUT
PWR
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
43
CPUCLKC1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
44
45
CPUCLKT1
GND
OUT
PWR
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
46
CPUCLKC2
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
47
48
CPUCLKT2
VDDCPU
OUT
PWR
Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at logic
0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.
Stops all CPUCLK besides the free running clocks. Internal pull-up of
150K nominal
49
PCI_STOP#
IN
50
51
CPU_STOP#
FS_A
IN
IN
Frequency select pin, see Frequency table for functionality
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
52
IREF
OUT
53
54
55
56
GND
PWR
PWR
PWR
IN
Ground pin.
Ground pin for core.
3.3V power for the PLL core.
Frequency select pin, see Frequency table for functionality
GNDA
VDDA
FS_B
0701G—10/13/04
3
Integrated
Circuit
ICS952601
Systems, Inc.
General Description
ICS952601 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS952601 is driven with a 14.318MHz crystal. It generates CPU outputs up
to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
Frequency
Dividers
48MHz, USB, DOT, VCH
PLL2
X1
X2
XTAL
REF (1:0)
CPUCLKT (2:0)
CPUCLKC (2:0)
SRCCLKT0
SRCCLKC0
3V66(4:0)
Programmable
Spread
Programmable
Frequency
Dividers
STOP
Logic
SCLK
SDATA
PLL1
CPU_STOP#
PCI_STOP#
Vtt_PWRGD#
PD#
PCICLK (6:0)
PCICLKF (2:0)
Control
Logic
FS_A
I REF
FS_B
Power Groups
Pin Number
Description
VDD
3
GND
6
Xtal, Ref
24
10,16
36
25
11,17
39
3V66 [0:3]
PCICLK outputs
SRCCLK outputs
55
34
N/A
48, 42
54
33
53
45
Master clock, CPU Analog
48MHz, PLL, SCLK, SDATA
IREF
CPUCLK clocks
0701G—10/13/04
4
Integrated
Circuit
ICS952601
Systems, Inc.
Absolute Max
Symbol
Parameter
Min
Max
Units
V
DD + 0.5V
VDD_A
VDD_In
Ts
Tambient
Tcase
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
V
V
°C
°C
°C
V
VDD + 0.5V
GND - 0.5
-65
0
150
70
115
Ambient Operating Temp
Case Temperature
Input ESD protection human body model
ESD prot
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
V
DD + 0.3
3.3 V +/-5%
3.3 V +/-5%
2
1
V
V
VMID
VIL
1.8
V
SS - 0.3
3.3 V +/-5%
VIN = VDD
0.8
V
IIH
-5
5
uA
VIN = 0 V; Inputs with no pull-up
resistors
IIL1
IIL2
IDD3.3OP
IDD3.3PD
-5
uA
uA
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
-200
Full Active, CL = Full load;
Operating Supply Current
Powerdown Current
350
mA
258
29
0.3
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
35
12
mA
mA
MHz
nH
pF
Input Frequency3
Pin Inductance1
Fi
14.31818
3
1
1
1
1
Lpin
7
5
6
5
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
Input Capacitance1
COUT
CINX
pF
pF
From VDD Power-Up or de-
Clk Stabilization1,2
Modulation Frequency
Tdrive_SRC
TSTAB
1.8
33
15
ms
kHz
ns
1,2
1
assertion of PD# to 1st clock
Triangular Modulation
SRC output enable after
PCI_Stop# de-assertion
CPU output enable after
PD# de-assertion
30
1
Tdrive_PD#
300
us
1
Tfall_Pd#
Trise_Pd#
PD# fall time of
PD# rise time of
5
5
ns
ns
1
2
CPU output enable after
CPU_Stop# de-assertion
PD# fall time of
Tdrive_CPU_Stop#
10
us
1
Tfall_CPU_Stop#
Trise_CPU_Stop#
SMBus Voltage
5
5
5.5
0.4
ns
ns
V
1
2
1
1
1
PD# rise time of
VDD
VOL
2.7
4
@ IPULLUP
Low-level Output Voltage
Current sinking at VOL = 0.4 V
SCLK/SDATA
V
IPULLUP
mA
TRI2C
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
1000
300
ns
ns
1
1
Clock/Data Rise Time3
SCLK/SDATA
Clock/Data Fall Time3
TFI2C
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
0701G—10/13/04
5
Integrated
Circuit
ICS952601
Systems, Inc.
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
1
3000
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
770
5
1
mV
-150
150
1
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
756
-7
350
1150
1
mV
1
mV
-300
250
550
140
300
1
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
12
mV
1
-300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
4.9985 5.0000 5.0015
4.9985 5.0266
5.9982 6.0000 6.0018
5.9982 6.0320
7.4978 7.5000 7.5023
7.4978 5.4000
9.9970 10.0000 10.0030
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
9.9970
4.8735
5.8732
7.3728
9.8720
175
10.0533
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Tabsmin
Absolute min period
tr
Rise Time
Fall Time
332
344
30
700
700
125
125
tf
VOH = 0.525V VOL = 0.175V
175
ps
ps
ps
1
1
1
d-tr
d-tf
Rise Time Variation
Fall Time Variation
30
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
49
8
55
%
ps
ps
1
1
1
100
125
tjcyc-cyc
Jitter, Cycle to cycle
37
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
0701G—10/13/04
6
Integrated
Circuit
ICS952601
Systems, Inc.
Electrical Characteristics - 3V66 Mode: 3V66 [4:0]
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
66.66MHz output nominal
66.66MHz output spread
IOH = -1 mA
MIN
-300
14.9955
14.9955
2.4
TYP
15
MAX
300
15.0045
15.0799
UNITS Notes
ppm
ns
1,2
2
Tperiod
Clock period
ns
2
VOH
VOL
Output High Voltage
Output Low Voltage
V
IOL = 1 mA
0.55
-33
V
V OH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
-33
30
mA
mA
mA
mA
V/ns
V/ns
ns
IOH
IOL
Output High Current
Output Low Current
VOL @ MIN = 1.95 V
V
OL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
38
4
4
Edge Rate
Edge Rate
Rise Time
Fall Time
1
1
0.5
0.5
1
1
1
1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.92
1.97
53.1
38
2
2
ns
dt1
Duty Cycle
Skew
45
55
%
ps
ps
1
1
1
tsk1
VT = 1.5 V
250
250
tjcyc-cyc
VT = 1.5 V 3V66
Jitter
139
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
IOH = -1 mA
MIN
-300
TYP MAX
300
UNITS Notes
ppm
ns
1,2
2
29.9910 30 30.0090
29.9910
2.4
Tperiod
Clock period
30.1598
0.55
-33
ns
2
VOH
VOL
Output High Voltage
Output Low Voltage
V
IOL = 1 mA
V
V
OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
OL @ MIN = 1.95 V
-33
30
mA
mA
mA
mA
IOH
IOL
Output High Current
Output Low Current
V
V
OL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
38
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
1
4
4
V/ns
V/ns
ns
1
1
1
1
1
1
1
1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
1.92
1.9
51.4
18
2
2
ns
dt1
55
500
250
%
tsk1
VT = 1.5 V
ps
tjcyc-cyc
VT = 1.5 V 3V66
Jitter
92
ps
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
0701G—10/13/04
7
Integrated
Circuit
ICS952601
Systems, Inc.
Electrical Characteristics - 48MHz DOT Clock
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5-10 pF (unless otherwise specified)
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max
values
MIN
-200
TYP
MAX
200
UNITS Notes
ppm
1,2
2
Tperiod
VOH
Clock period
Output High Voltage
Output Low Voltage
66.66MHz output nominal 20.8257
20.8340
ns
V
IOH = -1 mA
2.4
-33
30
VOL
IOL = 1 mA
0.55
-33
V
V
OH @ MIN = 1.0 V
mA
mA
mA
mA
V/ns
V/ns
IOH
IOL
Output High Current
Output Low Current
VOH @ MAX = 3.135 V
OL @ MIN = 1.95 V
V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
38
4
Edge Rate
Edge Rate
2
2
1
1
4
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
Rise Time
0.5
0.71
1
ns
1
tf1
Fall Time
0.5
45
0.77
49
1
ns
%
1
1
dt1
VT = 1.5 V
Duty Cycle
55
125us period jitter
(8kHz frequency
Long Term Jitter
0.7
2
ns
1
modulation amplitude)
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
Electrical Characteristics - VCH, 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
Tperiod
CONDITIONS
see Tperiod min-max values
66.66MHz output nominal
IOH = -1 mA
MIN TYP MAX UNITS Notes
-200
20.8257
2.4
200
20.8340 ns
V
ppm
1,2
2
VOH
Output High Voltage
VOL
IOH
IOL = 1 mA
Output Low Voltage
0.55
V
V OH @ MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
-33
30
mA
mA
mA
mA
V/ns
V/ns
Output High Current
-33
IOL
Output Low Current
38
2
Edge Rate
Edge Rate
1
1
1
1
Falling edge rate
2
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
Fall Time
1
1
1.43
1.33
48
2
2
ns
ns
%
1
1
1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
dt1
Duty Cycle
45
55
125us period jitter
(8kHz frequency modulation
amplitude)
Long Term Jitter
0.7
6
ns
1
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
0701G—10/13/04
8
Integrated
Circuit
ICS952601
Systems, Inc.
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Long Accuracy
SYMBOL
CONDITIONS
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
MIN
-300
TYP MAX
UNITS
ppm
ns
ppm1
Tperiod
300
Clock period
69.8270
2.4
69.8550
1
Output High Voltage
Output Low Voltage
V
VOH
1
IOL = 1 mA
0.4
-23
V
VOL
V OH @MIN = 1.0 V,
OH@MAX = 3.135 V
V
1
Output High Current
Output Low Current
-29
29
mA
mA
IOH
VOL @MIN = 1.95 V,
@MAX = 0.4 V
VOL
1
27
IOL
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Rise Time
Fall Time
Skew
1
1
1.92
1.92
26
2
2
ns
ns
ps
%
tr1
1
tf1
1
500
55
tsk1
1
VT = 1.5 V
Duty Cycle
45
53.4
284
dt1
1
VT = 1.5 V
Jitter
1000
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
Group to Group Skews at Common Transition Edges
GROUP
200MHZ CPU to
3V661
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
3V66 (4:0) leads 200MHZ
CPU
SCPU200-3V66
-2.1
-1.6 -1.1
ns
3V66 to PCI
DOT-USB
S3V66-PCI
SDOT_USB
SDOT_VCH
3V66 (4:0) leads 33MHz PCI 1.50
3.50
1.00
1.00
ns
ns
ns
2.59
180 degrees out of phase
in phase
0.00
0.00
DOT-VCH
1. 3V66 MHz CL = 0pf, Rseries = 33 ohm. CPU CL = 2 pf, Rseries = 33 ohm, Rshunt = 49.9 ohms.
Measured at the pins of the 952601.
0701G—10/13/04
9
Integrated
Circuit
ICS952601
Systems, Inc.
General I2C serial interface information for the ICS952601
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0701G—10/13/04
10
Integrated
Circuit
ICS952601
Systems, Inc.
I2C Table: Read-Back Register
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Pin #
Name
Control Function
RESERVED
Type
0
1
PWD
-
-
-
-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PCI_STOP#
-
-
-
-
X
X
X
X
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PCI STOP# Read
-
-
-
-
READBACK
READBACK
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
X
X
X
Back
CPU STOP Read
Back
CPU_STOP#
FSB
Freq Select 1 Read
READBACK of CPU(2:0)
Frequency
Back
Freq Select 0 Read
Back
FSA
X
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Control Function
SRC Free-Running
Control
Type
0
1
PWD
37,38
Bit 7
SRC/SRC#
RW
FREE-RUN STOPPABLE
0
37,38
46,47
43,44
40,41
46,47
43,44
40,41
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRC
Output Control
CPU FREE-
RUNNING
CONTROL
Output Control
Output Control
Output Enable
RW
RW
RW
RW
RW
RW
RW
Disable Enable
1
1
1
1
1
1
1
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
Disable
Disable
Disable
Enable
Enable
Enable
I2C Table: Output Control Register
Byte 2
Pin #
37,38
Name
Control Function
Type
0
1
PWD
SRC_PD#
Drive Mode
SRC_Stop#
Drive Mode
Bit 7
0: Driven in PD#
RW
Driven
Hi-Z
0
0: Driven in
PCI_Stop#
37,38
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
RW
RW
RW
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
0
0
0
0
0
CPUT2_PD# Drive Mode
CPUT1_PD# Drive Mode
CPUT0_PD# Drive Mode
CPUT2_Stop Drive Mode
CPUT1_Stop Drive Mode
CPUT0_Stop Drive Mode
46,47
43,44
0:driven in PD#
1: Tri-stated
40,41
46,47
43,44
0:driven when
stopped
1: Tri-stated
40,41
0701G—10/13/04
11
Integrated
Circuit
ICS952601
Systems, Inc.
I2C Table: Output Control Register
Byte 3
Pin #
Name
Control Function
PCI_Stop# Control
0:all stoppable PCI
and SRC are
Type
0
1
PWD
7,8,9,12,13,14,15,
18,19,20,37,38,
Bit 7
PCI_Stop#
RW
Enable
Disable
1
stopped
20
19
18
15
14
13
12
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
PCICLK0
Output Control
RW
Disable
Enable
1
I2C Table: Output Control Register
Byte 4
Pin #
Name
Control Function
0=2x drive
Type
0
1
PWD
48MHz_USB
2x output drive
48MHz_USB
PCIF2
31
Bit 7
RW
2x drive
Disable
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
FREE-RUN STOPPABLE
Disable
Disable
Disable
normal
Enable
0
31
9
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output Control
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
1
1
1
PCI FREE-RUN
NING CONTROL
8
7
9
8
PCIF1
PCIF0
PCICLK_F2
PCICLK_F1
PCICLK_F0
Output Control
Output Control
Output Control
Enable
Enable
Enable
7
I2C Table: Output Control Register
Byte 5
Bit 7
Pin #
Name
48MHZ_DOT
RESERVED
3V66_4/VCH
Select
Control Function
Output Control
RESERVED
Type
RW
`
0
1
Enable
-
PWD
1
0
32
-
Disable
-
Bit 6
29
Bit 5
Output Select
RW
3V66
VCH
0
29
27
26
23
22
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66_4/VCH
3V66_3
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
3V66_2
3V66_1
3V66_0
0701G—10/13/04
12
Integrated
Circuit
ICS952601
Systems, Inc.
I2C Table: Output Control and Fix Frequency Register
Byte 6
Pin #
Name
Control Function
Type
0
1
PWD
1,2,7,8,9,12,13,14,1
5,18,19,20,22,23,26,
27,29,31,32,37,38,4
0,41,43,44,46,47
Bit 7
Test Clock Mode
Test Clock Mode
-
Disable
Enable
0
-
Bit 6
Bit 5
RESERVED
RESERVED
-
-
-
-
-
0
0
FS_A and FS_B
Operation
SRC Frequency
Select
40,41,43,44,46,47
Normal
Test Mode
37,38
Bit 4
Bit 3
RESERVED
RESERVED
-
-
100MHz
-
200MHz
-
0
0
-
7,8,9,12,13,14,15,18
,19,20,22,23,26,27,2
9,31,32,37,38,40,41,
43,44,46,47
Spread
ON
Bit 2
Spread Spectrum Mode
Spread OFF
0
2
1
Bit 1
Bit 0
REF1
REF0
Output Control
Output Control
RW
RW
Disable
Disable
Enable
Enable
1
1
I2C Table: Vendor & Revision ID Register
Byte 7
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
X
X
X
X
0
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
0701G—10/13/04
13
Integrated
Circuit
ICS952601
Systems, Inc.
PCI Stop Functionality
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.
PCI_STOP#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI USB/DOT
REF
Note
1
0
Normal Normal Normal Normal 66MHz
33MHz
Low
48MHz
48MHz
14.318MHz
14.318MHz
Normal Normal Iref * 6
or Float
Low
66MHz
PCI_STOP# Assertion (transition from '1' to '0')
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.
Tsu
PCI_STOP#
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - De-assertion
The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.
Tsu
Tdrive_SRC
PCI_STOP#
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
0701G—10/13/04
14
Integrated
Circuit
ICS952601
Systems, Inc.
CPU_STOP# Functionality
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU_STOP#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI USB/DOT
REF
Note
1
0
Normal
Normal Normal Normal 66MHz
33MHz
33MHz
48MHz
48MHz
14.318MHz
14.318MHz
Iref * 6 or
Float
Low
Normal Normal 66MHz
CPU_STOP# - Assertion (transition from '1' to '0')
Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the I2C
CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a '0', CPU output will stop CPU_True
= HIGH and CPU_Complement = LOW. When the I2C CPU_Stop tri-state bit corresponding to the CPU output of interest is
programmed to a '1', CPU outputs will be tri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of CPU_Stop# all stopped CPU outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 CPU clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped CPU outputs will be driven High within 10nS of CPU_Stop# de-assertion to
a voltage greater than 200mV.
CPU_Stop#
CPU
CPU#
CPU Internal
Tdrive_CPU_Stop, 10nS >200mV
0701G—10/13/04
15
Integrated
Circuit
ICS952601
Systems, Inc.
PD#, Power Down
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.
When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start
without glitches.
PWRDWN#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI USB/DOT
REF
14.318MHz
Low
Note
1
0
Normal
Normal Normal Normal 66MHz
33MHz
Low
48MHz
Low
Iref * 2 or
Float
Float
Iref * 2
or Float
Float
Low
Notes:
1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.
2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.
PD# Assertion
PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at
2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
0701G—10/13/04
16
Integrated
Circuit
ICS952601
Systems, Inc.
PD# De-assertion
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300µs of PD# deassertion.
Tstable
<1.8mS
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tdrive_PwrDwn#
<300µS, >200mV
3V66_4/VCH Pin Functionality
The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is
3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output
will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising
edge of DOT_48 clock.
3V66
3V66_4/VCH
DOT_48
7.49nS min
0701G—10/13/04
17
Integrated
Circuit
ICS952601
Systems, Inc.
Differential Clock Tristate
To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or
tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during
PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the
corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",
"SRC_Stop" and "PwrDwn" register bit settings.
Signal
Pin PD#
Pin
CPU_Stop
Pwrdwn
Non-Stoppable
Outputs
Stoppable
Outputs
CPU_Stop# Tristate Bit Tristate Bit
CPU[2:0}
CPU[2:0}
CPU[2:0}
CPU[2:0}
CPU[2:0}
1
1
1
0
0
1
0
X
X
X
X
0
Running
Running
Running
Running
Driven @ Iref x 6
Tristate
0
1
0
X
X
X
X
Driven @ Iref x 2 Driven @ Iref x 2
Tristate Tristate
1
Notes:
1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
Signal
Pin PD#
Pin
PCI_Stop#
PCI_Stop
Tristate Bit Tristate Bit
Pwrdwn
Non-Stoppable
Output
Stoppable
Output
SRC
SRC
SRC
SRC
SRC
1
1
1
0
0
1
0
X
X
X
X
0
Running
Running
Running
Running
Driven @ Iref x 6
Tristate
0
1
0
X
X
X
X
Driven @ Iref x 2 Driven @ Iref x 2
Tristate Tristate
1
Notes:
1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
0701G—10/13/04
18
Integrated
Circuit
ICS952601
Systems, Inc.
CPU Clock Tristate Timing
The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
CPU_Stop = Driven, CPU_Pwrdwn = Driven
1.8mS
CPU_Stop#
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")
CPU_Stop = Tristate, CPU_Pwrdwn = Driven
1.8mS
CPU_Stop#
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.
0701G—10/13/04
19
Integrated
Circuit
ICS952601
Systems, Inc.
CPU_Stop = Driven, CPU_Pwrdwn = Tristate
1.8mS
CPU_Stop#
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the
assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected.
2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately
after the 1.8mS windows expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
CPU_Stop = Tristate, CPU_Pwrdwn = Tristate
1.8mS
CPU_Stop#
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of
CPU_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
0701G—10/13/04
20
Integrated
Circuit
ICS952601
Systems, Inc.
SRC Clock Tristate Timing
The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and
SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
SRC_Stop = Driven, SRC_Pwrdwn = Driven
1.8mS
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output
clock (assuming clock's OE bit is set to "1")
SRC_Stop = Tristate, Pwrdwn = Tristate
1.8mS
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of
PCI_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
0701G—10/13/04
21
Integrated
Circuit
ICS952601
Systems, Inc.
PCI_STOP Asserted
SRC_Stop = Tristate, SRC_Pwrdwn = Tristate
1.8mS
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
Notes:
1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop#
and PWRDWN#.
2. In the case that PCI_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the PCI_Stop# high with the internal rising edges of CPU clock#. This will result in SRC clocks resuming
immediately after the 1.8mS window expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
0701G—10/13/04
22
Integrated
Circuit
ICS952601
Systems, Inc.
c
56-Lead, 300 mil Body, 25 mil, SSOP
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS
COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
h x 45°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
a
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- C -
D mm.
D (inch)
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
e
SEATING
PLANE
56
b
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS952601yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0701G—10/13/04
23
Integrated
Circuit
ICS952601
Systems, Inc.
c
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
N
(240 mil)
(20 mil)
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
INDEX
AREA
c
1
2
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
A
A2
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A1
- C -
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
b
N
MIN
13.90
MAX
14.10
MIN
.547
MAX
.555
aaa
C
56
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS952601yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0701G—10/13/04
24
相关型号：
ICS952601YGT
Processor Specific Clock Generator, 400MHz, PDSO56, 0.240 INCH, 0.020 INCH, MO-153, TSSOP-56
IDT
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