ICS954201 [ICSI]
Programmable Timing Control Hub⑩ for Mobile P4⑩ Systems; 可编程定时控制中心™移动P4 ™系统
| 型号： | ICS954201 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable Timing Control Hub⑩ for Mobile P4⑩ Systems |
| 文件： | 总15页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS954201
Systems, Inc.
Programmable Timing Control Hub™ for Mobile P4™ Systems
Recommended Application:
Features/Benefits:
CK410M clock, Intel Yellow Cover part
•
Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
Output Features:
•
Supports spread spectrum modulation, 0 to -0.5%
down spread
•
•
2 - 0.7V current-mode differential CPU pairs
7 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
•
•
Supports CPU clocks up to 400MHz
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
1 - 0.7V current-mode differential CPU/SRC selectable
pair
•
Supports undriven differential CPU, SRC pair in PD#
for power management.
•
•
•
•
•
4 - PCI (33MHz)
2 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 96MHz, 0.7V current differential pair
1 - REF, 14.318MHz
Key Specifications:
•
•
•
•
•
CPU outputs cycle-cycle jitter < 85ps
SRC outputs cycle-cycle jitter < 125ps
PCI outputs cycle-cycle jitter < 500ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
+/- 100ppm frequency accuracy on USB clocks
Pin Configuration
Functionality
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
PCICLK5 5
56 PCICLK2
FS_C1 FS_B2 FS_A2
55 PCI/SRC_STOP#
54 CPU_STOP#
53 FS_C/TEST_SEL
52 REFOUT
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
100.00 33.33 14.318
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
PCICLK_F1 9
Vtt_PwrGd#/PD 10
VDD48 11
USB_48MHz/FS_A 12
GND 13
RESERVED
14.318
1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
45 GND
44 CPUCLKT0
43 CPUCLKC0
42 VDDCPU
41 CPUCLKT1
40 CPUCLKC1
39 IREF
DOTT_96MHz 14
DOTC_96MHz 15
FS_B/TEST_MODE 16
SRCCLKT0 17
SRCCLKC0 18
SRCCLKT1 19
SRCCLKC1 20
VDDSRC 21
SRCCLKT2 22
SRCCLKC2 23
SRCCLKT3 24
SRCCLKC3 25
SRCCLKT4_SATA 26
SRCCLKC4_SATA 27
VDDSRC 28
38 GNDA
37 VDDA
36 CPUCLKT2_ITP/SRCCLKT7
35 CPUCLKC2_ITP/SRCCLKC7
34 VDDSRC
33 SRCCLKT6
32 SRCCLKC6
31 SRCCLKT5
30 SRCCLKC5
29 GND
56-pin SSOP & TSSOP
0819G—12/06/04
Integrated
Circuit
ICS954201
Systems, Inc.
Pin Description
PIN
TYPE
PIN # PIN NAME
DESCRIPTION
1
2
3
4
5
6
7
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
PWR Power supply for PCI clocks, nominal 3.3V
PWR Ground pin.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin.
PWR Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
VDDPCI
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
8
9
ITP_EN/PCICLK_F0
PCICLK_F1
I/O
OUT Free running PCI clock not affected by PCI_STOP# .
Vtt_PwrGd# is an active low input used to determine when
latched inputs are ready to be sampled. PD is an asynchronous
active high input pin used to put the device into a low power
state. The internal clocks, PLLs and the crystal oscillator are
stopped.
10 Vtt_PwrGd#/PD
IN
11 VDD48
PWR Power pin for the 48MHz output.3.3V
Frequency select latch input pin / Fixed 48MHz USB clock
output. 3.3V.
12 USB_48MHz/FS_A
I/O
13 GND
PWR Ground pin.
14 DOTT_96MHz
OUT True clock of differential pair for 96.00MHz DOT clock.
15 DOTC_96MHz
OUT Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
16 FS_B/TEST_MODE
IN
TEST_MODE is a real time input to select between Hi-Z and
REF/N divider mode while in test mode. Refer to Test
Clarification Table.
17 SRCCLKT0
18 SRCCLKC0
19 SRCCLKT1
20 SRCCLKC1
21 VDDSRC
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR Supply for SRC clocks, 3.3V nominal
22 SRCCLKT2
23 SRCCLKC2
24 SRCCLKT3
25 SRCCLKC3
26 SRCCLKT4_SATA
27 SRCCLKC4_SATA
28 VDDSRC
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC/SATA pair.
OUT Complement clock of differential SRC/SATA pair.
PWR Supply for SRC clocks, 3.3V nominal
0819G—12/06/04
2
Integrated
Circuit
ICS954201
Systems, Inc.
Pin Description (Continued)
PIN # PIN NAME
29 GND
TYPE DESCRIPTION
PWR Ground pin.
30 SRCCLKC5
31 SRCCLKT5
32 SRCCLKC6
33 SRCCLKT6
34 VDDSRC
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
PWR Supply for SRC clocks, 3.3V nominal
Complimentary clock of CPU_ITP/SRC differential pair
CPU_ITP/SRC output. These are current mode outputs.
External resistors are required for voltage bias. Selected by
ITP_EN input.
35 CPUCLKC2_ITP/SRCCLKC7
OUT
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
OUT output. These are current mode outputs. External resistors are
required for voltage bias. Selected by ITP_EN input.
PWR 3.3V power for the PLL core.
36 CPUCLKT2_ITP/SRCCLKT7
37 VDDA
38 GNDA
PWR Ground pin for the PLL core.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
39 IREF
OUT
current. 475 ohms is the standard value.
Complimentary clock of differential pair CPU outputs. These are
OUT current mode outputs. External resistors are required for voltage
bias.
40 CPUCLKC1
True clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
PWR Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential pair CPU outputs. These are
OUT current mode outputs. External resistors are required for voltage
bias.
41 CPUCLKT1
42 VDDCPU
OUT
43 CPUCLKC0
True clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44 CPUCLKT0
OUT
45 GND
46 SCLK
47 SDATA
48 VDDREF
49 X2
PWR Ground pin.
IN
I/O
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
PWR Ref, XTAL power supply, nominal 3.3V
OUT Crystal output, Nominally 14.318MHz
50 X1
IN
Crystal input, Nominally 14.318MHz.
51 GND
52 REFOUT
PWR Ground pin.
OUT Reference Clock output
3.3V tolerant input for CPU frequency selection. Low voltage
threshold inputs, see input electrical characteristics for Vil_FS
and Vih_FS values.
53 FS_C/TEST_SEL
IN
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
54 CPU_STOP#
IN
IN
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running
clocks at logic 0 level, when input low
55 PCI/SRC_STOP#
56 PCICLK2
OUT PCI clock output.
0819G—12/06/04
3
Integrated
Circuit
ICS954201
Systems, Inc.
General Description
ICS954201 is a CK410M Yellow Cover clock synthesizer. ICS954201 provides a single-chip solution for mobile systems built
with Intel P4-M processors and Intel mobile chipsets. ICS954201 is driven with a 14.318MHz crystal and generates CPU
outputs up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI-Express.
Block Diagram
REF
USB_48MHz
X1
XTAL
OSC.
FIXED PLL
DIVIDER
X2
DOT_96MHz
PCICLK(5:2)
PCICLK_F(1:0)
SRCCLK(6:0)
PROG.
SPREAD
MAIN PLL
PROG.
DIVIDERS
CPUCLK2_ITP/SRCCLK7
CPUCLK(1:0)
PCI/SRC_STOP#
CPU_STOP#
FS(C:A)
ITP_EN
CONTROL
LOGIC
TEST_MODE
TEST_SEL
VTT_PWRGD#/PD
SDATA
SCLK
IREF
Power Groups
Pin Number
Description
VDD
48
1,7
21,28,34
37
GND
51
2,6
29
Xtal, Ref
PCICLK outputs
SRCCLK outputs
38
Master clock, CPU Analog
DOT, USB, PLL_48
CPUCLK clocks
11
13
42
45
0819G—12/06/04
4
Integrated
Circuit
ICS954201
Systems, Inc.
General I2C serial interface information for the ICS954201
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
starT bit
T
T
starT bit
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0819G—12/06/04
5
Integrated
Circuit
ICS954201
Systems, Inc.
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
V
V
DD + 0.5V
DD + 0.5V
V
V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
-65
0
150
70
115
°C
°C
°C
Input ESD protection
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
VIH
CONDITIONS
3.3 V +/-5%
MIN
2
TYP
MAX UNITS Notes
Input High Voltage
VDD + 0.3
V
1
Input Low Voltage
Input High Current
VIL
IIH
3.3 V +/-5%
VIN = VDD
VSS - 0.3
-5
0.8
5
V
1
1
uA
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
IIL1
IIL2
-5
uA
uA
1
1
Input Low Current
-200
Low Threshold Input High
Voltage
VIH_FS
3.3 V +/-5%
0.7
VDD + 0.3
0.35
V
V
1
1
Low Threshold Input Low
Voltage
Operating Supply Current
VIL_FS
IDD3.3OP
IDD3.3PD
3.3 V +/-5%
VSS - 0.3
Full Active, CL = Full load;
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
278
67
4.8
400
70
12
mA
mA
mA
Powerdown Current
Input Frequency3
Pin Inductance1
Fi
14.31818
MHz
3
1
1
1
1
Lpin
7
5
6
5
nH
pF
pF
pF
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
Input Capacitance1
COUT
CINX
From VDD Power-Up or de-
assertion of PD# to 1st clock
Triangular Modulation
SRC output enable after
PCI_STOP de-assertion
Differential output enable after
PD# de-assertion
Clk Stabilization1,2
Modulation Frequency
Tdrive_SRC
TSTAB
1.3
8
1.8
33
10
ms
kHz
ns
1,2
1
30
1
Tdrive_PD
300
us
1
Tfall_PD
Trise_PD
PD# fall time of
PD# rise time of
5
5
ns
ns
1
2
CPU output enable after
CPU_STOP de-assertion
CPU_STOP fall time of
CPU_STOP rise time of
Tdrive_CPU_STOP
8
10
ns
1
Tfall_CPU_STOP
Trise_CPU_STOP#
SMBus Voltage
5
5
5.5
ns
ns
V
1
2
1
VDD
VOL
2.7
4
Low-level Output Voltage
SDATA, SCLK @ IPULLUP
0.4
V
1
1
Current sinking
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
IPULLUP
VOL = 0.4 V
mA
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
TRI2C
1000
300
ns
ns
1,3
1,3
TFI2C
Clock/Data Fall Time
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
0819G—12/06/04
6
Integrated
Circuit
ICS954201
Systems, Inc.
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Zo1
CONDITIONS
VO = Vx
MIN
TYP
MAX
UNITS Notes
Current Source Output
Impedance
3000
Ω
1
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
Voltage High
Voltage Low
Max Voltage
VHigh
VLow
Vovs
Vuds
Vcross
660
-150
760
2
782
-33
850
150
1150
1,3
1,3
1
mV
mV
mV
mV
Min Voltage
-300
250
1
Crossing Voltage (abs)
344
97
550
1
1
(abs)
Variation of crossing over all
edges
see Tperiod min-max values
100.00MHz non-spread
100.00MHz spread
100.00MHz non-spread
100.00MHz spread
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
140
300
-300
ppm
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
1,2
1,2
1
1
1
1
9.9999 10.0030
10.0533
9.9999 10.1280
10.1783
260
212
20
Tperiod
Average period
9.9970
Tabs
Absolute min/max period
9.8720
tr
tf
d-tr
d-tf
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V, VOL = 0.175V
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
175
175
700
700
125
125
13
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
51
87
37
55
%
ps
ps
1
1
1
VT = 50%
250
125
Measurement from differential
wavefrom
tjcyc-cyc
Jitter, Cycle to cycle
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
0819G—12/06/04
7
Integrated
Circuit
ICS954201
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
850
UNITS Notes
Current Source Output
Impedance
VO = Vx
Zo
3000
1
Ω
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
727
-2
1,3
1,3
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Vovs
Vuds
Vcross
752
-21
1150
1
1
mV
mV
mV
-300
250
Crossing Voltage (abs)
348
39
550
140
1
1
(abs)
Variation of crossing over all
edges
see Tperiod min-max values
400MHz non-spread
400MHz spread
333.33MHz non-spread
333.33MHz spread
266.66MHz non-spread
266.66MHz spread
200MHz non-spread
200MHz spread
166.66MHz non-spread
166.66MHz spread
133.33MHz non-spread
133.33MHz spread
100.00MHz non-spread
100.00MHz spread
400MHz non-spread
400MHz spread
333.33MHz non-spread
333.33MHz spread
266.66MHz non-spread
266.66MHz spread
200MHz non-spread
200MHz spread
166.66MHz non-spread
166.66MHz spread
133.33MHz non-spread
133.33MHz spread
100.00MHz non-spread
100.00MHz spread
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
2.4999
3.0000
3.7509
4.9998
6.0000
7.5017
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
Tperiod
Average period
9.9970 10.0000 10.0030
9.9970
10.0533
2.5750
2.4970
2.9940
3.7430
4.9940
5.9950
7.4970
2.4143
2.5983
3.0859
3.1010
3.8361
3.8550
5.0865
5.1116
6.0868
6.1170
7.5873
7.6250
2.9141
3.6639
4.9135
5.9132
7.4128
9.9120
Tabs
Absolute min/max period
10.0000 10.0880
10.1383
230
206
15
tr
tf
d-tr
d-tf
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
175
175
700
700
125
125
ps
ps
ps
1
1
1
14
Measurement from differential
wavefrom
dt3
Duty Cycle
Skew
45
51
55
%
1
CPU(1:0), VT = 50%
CPU2_ITP, VT = 50%
Differential waveform
measurement, CPU(1:0)
Differential waveform
measurement, CPU2_ITP
7.5
145
100
150
ps
ps
1
1
tsk3
tjcyc-cyc
tjcyc-cyc
Jitter, Cycle to cycle
Jitter, Cycle to cycle
36
96
85
ps
ps
1
1
125
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
0819G—12/06/04
8
Integrated
Circuit
ICS954201
Systems, Inc.
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
CONDITIONS
MIN
-300
TYP
35
MAX UNITS Notes
see Tperiod min-max values
33.33MHz output non-spread
33.33MHz output spread
33.33MHz output non-spread
33.33MHz output spread
IOH = -1 mA
300
ppm
ns
ns
1,2
2
2
29.9989 30.0090
30.0752 30.1598
30.5090
Tperiod
29.9910
ns
ns
V
1,2
1,2
1
Absolute min/max period
Tabs
29.4910
2.4
30.6598
Output High Voltage
Output Low Voltage
VOH
VOL
3.25
IOL = 1 mA
OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
0.05
-62
-10
61
0.55
-33
V
1
1
1
1
1
1
1
1
V
-33
30
mA
mA
mA
mA
V/ns
V/ns
ns
Output High Current
Output Low Current
IOH
IOL
23
38
4
4
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
1
1
0.5
0.5
45
1.60
1.71
1.25
1.17
50
Falling edge rate
tr1
tf1
dt1
tsk1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
2
ns
1
55
500
%
ps
1
1
VT = 1.5 V
81
Jitter
tjcyc-cyc
VT = 1.5 V
250
500
ps
1
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Electrical Characteristics - 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
-100
TYP
0.25
MAX UNITS Notes
Long Accuracy
Clock period
Absolute min/max period
ppm
Tperiod
Tabs
see Tperiod min-max values
48.00000 MHz output
100
ppm
ns
1,2
2
20.8313 20.8333 20.8354
20.4813
2.4
48.00000 MHz output
21.1854
ns
1,2
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = -1 mA
IOL = 1 mA
3.25
0.05
-53
V
1
1
1
1
1
1
1
1
0.55
V
V
OH @ MIN = 1.0 V
-29
29
mA
mA
mA
mA
V/ns
V/ns
Output High Current
Output Low Current
IOH
IOL
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
-6.2
61
-23
V
OL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
23
1.53
1.68
27
2
Edge Rate
Edge Rate
1
1
2
Rise Time
Fall Time
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
1.31
1.19
52
2
2
ns
ns
%
1
1
1
Duty Cycle
dt1
45
55
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
139
350
ps
1
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0819G—12/06/04
9
Integrated
Circuit
ICS954201
Systems, Inc.
Electrical Characteristics - DOT, 96MHz 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Zo1
CONDITIONS
VO = Vx
MIN
TYP
MAX
UNITS Notes
Current Source Output
Impedance
3000
1
Ω
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
Voltage High
Voltage Low
Max Voltage
VHigh
VLow
Vovs
Vuds
Vcross
660
-150
749
1.5
778
-51
850
150
1150
1,3
1,3
1
mV
mV
mV
mV
Min Voltage
-300
250
1
Crossing Voltage (abs)
Crossing Voltage (var)
358
26
550
1
1
(abs)
Variation of crossing over all
edges
see Tperiod min-max values
d-Vcross
140
100
Long Accuracy
Average period
ppm
Tperiod
Tabs
tr
tf
d-tr
d-tf
-100
ppm
ns
1,2
2
96.00MHz
10.4156 10.4167 10.4177
10.1656 10.4100 10.6677
175
175
Absolute min/max period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
96.00MHz
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V, VOL = 0.175V
ns
ps
ps
ps
1,2
1
1
1
1
210
180
23
700
700
125
125
50
ps
Measurement from differential
wavefrom
Measurement from differential
dt3
Duty Cycle
45
49
98
55
%
1
1
tjcyc-cyc
Jitter, Cycle to cycle
250
ps
wavefrom
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
SYMBO
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS Notes
L
Long Accuracy
Clock period
ppm
Tperiod
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
-300
300
ppm
ns
1
1
69.8270 69.841 69.8550
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
-33
30
3.25
0.05
-53
-6
V
1
IOL = 1 mA
0.4
-33
38
V
1
VOH @ MIN = 1.0 V
mA
mA
mA
mA
mA
mA
mA
mA
ns
1
Output High Current (1X)
Output Low Current (1X)
Output High Current (2X)
Output Low Current (2X)
IOH
IOL
IOH
IOL
V
V
OH@ MAX = 3.135 V
OL @MIN = 1.95 V
1
60.9
23
1
VOL @ MAX = 0.4 V
OH @ MIN = 1.0 V
VOH@ MAX = 3.135 V
1
V
-33
-110
-12
110
47
1
-33
1
V
V
OL @MIN = 1.95 V
OL @ MAX = 0.4 V
1
1
Rise Time
Fall Time
Duty Cycle
Jitter
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
1.7
1.9
54
2
2
1
ns
1,2
dt1
45
55
%
1,2
1
tjcyc-cyc
VT = 1.5 V
197
1000
ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0819G—12/06/04
10
Integrated
Circuit
ICS954201
Systems, Inc.
SMBus Table: Output Control Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
CPUCLK2_ITP/SRCCLK7 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
SRCCLK6 Enable
SRCCLK5 Enable
SRCCLK4 Enable
SRCCLK3 Enable
SRCCLK2 Enable
SRCCLK1 Enable
SRCCLK0 Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
RW
RW
RW
RW
RW
RW
RW
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
DISABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
1
1
1
1
1
1
1
SMBus Table: Spreading and Device Behavior Control Register
Byte 1
Bit 7
Pin #
Name
PCI_F0 Enable
DOT_96MHz Enable
USB_48MHz Enable
REFOUT Enable
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
RESERVED
Type
RW
RW
RW
RW
0
1
PWD
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CPUCLK1
CPUCLK0
Output Enable
Output Enable
RW
RW
Disable
Disable
Enable
Enable
SPREAD
ON
Bit 0
Spread Spectrum Mode
Spread Off
RW SPREAD OFF
0
SMBus Table: Output Control Register
Byte 2 Pin #
Bit 7
Name
PCICLK5
Control Function
Output Enable
Type
RW
0
1
PWD
1
Disable
Enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK4
PCICLK3
PCICLK2
Output Enable
Output Enable
Output Enable
RESERVED
RESERVED
RESERVED
RW
RW
RW
Disable
Disable
Disable
Enable
Enable
Enable
1
1
1
1
1
1
1
PCI_F1 Enable
Output Enable
RW
Disable
Enable
0819G—12/06/04
11
Integrated
Circuit
ICS954201
Systems, Inc.
SMBus Table: SRC Stop Control Register
Byte 3
Bit 7
Pin #
36,35
Name
Control Function
Type
0
1
PWD
SRCCLK7
SRCCLK6
SRCCLK5
SRCCLK4
SRCCLK3
SRCCLK2
SRCCLK1
SRCCLK0
RW Free-Running Stoppable
RW Free-Running Stoppable
RW Free-Running Stoppable
RW Free-Running Stoppable
RW Free-Running Stoppable
RW Free-Running Stoppable
RW Free-Running Stoppable
RW Free-Running Stoppable
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
33,32
31,30
26,27
24,25
22,23
19,20
17,18
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
SRC clocks
SMBus Table: Stop and Output Control Register
Byte 4
Bit 7
Bit 6
Bit 5
Pin #
Name
Control Function
RESERVED
Type
0
1
PWD
X
0
0
Driven in PD
14,15
DOT_96MHz
RW
Driven
Hi-Z
RESERVED
Allow assertion of
Bit 4
Bit 3
9
8
PCI_F1
PCI_F0
RW Free-Running Stoppable
RW Free-Running Stoppable
0
0
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
PCICLK_F outputs
Allow assertion of
CPU_STOP# to stop
CPUCLK outputs
Bit 2
Bit 1
Bit 0
36,35
41,40
44,43
CPUCLK2_ITP
CPUCLK1
RW Free-Running Stoppable
RW Free-Running Stoppable
RW Free-Running Stoppable
1
1
1
CPUCLK0
SMBus Table: Output Control Register
Byte 5
Pin #
Name
Control Function
Driven in
PCI/SRC_STOP#
Type
0
1
PWD
Bit 7
SRCCLK(7:0)
SRC_STOP Drive Mode
RW
Driven
Hi-Z
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
36,35
41,40
44,43
CPUCLK2_ITP_STOP Drive Mode
CPUCLK1_STOP Drive Mode
CPUCLK0_STOP Drive Mode
SRC_PD Drive Mode
CPUCLK2_ITP_PD Drive Mode
CPUCLK1_PD Drive Mode
CPUCLK0_PDDrive Mode
RW
RW
RW
RW
RW
RW
RW
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
0
0
0
0
0
Driven in CPU_STOP#
SRCCLK(7:0)
36,35
Driven in Powerdown
(PD)
41,40
44,43
0819G—12/06/04
12
Integrated
Circuit
ICS954201
Systems, Inc.
SMBus Table: Test and Readback Control Register
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Pin #
Name
Test Mode Selection
Test Clock Mod eEntry
Control Function
Test Mode Selection
Test Mode
RESERVED
Strength Prog
Stop all PCI and SRC
clocks
Type
RW
RW
0
Hi-Z
Disable
1
PWD
-
-
-
-
REF/N
Enable
0
0
0
1
REFOUT STRENGTH
PCI/SRC_STOP
RW
RW
1X
2X
-
Enabled
Disabled
1
Bit 3
-
-
-
FS_C
FS_B
FS_A
readback
readback
readback
R
R
R
-
-
-
-
-
-
LATCHED
LATCHED
LATCHED
Bit 2
Bit 1
Bit 0
SMBus Table: Vendor & Revision ID Register
Byte 7
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
1
0
0
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
Test Clarification Table
Comments
HW
SW
TEST
FS_C/TEST FS_B/TEST ENTRY REF/N or
_SEL
_MODE
BIT
B6b6
0
HI-Z
B6b7
X
HW PIN HW PIN
OUTPUT
NORMAL
0
1
1
X
0
0
X
X
X
0
1
0
HI-Z
· FS_C/TEST_SEL is a 3-level latched input.
o Power-up w/ V >= 2.0V to select TEST
o Power-up w/ V < 2.0V to have pin function as
FS_C.
REF/N
REF/N
1
1
0
1
· When pin is FS_C, VIH_FS and VIL_FS levels
apply.
1
X
1
1
0
REF/N
HI-Z
· FS_B/TEST_MODE is a low-threshold input
o VIH_FS and VIL_FS levels apply.
o TEST_MODE is a real time input
· TEST_SEL can be invoked after power up
through SMBus B6b6.
X
o If TEST is selected by B6b6, only B6b7 controls
TEST_MODE. The FS_B/TEST_Mode pin is not
used.
0
X
1
1
REF/N
· Power must be cycled to exit TEST.
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
0819G—12/06/04
13
Integrated
Circuit
ICS954201
Systems, Inc.
c
56-Lead, 300 mil Body, 25 mil, SSOP
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS
COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
hh xx 45°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
a
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- C -
D mm.
D (inch)
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
e
SEATING
PLANE
56
b
.10 (.004) C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS954201yFLNT
Example:
ICS XXXX y F LN T
Designation for tape and reel packaging
Annealed Lead Free
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0819G—12/06/04
14
Integrated
Circuit
ICS954201
Systems, Inc.
c
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
N
(240 mil)
(20 mil)
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
INDEX
AREA
c
1
2
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
A
A2
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A1
- C -
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
b
N
MIN
13.90
MAX
14.10
MIN
.547
MAX
.555
aaa
C
56
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS954201yGLNT
Example:
ICS XXXX y G LN T
Designation for tape and reel packaging
Annealed Lead Free
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0819G—12/06/04
15
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