ICS9DB202CFLFT [ICSI]
Two 0.7V current mode differential HCSL output pairs, 1 differential clock input; 两个0.7V电流模式差分HCSL输出对， 1差分时钟输入
| 型号： | ICS9DB202CFLFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Two 0.7V current mode differential HCSL output pairs, 1 differential clock input |
| 文件： | 总11页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
GENERAL DESCRIPTION
Features
The ICS9DB202 is a high perfromance 1-to-2 Dif- • Two 0.7V current mode differential HCSL output pairs
ICS
ferential-to-HCSL Jitter Attenuator designed for use
• 1 differential clock input
HiPerClockS™
in PCI Express™ systems. In some PCI Express™
systems, such as those found in desktop PCs, the
PCI Express™ clocks are generated from a low
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
bandwidth, high phase noise PLL frequency synthesizer.In these
systems, a jitter-attenuating device may be necessary in order
to reduce high frequency random and deterministic jitter com-
ponents from the PLL synthesizer and from the system board.
The ICS9DB202 has two PLL bandwidth modes. In low band-
width mode, the PLL loop bandwidth is 500kHz.This setting of-
fers the best jitter attenuation and is still high enough to pass a
triangular input spread spectrum profile. In high bandwidth mode,
the PLL bandwidth is at 1MHz and allows the PLL to pass more
spread spectrum modulation.
• Maximum output frequency: 140MHz
• Output skew: 110ps (maximum)
• Cycle-to-cycle jitter: 110ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
For serdes which have x10 reference multipliers instead of x12.5
multipliers, each of the two PCI Express™ outputs (PCIEX0:1)
can be set for 125MHz instead of 100MHz by configuring the
appropriate frequency select pins (FS0:1).
• Industrial temperature information available upon request
PIN ASSIGNMENT
VDDA
BYPASS
IREF
FS1
VDD
PLL_BW
CLK
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
nCLK
FS0
VDD
BLOCK DIAGRAM
IREF
Current
Set
-
GND
GND
+
PCIEXT1
PCIEXC1
VDD
PCIEXT0
PCIEXC0
VDD
9
10
1 HiZ
0 Enabled
nOE0
nOE1
nOE0
ICS9DB202
20-LeadTSSOP
6.50mm x 4.40mm x 0.92
package body
0
1
PCIEXT0
nPCIEXC0
nCLK
CLK
Loop
Filter
Phase
Detector
0 ÷4
1 ÷5
VCO
G Package
Top View
ICS9DB202
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm
body package
FS0
÷5
F Package
TopView
Internal Feedback
0
1
PCIEXT1
nPCIEXC1
0 ÷5
1 ÷4
FS1
BYPASS
nOE1
1 HiZ
0 Enabled
9DB202CG
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REV. A OCTOBER 6, 2004
1
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
PLL_BW
CLK
Type
Pullup
Description
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
1
2
Input
Input
Pulldown Non-inverting differential clock input.
Pullup/
3
nCLK
Input
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
4
FS0
VDD
Input
Power
Power
Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
Core supply pins.
5, 9, 12, 16
6, 15
GND
Power supply ground.
PCIEXT0,
PCIEXC0
7, 8
Output
Input
Differential output pairs. HCSL interface levels.
Output enable. When HIGH, forces outputs to HiZ state.
Pulldown
10, 11
nOE0, nOE1
When LOW, enables outputs. LVCMOS/LVTTL interface levels.
PCIEXC1,
PCIEXT1
13, 14
17
Output
Input
Differential output pairs. HCSL interface levels.
FS1
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
A fixed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode PCIEX clock outputs.
BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode.
18
IREF
Input
19
20
BYPASS
VDDA
Power Pulldown
Power
LVCMOS/LVTTL interface levels.
Analog supply pin. Requires 24Ω series resistor.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3B. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS1
TABLE 3C. BYPASS TABLE
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS0
Inputs
Mode
Inputs
Outputs
PCIEX0
5/4
Inputs
Outputs
PCIEX1
1
BYPASS
FS0
0
FS1
0
0
PLL Mode
Bypass Mode
(output = inputs)
1
1
1
1
5/4
TABLE 3D. OUTPUT ENABLE
FUNCTION TABLE, NOE0
TABLE 3E. OUTPUT ENABLE
FUNCTION TABLE, NOE1
TABLE 3F. PLL BANDWIDTH TABLE
Inputs
Outputs
PCIEX0
Enabled
HiZ
Inputs
Inputs
Outputs
PCIEX1
Enabled
HiZ
Bandwidth
PLL_BW
nOE0
nOE1
0
1
0
1
500kHz
1MHz
0
1
9DB202CG
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REV. A OCTOBER 6, 2004
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ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
I
Outputs, VO
PackageThermal Impedance, θ
20 Lead TSSOP
20 Lead SSOP
JA
73.2°C/W (0 lfpm)
80.8°C/W (0 lfpm)
StorageTemperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C, RREF = 475Ω
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
112
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
IDDA
22
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
mV
mV
Input Low Voltage
-0.3
BYPASS,
nOE0, nOE1, FS1
150
5
µA
IIH
Input High Current
VDD = VIN = 3.465V
FS0, PLL_BW
BYPASS,
nOE0, nOE1, FS1
-5
µA
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
FS0, PLL_BW
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C, RREF = 475Ω
Symbol Parameter
Test Conditions
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
Minimum Typical Maximum Units
IIH
Input High Current CLK, nCLK
Input Low Current CLK, nCLK
150
150
µA
µA
V
IIL
VPP
VCMR
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
9DB202CG
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REV. A OCTOBER 6, 2004
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ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
TABLE 4D. HCSL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C, RREF = 475Ω
Symbol Parameter
Test Conditions
Minimum
12
Typical
Maximum Units
IOH
Output Current
14
16
mA
V
VOH
VOL
IOZ
Output High Voltage
680
Output Low Voltage
65
10
V
High Impedance Leakage Current
Output Crossover Voltage
-10
µA
mV
VOX
250
550
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C, RREF = 475Ω
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
140
110
110
50
MHz
ps
tsk(o)
Output Skew; NOTE 1, 2
50
Outputs @ Different Frequencies
Outputs @ Same Frequencies
ps
tjit(cc)
tjit(Ø)
Cycle-to-Cycle Jitter
ps
RMS Phase Jitter
(Random); NOTE 3
Integration Range: 1.5MHz - 22MHz
20ꢀ to 80ꢀ
2.42
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
48
1100
52
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot following this section.
9DB202CG
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REV. A OCTOBER 6, 2004
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ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
TYPICAL PHASE NOISE AT 100MHZ
0
-10
-20
-30
-40
PCI Express™ Filter
100MHz
RMS Phase Jitter (Random)
1.5MHz to 22MHz = 2.42ps (typical)
-50
-60
-70
-80
-90
-100
Raw Phase Noise Data
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
PCI Express™ Filter to raw data
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
The illustrated phase noise plot was taken using a low phase Due to the tracking ability of a PLL, it will track the input signal
noise signal generator, the noise floor of the signal generator is up to its loop bandwidth.Therefore, if the input phase noise is
less than that of the device under test.
greater than that of the PLL, it will increase the output phase
noise performance of the device. It is recommended that the
Using this configuration allows one to see the true spectral purity phase noise performance of the input is verified in order to
or phase noise performance of the PLL in the device under test. achieve the above phase noise performance.
9DB202CG
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REV. A OCTOBER 6, 2004
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ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
3.3V 5ꢀ
VDD
nCLK
CLK
SCOPE
VDD,
VDDA
VPP
VCMR
Cross Points
Qx
HCSL
GND
GND
0V
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PCIEXC0,
PCIEXC1
PCIEXCx
PCIEXTy
PCIEXT0,
PCIEXT1
➤
➤
tcycle n
tcycle n+1
➤
➤
PCIEXCx
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
PCIEXTy
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
PCIEXC0,
PCIEXC1
80ꢀ
tF
80ꢀ
tR
PCIEXT0,
PCIEXT1
VSWING
20ꢀ
Pulse Width
Clock
Outputs
20ꢀ
tPERIOD
tPW
odc =
tPERIOD
HCSL OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
9DB202CG
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REV. A OCTOBER 6, 2004
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ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS9DB202 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL.VDD andVDDA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin.To achieve optimum jitter
performance, power supply isolation is required. Figure 1 illus-
trates how a 24Ω resistor along with a 10µF and a .01µF by-
pass capacitor should be connected to eachVDDA pin.
3.3V
VDD
.01µF
24Ω
VDDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
9DB202CG
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REV. A OCTOBER 6, 2004
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ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
9DB202CG
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REV. A OCTOBER 6, 2004
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ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
RELIABILITY INFORMATION
TABLE 6A. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP PACKAGE
θJA byVelocity (Linear Feet per Minute)
0
200
98°C/W
66.6°C/W
500
88°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 6B. θJAVS. AIR FLOW TABLE FOR 20 LEAD SSOP PACKAGE
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
80.8°C/W
73.2°C/W
69.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS9DB202 is: 2471
9DB202CG
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REV. A OCTOBER 6, 2004
9
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
PACKAGE OUTLINE - F SUFFIX FOR 20 LEAD SSOP
TABLE 6A. PACKAGE DIMENSIONS
TABLE 6B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
Minimum
Maximum
N
A
20
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
--
2.0
--
A1
A2
b
0.05
0.80
0.19
0.09
6.40
A1
A2
b
0.05
1.65
0.22
0.09
6.90
7.40
5.0
1.85
0.38
0.25
7.50
8.20
5.60
c
c
D
D
E
6.40 BASIC
0.65 BASIC
E
E1
e
4.30
4.50
E1
e
0.65 BASIC
L
0.45
0°
0.75
8°
L
0.55
0°
0.95
8°
α
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
Reference Document: JEDEC Publication 95, MO-150
9DB202CG
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REV. A OCTOBER 6, 2004
10
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS
™
JITTER
ATTENUATOR
TABLE 7. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
72 per Tube
2500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS9DB202CG
ICS9DB202CGT
ICS9DB202CGLF
ICS9DB202CG
ICS9DB202CG
ICS9DB202CGL
20 Lead TSSOP
20 Lead TSSOP on Tape and Reel
20 Lead "Lead-Free" TSSOP
72 per Tube
20 Lead "Lead-Free" TSSOP on
Tape and Reel
ICS9DB202CGLFT
ICS9DB202CGL
2500
0°C to 70°C
ICS9DB202CF
ICS9DB202CFT
ICS9DB202CFLF
ICS9DB202CF
ICS9DB202CF
ICS9DB202CFLF
20 Lead SSOP
64 per Tube
1000
0°C to 70°C
0°C to 70°C
0°C to 70°C
20 Lead SSOP on Tape and Reel
20 Lead "Lead-Free" SSOP
64 per Tube
20 Lead "Lead-Free" SSOP on
Tape and Reel
ICS9DB202CFLFT
ICS9DB202CFLF
1000
0°C to 70°C
The aforementioned trademarks, HiPerClockS™ and PCI Express™ iare trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV. A OCTOBER 6, 2004
11
相关型号：
ICS9DB202CGLFT
Two 0.7V current mode differential HCSL output pairs, 1 differential clock input
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