ICS9FG108 [ICSI]
Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks; 差分P4 CPU ， PCI - Express的＆ SATA时钟可编程FTG
| 型号： | ICS9FG108 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks |
| 文件： | 总13页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Recommended Application:
Pin Configuration
Frequency Timing Generator for Differential CPU, PCI-Express
& SATA clocks
XIN/CLKIN
X2
1
2
3
4
5
6
7
8
9
48 VDDA
47 GNDA
46 IREF
45 FS0
44 FS1
43 OE_0**
42 DIF_0
41 DIF_0#
40 VDD
39 DIF_1
38 DIF_1#
37 OE_1*
36 VDD
VDD
GND
Features:
•
Generates common frequencies from 14.318 MHz or 25
MHz
REFOUT
FS2
OE_7**
DIF_7
DIF_7#
VDD 10
DIF_6 11
DIF_6# 12
OE_6* 13
VDD 14
•
•
•
•
Crystal or reference input
8 - 0.7V current-mode differential output pairs
Supports Serial-ATA at 100 MHz
Two spread spectrum modes: 0 to -0.5 downspread and
+/-0.25% centerspread
•
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
35 GND
GND 15
34 OE_2*
33 DIF_2
32 DIF_2#
31 VDD
30 DIF_3
29 DIF_3#
28 OE_3**
27 SEL14M_25M#
26 SPREAD
25 DIF_STOP#
Key Specifications:
OE_5* 16
DIF_5 17
DIF_5# 18
VDD 19
DIF_4 20
DIF_4# 21
OE_4** 22
SDATA 23
SCLK 24
•
•
•
Output cycle-to-cycle jitter < 85 ps
Output to output skew < 85 ps
+/-300 ppm frequency accuracy on output clocks
Frequency Select Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00
125.00
133.33
166.67
200.00
266.66
333.33
400.00
100.00
125.00
133.33
166.67
200.00
266.66
333.33
400.00
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by an '*' have 120 Kohm pull UP resistors
48-pin SSOP & TSSOP
0823—04/02/04
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
Third party brands and names are the property of their respective owners
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
Pin Description
PIN #
PIN NAME
XIN/CLKIN
PIN TYPE
DESCRIPTION
1
2
3
4
5
6
IN
OUT
PWR
PWR
IN
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
X2
VDD
GND
REFOUT
FS2
Ground pin.
Reference Clock output
Frequency select pin.
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Power supply, nominal 3.3V
7
OE_7**
IN
8
9
DIF_7
DIF_7#
OUT
OUT
PWR
OUT
OUT
10 VDD
11 DIF_6
12 DIF_6#
13 OE_6*
IN
14 VDD
15 GND
PWR
PWR
Ground pin.
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
16 OE_5*
IN
17 DIF_5
18 DIF_5#
19 VDD
20 DIF_4
21 DIF_4#
OUT
OUT
PWR
OUT
OUT
22 OE_4**
IN
23 SDATA
24 SCLK
I/O
IN
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
0823—04/02/04
2
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
25 DIF_STOP#
IN
IN
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum
functionality.
26 SPREAD
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818
MHz, 0 = 25 MHz
27 SEL14M_25M#
28 OE_3**
IN
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Ground pin.
29 DIF_3#
30 DIF_3
31 VDD
32 DIF_2#
33 DIF_2
OUT
OUT
PWR
OUT
OUT
34 OE_2*
IN
35 GND
36 VDD
PWR
PWR
Power supply, nominal 3.3V
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Frequency select pin.
37 OE_1*
IN
38 DIF_1#
39 DIF_1
40 VDD
41 DIF_0#
42 DIF_0
OUT
OUT
PWR
OUT
OUT
43 OE_0**
IN
44 FS1
45 FS0
IN
IN
Frequency select pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied
to ground in order to establish the appropriate current. 475 ohms is
the standard value.
46 IREF
OUT
47 GNDA
48 VDDA
PWR
PWR
Ground pin for the PLL core.
3.3V power for the PLL core.
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
0823—04/02/04
3
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
General Description
ICS9FG108 is a Frequency Timing Generator that provides 8 differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express, next generation I/O, and SATA. The part synthesizes several output
frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock
instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 85 ps and output-to-output skew of less than 85 ps.
ICS9FG108 also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or SMBus
control.
Block Diagram
XIN/CLKIN
X2
OE(7:0)
REFOUT
OSC
4
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
DIF(7:0)
SPREAD
SEL14M_25M#
CONTROL
LOGIC
DIF_STOP#
FS(2:0)
SDATA
SCLK
IREF
Power Groups
Pin Number
VDD
3
GND
4
15,35
47
Description
REFOUT, Digital Inputs, SMBus
DIF Outputs
10,14,19,31,36,40
N/A
48
IREF
47
Analog VDD & GND for PLL Core
0823—04/02/04
4
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
VDD + 0.5V
VDD + 0.5V
V
V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
-65
0
150
70
115
°C
°C
°C
Input ESD protection
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
Input Low Voltage
Input High Current
VIH
VIL
IIH
3.3 V +/-5%
3.3 V +/-5%
2
VSS - 0.3
-5
VDD + 0.3
V
V
0.8
5
VIN = VDD
uA
VIN = 0 V; Inputs with no pull-
up resistors
IIL1
-5
uA
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
uA
Full Active, CL = Full load;
f = 400 MHz
Full Active, CL = Full load;
250
200
mA
mA
Operating Supply Current IDD3.3OP
f = 100 MHz
VDD = 3.3 V
Input Frequency3
Fi
14
25
7
MHz
nH
3
1
1
1
Pin Inductance1
Lpin
Input/Output
Capacitance1
CIN
Logic Inputs
1.5
5
pF
COUT
Output pin capacitance
6
pF
From VDD Power-Up and after
input clock stabilization to 1st
clock
Clk Stabilization1,2
TSTAB
1.8
ms
1,2
Modulation Frequency
DIF output enable
fMOD
Triangular Modulation
DIF output enable after
DIF_Stop# de-assertion
30
40
10
kHz
ns
1
1
tDIFOE
Input Rise and Fall times
tR/tF
20% to 80% of VDD
5
ns
1
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet
ppm frequency accuracy on PLL outputs.
0823—04/02/04
5
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Zo1
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
3000
Ω
1
1
1
Statistical measurement on
single ended signal using
oscilloscope math function.
Voltage High
Voltage Low
VHigh
VLow
660
mV
-150
150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Measurement on single ended
signal using absolute value.
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
see Tperiod min-max values
400MHz nominal
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
1
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Absolute min period
Tabsmin
Rise Time
Fall Time
tr
700
700
125
125
tf
VOH = 0.525V VOL = 0.175V
175
ps
ps
ps
1
1
1
Rise Time Variation
Fall Time Variation
d-tr
d-tf
Measurement from differential
wavefrom
Duty Cycle
Skew
dt3
tsk3
45
55
50
50
%
ps
ps
1
1
1
VT = 50%
Measurement from differential
wavefrom
Jitter, Cycle to cycle
tjcyc-cyc
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at
14.31818MHz or 25 MHz
3 Figures are for down spread.
0823—04/02/04
6
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
Electrical Characteristics - REF-14.318/25 MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
SYMBO
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS Notes
L
Long Accuracy
Clock period
ppm
Tperiod
see Tperiod min-max values
14.318MHz output nominal
25.000MHz output nominal
IOH = -1 mA
-300
0
300
ppm
1
1,2
1,2
1
69.8270 69.8413 69.8550 ns
39.9880 40.0000 40.0120 ns
Clock period
Tperiod
VOH
Output High Voltage
Output Low Voltage
2.4
V
V
VOL
IOL = 1 mA
0.4
-23
1
VOH @MIN = 1.0 V,
Output High Current
Output Low Current
IOH
IOL
-29
29
mA
mA
1
1
V
OH@MAX = 3.135 V
VOL @MIN = 1.95 V,
OL @MAX = 0.4 V
27
V
Rise Time
Fall Time
Duty Cycle
Jitter
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
1.6
1.6
2
2
ns
ns
%
1
1
1
1
dt1
45
55
200
tjcyc-cyc
VT = 1.5 V
150
ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818 or 25.00 MHz
0823—04/02/04
7
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
I2C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Control
Byte 0
Pin #
Name
Type
0
1
PWD
Function
FS31
FS21
FS11
FS01
27
5
RW
RW
RW
RW
RW
Pin 27
Pin 5
Pin 44
Pin 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
See Frequency
Selection Table, Page 1
44
7
26
Spread Enable1
Enable Software Control of
Frequency, Spread Enable
(Spread Type always Software
Control)
Off
On
Pin 26
Hardware
Select
Software
Select
-
RW
0
Bit 2
-
-
DIF_STOP# drive mode
SPREAD TYPE
RW
RW
Driven
Down
Hi-Z
Center
0
0
Bit 1
Bit 0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
I2C Table: Output Enable Register
Control
Byte 1
Pin #
Name
Type
0
1
PWD
Function
-
-
-
-
-
-
-
-
DIF_7
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0823—04/02/04
8
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
I2C Table: Output Stop Mode Register
Control
Function
Byte 2
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
DIF_7
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Frequency Select Readback Register
Control
Function
Byte 3
Pin #
Name
Type
0
1
PWD
SEL14M_25M#1
(FS3)
27
State of pin 27
R
Pin 27
Bit 7
See Frequency
Selection Table, Page 1
FS21
FS11
6
State of pin 6
State of pin 44
State of pin 45
State of pin 26
R
R
R
R
R
R
R
Pin 6
Pin 44
Pin 45
Pin 26
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
44
45
26
FS01
SPREAD1
Off
On
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
X
X
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
0823—04/02/04
9
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
I2C Table: Vendor & Revision ID Register
Control
Function
Byte 4
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
I2C Table: DEVICE ID
Byte 5
Control
Function
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
R
R
R
R
R
R
R
R
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
1
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device ID = 08 hex
I2C Table: Byte Count Register
Byte 6 Pin #
Control
Name
Type
0
1
PWD
Function
Writing to this
register will
configure how
many bytes
will be read
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
back, default
is 07 = 7
bytes.
0823—04/02/04
10
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the I2C
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the I2C DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP#
DIF
DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 10nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_Stop#
DIF
DIF#
DIF Internal
Tdrive_DIF_Stop, 10nS >200mV
0823—04/02/04
11
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
h x 45°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
- C -
VARIATIONS
D mm.
D (inch)
e
SEEAATTIINNGG
PLANE
N
b
MIN
15.75
MAX
16.00
MIN
.620
MAX
.10 (.004)
C
48
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS9FG108yFLF-T
Example:
ICS XXXX y F - LF T
Designation for tape and reel packaging
Lead Free (if required)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0823—04/02/04
12
Integrated
Circuit
Systems, Inc.
ICS9FG108
Advance Information
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
INDEX
AREA
c
1
2
D
E
E1
e
L
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
6.00
6.20
.236
.244
0.020 BASIC
.030
SEE VARIATIONS
D
0.50 BASIC
0.45
0.75
.018
N
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
48
b
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS9FG108yGLF-T
Example:
ICS XXXX y G - LF T
Designation for tape and reel packaging
Lead Free (if required)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0823—04/02/04
13
相关型号：
ICS9FG108CFLF
Processor Specific Clock Generator, 400MHz, PDSO48, 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48
IDT
ICS9FG108CFLF-T
400MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48
IDT
ICS9FG108CG-T
Processor Specific Clock Generator, 400MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
IDT
ICS9FG108CGLF
Processor Specific Clock Generator, 400MHz, PDSO48, 6.10 MM WIDTH, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
IDT
ICS9FG108CGLF-T
400MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
IDT
ICS9FG108CGLFT
Processor Specific Clock Generator, 400MHz, PDSO48, 6.10 MM WIDTH, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
IDT
©2020 ICPDF网 联系我们和版权申明