ICSSSTV32852 [ICSI]
DDR 24-Bit to 48-Bit Registered Buffer; DDR 24位至48位寄存缓冲器
| 型号： | ICSSSTV32852 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DDR 24-Bit to 48-Bit Registered Buffer |
| 文件： | 总7页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICSSSTV32852
Integrated
Circuit
Systems,Inc.
DDR 24-Bit to 48-Bit Registered Buffer
Recommended Application:
•
DDR Memory Modules
Pin Configuration
•
Provides complete DDR DIMM logic solution with
ICS93V857 or ICS95V857
1
2
3
4
5
6
A
B
C
D
E
F
•
SSTL_2 compatible data registers
Product Features:
•
•
Differential clock signals
Supports SSTL_2 class II specifications on inputs
and outputs
•
•
Low-voltage operation
- VDD = 2.3V to 2.7V
Available in 114 ball BGA package.
G
H
J
Truth Table1
K
L
Inputs
CLK
X or
Q Outputs
Q
M
N
P
R
T
RESET#
CLK#
D
X or
X or
L
L
Floating Floating Floating
U
V
W
H
H
H
↑
↑
↓
↓
H
L
H
L
Q0(2)
L or H
L or H
X
Notes:
114-Pin Ball BGA
Pin Configuration Assignments
1.
H = "High" Signal Level
L = "Low" Signal Level
↑ = Transition "Low"-to-"High"
↓ = Transition "High"-to-"Low"
X = Don't Care
1
2
3
4
5
6
Q2A
Q3A
Q5A
Q1A
VDDQ
Q4A
Q6A
GND
Q9A
Q11A
CLK
CLK#
GND
Q1B
VDDQ
Q4B
Q6B
GND
Q9B
Q11B
Q2B
Q3B
Q5B
Q7B
Q8B
Q10B
Q12B
A
B
C
D
E
F
GND
VDDQ
GND
VDDQ
VDDQ
GND
VDDQ
GND
2.
Output level before the indicated
steady state input conditions were
established.
Q7A
Q8A
Q10A
VDDQ
VDDQ
GND
Block Diagram
G
Q12A
Q13A
Q14A
Q17A
Q18A
Q20A
Q22A
Q23A
Q24A
D2
H
J
VDD
Q15A
Q16A
Q19A
VDDQ
Q21A
VDDQ
VDD
D1
VDDQ
GND
VDDQ
GND
GND
VDDQ
GND
RESET#
D6
VDDQ
GND
VDDQ
GND
GND
VDDQ
GND
VREF
D18
VDD
Q15B
Q16B
Q19B
VDDQ
Q21B
VDDQ
VDD
Q13B
Q14B
Q17B
Q18B
Q20B
Q22B
Q23B
Q24B
D14
CLK
CLK#
K
L
RESET#
R
Q1A
M
CLK
N
Q1B
D1
VREF
D1
P
R
T
D13
U
V
D4
D3
D10
D22
D15
D16
D5
D7
D11
D23
D19
D17
To 23 Other Channels
W
D8
D9
D12
D24
D21
D20
0513F—05/13/03
ICSSSTV32852
General Description
The 24-bit-to-48-bit ICSSSTV32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/
O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV32852 supports low-power
standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the
logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET#
must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-
up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic “Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals.When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable
the differential input receivers.This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
R1,P1, N1, N2, M1, L2, L1, K1,
K2, J2, J1, H1, G1, G2, F1, F2,
E1, D1, D2, C1, C2, B1, A1,
A2
Q (24:1)A
OUTPUT
Data output
R6, P6, N6, N5, M6, L5, L6,
K6, K5, J5, J6, H6, G6, G5,
F6, F5, E6, D6, D5, C6, C5,
B6, A6, A5
Q (24:1)B
OUTPUT
Data output
Ground
E2, B3, D3, G3, J3, L3, M3,
P3, B4, D4, G4, J4, L4, M4,
P4, E5
GND
PWR
PWR
B2, M2, P2, C3, E3, F3, H3,
K3, N3, C4, E4, F4, H4, K4,
N4, B5, M5, P5
VDDQ
Output supply voltage, 2.5V nominal
Data input
W4, V4, U4, W5, W6, V5, T4,
V6, U6, U5, T6, T5, W3, V3,
U3, W2, W1, V2, T3, V1, U1,
U2, T1, T2
D (24:1)
INPUT
A3
CLK
CLK#
INPUT
INPUT
PWR
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
A4
H2, H5, R2, R5
VDD
R3
R4
RESET#
VREF
INPUT
INPUT
Input reference voltage, 1.25V nominal
0513F—05/13/03
2
ICSSSTV32852
Absolute Maximum Ratings
Notes:
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VDDQ +0.5
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50mA
Continuous Output Current. . . . . . . . . . . . . . . ±50mA
VDD, VDDQ or GND Current/Pin . . . . . . . . . . ±100mA
1. The input and output negative voltage
ratings may be excluded if the input
andoutputclampratingsareobserved.
2. This current will flow only when the
output is in the high state level
V0 >VDDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Package Thermal Impedance3 . . . . . . . . . . . . . . . 55°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Recommended Operating Conditions
DESCRIPTION
PARAMETER
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
Supply Voltage
VDD
I/O Supply Voltage
VDDQ
VREF
2.3
2.5
2.7
Reference Voltage
1.15
1.25
VREF
1.35
Termination Voltage
Input Voltage
VTT
VREF - 0.04
0
VREF + 0.04
VDDQ
VI
VIH (DC)
VIH (AC)
VIL (DC)
VIL (DC)
VIH
DC Input High Voltage
AC Input High Voltage
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
Input Low Voltage Level
Common mode Input Range
Differential Input Voltage
VREF + 0.15
VREF + 0.31
Data Inputs
V
VREF - 0.15
VREF - 0.31
1.7
RESET#
VIL
0.7
VICR
0.97
0.36
1.53
CLK, CLK#
VID
Cross Point Voltage of Differential Clock
Pair
VIX
(VDDQ/2) - 0.2
(VDDQ/2) + 0.2
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
IOH
IOL
TA
19
19
70
mA
°C
0
1Guarenteed by design, not 100% tested in production.
0513F—05/13/03
3
ICSSSTV32852
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
CONDITIONS
SYMBOL
VIK
PARAMETERS
VDDQ
2.3V
MIN
TYP MAX
-1.2
UNITS
V
II = -18mA
IOH = -100µA
2.3V - 2.7V VDDQ - 0.2
VOH
IOH = -16mA
2.3V
2.3V - 2.7V
2.3V
2.05
IOL = 100µA
0.2
0.20
±5
VOL
II
IOL = 16mA
All Inputs
VI = VDD or GND
RESET# = GND
VI = VIH(AC) or VIL(AC)
RESET# = VDD
2.7V
µA
µA
Standby (Static)
0.01
IDD
,
Operating (Static)
40
35
mA
RESET# = VDD
,
Dynamic operating
(clock only)
µA/clock
MHz
VI = VIH(AC) or VIL(AC)
,
CLK and CLK# switching
50% duty cycle.
IO = 0
2.5V
RESET# = VDD
,
IDDD
VI = VIH(AC) or VIL (AC)
,
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
Dynamic Operating
(per each data input)
µA/ clock
MHz/data
7
rOH
rOL
Output High
I
OH = -20mA
2.3V - 2.7V
2.3V - 2.7V
12
10
Ω
Ω
Output Low
IOL = 20mA
[rOH - rOL] each
separate bit
Data Inputs
rO(D)
IO = 20mA, TA = 25°C
VI = VREF ±350mV
2.5V
2.5V
4
Ω
2.5
2.5
3.5
3.5
C
i
pF
CLK and CLK#
VICR = 1.25V, VI(PP) = 360mV
Notes:
1. Guaranteed by design, not 100% tested in production.
0513F—05/13/03
4
ICSSSTV32852
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
VDD = 2.5V ±0.2V
SYMBOL
PARAMETERS
UNITS
MIN
MAX
200
2.7
4.5
4
fclock
tPD
tRST
tSL
Clock frequency
MHz
ns
Clock to output time
Reset to output time
Output slew rate
1.9
ns
1
V/ns
ns
Setup time, fast slew rate 2, 4
0.50
tS
Data before CLK↑, CLK#↓
Setup time, slow slew rate 3, 4
0.70
ns
Hold time, fast slew rate 2, 4
Hold time, slow slew rate 3, 4
0.30
0.50
ns
ns
↑ ↓
Data after CLK , CLK#
Th
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
Notes:
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
From
(Input)
To
(Output)
VDD = 2.5V ±0.2V
SYMBOL
UNITS
MIN
200
1.9
TYP
MAX
fmax
tPD
MHz
ns
CLK, CLK#
RESET#
Q
Q
2.7
4.5
tphl
ns
0513F—05/13/03
5
ICSSSTV32852
VTT
RL 50Ω
=
From Output
Under Test
Test Point
CL = 30 pF
(see Note 1)
Load Circuit
LVCMOS
RESET#
Input
VDD
0 V
VDD/2
VDD/2
VI(pp)
Timing
Input
VICR
VICR
tinact
tact
IDDH
tPHL
tPHL
IDD
90%
(see note 2)
10%
VOH
IDDL
VTT
VTT
Voltage and Current Waveforms
Inputs Active and Inactive Times
VOL
Output
Voltage Waveforms - Propagation Delay Times
tw
VIH
VIL
Input
VREF
VREF
Voltage Waveforms - Pulse Duration
LVCMOS
RESET#
Input
VIH
VIL
VI(pp)
V
DD/2
Timing
Input
VICR
tPHL
VOH
VOL
Output
th
tSU
VTT
Voltage Waveforms - Propagation Delay Times
VIH
VIL
VREF
Input
VREF
Voltage Waveforms - Setup and Hold Times
Parameter Measurement Information (VDD = 2.5V ±±.2Vꢀ
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF -310mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tpd
0513F—05/13/03
6
ICSSSTV32852
----- BALL GRID -----
REF. DIMENSIONS
D
E
T Min/Max
e
HORIZ VERT TOTAL
d
h Min/Max
0.31/0.41
b
c
16.00 Bsc 5.50 Bsc 1.30/1.50 0.80 Bsc
6
19
114
0.46
0.80
0.75
ALL DIMENSIONS IN MILLIMETERS
10-0055
Ordering Information
ICSSSTV32852yHT
Example:
ICS XXXX y H - T
Designation for tape and reel packaging
Package Type
H = BGA
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0513F—05/13/03
7
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