IS61LV5128-12K [ICSI]
512K x 8 HIGH-SPEED CMOS STATIC RAM; 512K ×8高速CMOS静态RAM
| 型号： | IS61LV5128-12K |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 512K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LV5128
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
DESCRIPTION
The ICSI IS61LV5128 is a very high-speed, low power,
524,288-word by 8-bit COMS static RAM. The IS61LV5128 is
fabricated using ICSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields higher preformance and low power
consumotion devices.
High-speed access times:
8, 10, 12 and 15 ns
High-preformance, lower-power CMOS process
Multiple center power and ground pins for
greater noise immunity
Easy memory expansion with CE and OE
options
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 µW (typical) with CMOS input levels.
CE power-down
Fully static operation: no clock or refresh
reguired
The IS61LV5128 operates from a single 3.3V power supply
and all inputs are TTL-compatible.
TTL compatible inputs and outputs
Single 3.3V + 10% power supply
Packages available:
The IS61LV5128 is available in 36-pin, 400mil SOJ and 44-pin
TSOP-2 package.
36-pin 400mil SOJ
44-pin TSOP-2
FUNCTIONAL BLOCK DIAGRAM
512K X 8
MEMORY ARRAY
A0-A18
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.
Integrated Circuit Solution, Inc.
SR027-0C
1
IS61LV5128
PIN CONFIGURATION
36-Pin SOJ
PIN CONFIGURATION
44-Pin TSOP-2
A0
A1
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
NC
NC
A0
A1
A2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
2
A18
A17
A16
A15
OE
2
3
A2
3
4
A18
A17
A16
A15
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
A3
4
5
A4
5
A3
A4
6
CE
6
7
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
8
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A5
7
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
9
8
10
11
12
13
14
15
16
17
18
19
20
21
22
9
10
11
12
13
14
15
16
17
18
A6
A7
NC
NC
NC
NC
A8
A9
TRUTH TABLE
PIN DESCRIPTIONS
Mode
WE
CE
OE
I/O Operation Vcc Current
A0-A18
CE
Address Inputs
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
OE
Output Disabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
WE
I/O0-I/O7
Vcc
Write
X
Power
GND
NC
Ground
No Connection
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VTERM
TBIAS
TSTG
PD
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
0.5 to Vcc + 0.5 V
55 to +125
65 to +150
1.0
°C
°C
W
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
Integrated Circuit Solution, Inc.
SR027-0C
IS61LV5128
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
3.3V + 10%
3.3V + 10%
40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = 4.0 mA
VCC = Min., IOL = 8.0 mA
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
V
2.0
VCC + 0.3
0.8
V
0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
1
5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
Com.
Ind.
1
5
1
5
µA
Notes:
1. VIL = 3.0V for pulse width less than 10 ns.
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
-10 ns
Min. Max.
-12 ns
-15 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max. Unit
ICC
Vcc Dynamic Operating
VCC = Max.,
Com.
Ind.
300
310
280
290
260
270
240
250
mA
Supply Current
IOUT = 0 mA, f = fMAX
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
Ind.
55
65
55
65
55
65
55
65
mA
VIN = VIH or VIL
CE
≥
VIH , f = 0
ISB2
CMOS Standby
VCC = Max.,
Com.
Ind.
10
15
10
15
10
15
10
15
mA
Current (CMOS Inputs)
CE
VIN
VIN
≥
≥
≤
VCC 0.2V,
VCC 0.2V, or
0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Output Capacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Circuit Solution, Inc.
SR027-0C
3
IS61LV5128
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
-10
Min.
-12
Min.
-15
Min.
Symbol Parameter
Min.
8
Max.
8
Max.
10
10
5
Max.
12
12
6
Max.
15
15
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
10
3
12
3
15
3
tAA
Address Access Time
Output Hold Time
CE Access Time
3
tOHA
tACE
tDOE
tHZOE
8
0
0
0
0
OE Access Time
4
(2)
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
4
5
6
6
(2)
tLZOE
0
4
5
6
0
6
(2
tHZCE
0
0
0
0
(2)
tLZCE
3
3
3
3
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
1.5V
Output Load
See Figures 1 and 2
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
353 Ω
30 pF
5 pF
Including
jig and
scope
Including
jig and
scope
Figure 1.
Figure 2.
4
Integrated Circuit Solution, Inc.
SR027-0C
IS61LV5128
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Circuit Solution, Inc.
SR027-0C
5
IS61LV5128
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
-10
Min.
-12
Min.
-15
Min.
Symbol Parameter
Min.
Max.
Max.
Max.
Max.
Unit
ns
tWC
tSCE
tAW
Write Cycle Time
8
7
7
10
8
12
9
15
10
10
CE to Write End
ns
Address Setup Time
to Write End
8
9
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
4
0
0
5
0
0
6
0
0
7
ns
ns
ns
ns
ns
ns
ns
tSA
tPWE
tSD
WE Pulse Width
7
8
9
10
7
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
4.5
0
5
6
tHD
0
0
0
(2)
tHZWE
3
3
3
3
(2)
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (1,2 )(CE Controlled, OE is HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
6
Integrated Circuit Solution, Inc.
SR027-0C
IS61LV5128
WRITE CYCLE NO. 2 (1,2) (WE Controlled, OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
Integrated Circuit Solution, Inc.
SR027-0C
7
IS61LV5128
ORDERING INFORMATION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: 40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
8
IS61LV5128-8T
IS61LV5128-8K
400mil TSOP-2
400mil SOJ
8
IS61LV5128-8TI
IS61LV5128-8KI
400mil TSOP-2
400mil SOJ
10
12
15
IS61LV5128-10T
IS61LV5128-10K
400mil TSOP-2
400mil SOJ
10
12
15
IS61LV5128-10TI
IS61LV5128-10KI
400mil TSOP-2
400mil SOJ
IS61LV5128-12T
IS61LV5128-12K
400mil TSOP-2
400mil SOJ
IS61LV5128-12TI
IS61LV5128-12KI
400mil TSOP-2
400mil SOJ
IS61LV5128-15T
IS61LV5128-15K
400mil TSOP-2
400mil SOJ
IS61LV5128-15TI
IS61LV5128-15KI
400mil TSOP-2
400mil SOJ
Integrated Circuit Solution, Inc.
HEADQUARTER:
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HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
8
Integrated Circuit Solution, Inc.
SR027-0C
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