IS61LV6432-133PQ [ICSI]
64K x 32 SYNCHRONOUS PIPELINE STATIC RAM; 64K ×32的同步管道静态RAM
| 型号： | IS61LV6432-133PQ |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| 文件： | 总16页 (文件大小：488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LV6432
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
FEATURES
DESCRIPTION
The ICSI IS61LV6432 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 65,536 words
by 32 bits, fabricated with ICSI's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin LQFP and PQFP package
• 3.3V VCC and 2.5V VCCQ for 2.5 I/O's
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
• Industrial temperature available
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned
by BWE being LOW. A LOW on GW input would cause all bytes
to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61LV6432 and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
FAST ACCESS TIME
Symbol
tKQ
Parameter
CLK Access Time
-166
5
-133
5
-117
5
-5
5
-6
6
-7
7
-8
8
Unit
ns
tKC
Cycle Time
6
7.5
133
8.5
117
10
100
12
83
13
75
15
66
ns
—
Frequency
166
MHz
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
1
SSR005-0B
IS61LV6432
BLOCK DIAGRAM
MODE
A0
A0’
A1’
Q0
CLK
CLK
BINARY
COUNTER
Q1
ADV
CE
A1
64K x 32
MEMORY
ARRAY
ADSC
ADSP
CLR
16
14
16
D
Q
A15-A0
ADDRESS
REGISTER
CE
CLK
32
32
D
Q
GW
BWE
DQ32-DQ25
BW4
BYTE WRITE
REGISTERS
CLK
D
Q
DQ24-DQ17
BYTE WRITE
REGISTERS
BW3
CLK
D
Q
DQ16-DQ9
BYTE WRITE
REGISTERS
BW2
BW1
CLK
D
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
CLK
CE1
CE2
CE3
4
32
INPUT
REGISTERS
OUTPUT
REGISTERS
D
Q
DATA[32:1]
ENABLE
OE
REGISTER
CLK
CLK
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Circuit Solution Inc.
SSR005-0B
IS61LV6432
PIN CONFIGURATION
100-Pin LQFP and PQFP (Top View)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
VCCQ
VCC
DQ16
DQ15
VCCQ
GNDQ
DQ14
DQ13
DQ12
DQ11
GNDQ
VCCQ
DQ10
DQ9
GND
NC
VCC
ZZ
DQ8
NC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
NC
DQ7
VCCQ
GNDQ
DQ6
DQ5
DQ4
DQ3
GNDQ
VCCQ
DQ2
DQ1
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PIN DESCRIPTIONS
A0-A15
Address Inputs
DQ1-DQ32
ZZ
Data Input/Output
Sleep Mode
CLK
Clock
ADSP
ADSC
ADV
Processor Address Status
Controller Address Status
Burst Address Advance
Synchronous Byte Write Enable
Byte Write Enable
MODE
VCC
Burst Sequence Mode
+3.3V Power Supply
Ground
GND
BW1-BW4
BWE
VCCQ
Isolated Output Buffer Supply:
+3.3V
GNDQ
NC
Isolated Output Buffer Ground
No Connect
GW
Global Write Enable
Synchronous Chip Enable
Output Enable
CE1, CE2, CE3
OE
Integrated Circuit Solution Inc.
3
SSR005-0B
IS61LV6432
TRUTH TABLE
Operation
Address
Used
CE1
CE2
CE3 ADSP ADSC ADV WRITE OE
DQ
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
None
None
None
None
None
External
External
External
External
External
Next
H
L
L
L
L
L
L
L
L
X
L
X
L
X
X
H
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
H
H
X
H
X
X
H
H
X
H
Next
Next
Next
Next
L
L
L
L
Next
L
L
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Read Cycle, Suspend Burst Current
Write Cycle, Suspend Burst Current
Write Cycle, Suspend Burst Current
Notes:
H
H
H
H
H
H
H
H
H
H
L
L
D
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is
LOW. WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held
HIGH throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
Function
GW
BWE BW1 BW2 BW3 BW4
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
H
H
H
X
L
H
X
L
L
X
X
H
L
L
X
X
H
H
L
X
H
H
L
X
H
H
L
X
X
X
4
Integrated Circuit Solution Inc.
SSR005-0B
IS61LV6432
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
A1 A0
A1 A0
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
A1’, A0’ = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–10 to +85
–55 to +150
1.8
Unit
°C
°C
W
TBIAS
TSTG
PD
Temperature Under Bias
Storage Temperature
Power Dissipation
IOUT
Output Current (per I/O)
100
mA
V
V
VIN, VOUT Voltage Relative to GND for I/O Pins
VIN
–0.5 to VCCQ + 0.3
–0.5 to 4.6
Voltage Relative to GND for
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static
voltages or electric fields; however, precautions may be taken to avoid application of any
voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Circuit Solution Inc.
5
SSR005-0B
IS61LV6432
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
VCC
VCCQ
0°C to +70°C
3.3V +10%, –5%
3.3V +10%, –5%
2.375V min., 3.465 max.
2.375V min, 3.465V max.
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
IOH = –1.0 mA
IOL = 1.0 mA
Min.
2.0
Max.
—
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
—
0.4
V
1.7
VCCQ + 0.3
0.7
V
–0.3
V
(2)
GND ≤ VIN ≤ VCCQ
Com.
Ind.
–5
–10
5
10
µA
ILO
Output Leakage Current
GND ≤ VOUT ≤ VCCQ, OE = VIH
Com.
Ind.
–5
–10
5
10
µA
POWER SUPPLY CHARACTERISTICS (Operating Range)
-166
-133
-117
-5
-6
-7
-8
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max. Unit
I
CC
AC Operating
Supply Current
Device Selected,
Com.
—
—
215
—
—
—
205
—
—
—
195
205
—
—
175
185
—
—
165
175
—
—
150
160
—
—
140 mA
150
All Inputs = VIL or VIH Ind.
OE = VIH
,
Cycle Time
≥
tKC min.
I
I
SB
ZZ
Standby Current
Device Deselected, Com.
—
—
70
—
—
—
60
—
—
—
50
60
—
—
25
35
—
—
25
35
—
—
25
35
—
—
25
35
mA
mA
V
CC = Max.,
Ind.
CLK Cycle Time
≥
t
KC min.
Power-Down Mode ZZ = VCCQ
,
Com.
Ind.
—
—
5
—
—
—
5
—
—
—
5
10
—
—
5
10
—
—
5
10
—
—
5
10
—
—
5
10
CLK Running
Current
All Inputs ≤ GND + 0.2V
or
≥
V
CC – 0.2V
Note:
1. MODE pin have an internal pullup. ZZ pin has an internal pull-down. These pins may be a No Connect, tied to GND, or tied to
VCCQ.
2. MODE pin should be tied to Vcc or GND. They exhibit ±30 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ Vcc –
0.2V.
6
Integrated Circuit Solution Inc.
SSR005-0B
IS61LV6432
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Input Capacitance
Conditions
VIN = 0V
Max.
6
Unit
pF
COUT
Input/Output Capacitance
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level for Input Pins
Input Pulse Level for I/O Pins
Input Rise and Fall Times
0V to 3.0V
0V to 2.5V
1.5 ns
Input and Output Timing
and Reference Level
1.25V
Output Load
See Figures 1 and 2
AC TEST LOADS
317 Ω
2.5V
ZO = 50Ω
OUTPUT
Output
Buffer
50Ω
30 pF
351 Ω
5 pF
Including
jig and
scope
1.25V
Figure 1
Figure 2
Integrated Circuit Solution Inc.
7
SSR005-0B
IS61LV6432
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
-133
-117
-5
-6
-7
-8
Symbol Parameter
Min. Max.
Min. Max.
Min. Max
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
KC
KH
KL
Cycle Time
6
—
—
—
5
7.5
2.8
2.8
—
—
—
—
5
8.5
3.0
3.0
—
—
—
—
5
10
3.5
3.5
—
—
—
—
5
12
—
—
—
6
13
—
—
—
7
15
—
—
—
8
Clock High Time
2.4
2.4
—
4
6
6
Clock Low Time
4
6
6
KQ
KQX
Clock Access Time
—
—
2
—
2
(2)
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
1.5
0
—
—
5
1.5
0
—
—
5
1.5
0
—
—
6
1.5
0
—
—
6
1.5
0
—
—
6
—
—
6
—
—
6
(2,3)
KQLZ
0
0
(2,3)
KQHZ
OEQ
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
2
2
5
5
5
5
6
—
0
6
—
0
6
(2)
OEQX
0
—
—
3
0
—
—
3
0
—
—
4
0
—
—
4
0
—
—
5
—
—
6
—
—
6
(2,3)
OELZ
0
0
0
0
0
0
0
(2,3)
OEHZ
AS
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
66.7
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
80
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
25
—
—
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
30
—
—
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
35
—
—
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
35
—
—
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SS
Address Status Setup Time
Write Setup Time
WS
CES
AVS
AH
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
SH
Address Status Hold Time
Write Hold Time
WH
CEH
AVH
CFG
Chip Enable Hold Time
Address Advance Hold Time
Configuration Setup(1)
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
8
Integrated Circuit Solution Inc.
SSR005-0B
IS61LV6432
READ CYCLE TIMING: PIPELINE
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE1 inactive
ADSC initiate read
t
SS
tSH
t
SS
tSH
t
AVH
t
AVS
Suspend Burst
ADV
t
AS
tAH
A15-A0
RD1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
BW4-BW1
t
CES
tCEH
CE1 Masks ADSP
CE1
CE2
CE3
t
t
CES
CES
t
t
CEH
CEH
Unselected with CE2
CE2 and CE3 only sampled with ADSP or ADSC
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
3a
1a
t
KQLZ
t
KQHZ
t
KQ
DATAIN
Pipelined Read
Burst Read
Single Read
Unselected
Integrated Circuit Solution Inc.
9
SSR005-0B
IS61LV6432
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
-133
-117
-5
-6
-7
-8
Symbol Parameter
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKC
Cycle Time
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7.5
2.8
2.8
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8.5
3.0
3.0
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
3.5
3.5
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tKH
Clock High Time
2.4
2.4
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
25
4
6
6
tKL
Clock Low Time
4
6
6
tAS
Address Setup Time
Address Status Setup Time
Write Setup Time
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
45
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
52
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
60
tSS
tWS
tDS
Data In Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
Address Status Hold Time
Data In Hold Time
tCES
tAVS
tAH
tSH
tDH
tWH
tCEH
tAVH
tCFG
Notes:
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Configuration Setup(1)
1. Configuration signal MODE is static and must not change during normal operation.
10
Integrated Circuit Solution Inc.
SSR005-0B
IS61LV6432
WRITE CYCLE TIMING
t
KC
CLK
t
KH
tKL
ADSP is blocked by CE1 inactive
ADSC initiate Write
t
SS
tSH
ADSP
ADSC
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
A15-A0
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
t
WS
t
WH
t
WS
tWH
BW4-BW1
WR1
WR2
CE1 Masks ADSP
WR3
t
CES
tCEH
CE1
CE2
CE3
t
t
CES
CES
t
CEH
CEH
Unselected with CE2
CE2 and CE3 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW4-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
Integrated Circuit Solution Inc.
11
SSR005-0B
IS61LV6432
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
-133
-117
-5
-6
-7
-8
Symbol Parameter
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKC
tKH
tKL
Cycle Time
6
—
—
—
5
7.5
2.8
2.8
—
—
—
—
5
8.5
3.0
3.0
—
—
—
—
5
10
3.5
3.5
—
—
—
—
5
12
—
—
—
6
13
—
—
—
7
15
—
—
—
8
Clock High Time
2.4
2.4
—
4
6
6
Clock Low Time
4
6
6
tKQ
tKQX
Clock Access Time
—
1.5
0
—
2
—
2
(2)
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
1.5
0
—
—
5
1.5
0
—
—
5
1.5
0
—
—
6
1.5
0
—
—
6
—
—
6
—
—
6
—
—
6
(2,3)
tKQLZ
0
0
(2,3)
tKQHZ
tOEQ
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
0
2
2
5
5
5
5
6
—
0
6
—
0
6
(2)
tOEQX
0
—
—
3
0
—
—
3
0
—
—
4
0
—
—
4
—
—
5
—
—
6
—
—
6
(2,3)
tOELZ
0
0
0
0
0
0
0
(2,3)
tOEHZ
tAS
—
—
—
—
—
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
45
—
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
52
—
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
60
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
2.5
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
30
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
35
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tSS
Address Status Setup Time
Write Setup Time
tWS
tCES
tAH
Chip Enable Setup Time
Address Hold Time
tSH
Address Status Hold Time
Write Hold Time
tWH
tCEH
tCFG
Notes:
Chip Enable Hold Time
Configuration Setup(1)
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
12
Integrated Circuit Solution Inc.
SSR005-0B
IS61LV6432
READ/WRITE CYCLE TIMING: PIPELINE
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE1 inactive
t
SS
tSH
t
SS
tSH
ADV
t
AS
tAH
A15-A0
RD1
WR1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
t
WS
tWH
WR1
BW4-BW1
t
CES
tCEH
CE1 Masks ADSP
CE1
CE2
CE3
t
t
CES
CES
t
t
CEH
CEH
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE3
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
KQLZ
t
KQHZ
t
KQX
KQHZ
t
KQ
t
1a
DATAIN
t
DS
tDH
Single Write
Burst Read
Single Read
Unselected
Integrated Circuit Solution Inc.
13
SSR005-0B
IS61LV6432
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
-133
-117
-5
-6
-7
-8
Symbol Parameter
Min. Max
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
tKC
tKH
tKL
Cycle Time
6
—
—
—
5
7.5
2.8
2.8
—
—
—
—
5
8.5
3.0
3.0
—
—
—
—
5
10
3.5
3.5
—
1.5
0
—
—
—
5
12
—
—
—
6
13
—
—
—
7
15
—
—
—
8
Clock High Time
2.4
2.4
—
1.5
0
4
6
6
Clock Low Time
4
6
6
tKQ
tKQX
Clock Access Time
—
1.5
0
—
2
—
2
(4)
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
—
—
5
1.5
0
—
—
5
1.5
0
—
—
6
—
—
6
—
—
6
—
—
6
—
—
6
(4,5)
tKQLZ
0
0
(4,5)
tKQHZ
tOEQ
1.5
—
0
1.5
—
1.5
—
1.5
—
0
1.5
—
0
2
2
5
5
5
5
6
—
0
6
—
0
6
(4)
tOEQX
—
—
3
0
—
—
3
0
—
—
4
—
—
4
—
—
5
—
—
6
—
—
6
(4,5)
tOELZ
0
0
0
0
0
0
0
(4,5)
tOEHZ
tAS
—
2.5
2.5
2.5
2.5
2.5
2.5
2
—
—
—
2.5
2.5
2.5
2.5
2.5
2.5
2
—
2.5
2.5
2.5
2.5
2.5
2.5
2
—
2.5
2.5
2.5
2.5
2.5
2.5
2
—
2.5
2.5
2.5
2.5
2.5
2.5
2
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
2.5
2
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
2.5
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tSS
Address Status Setup Time
Chip Enable Setup Time
Address Hold Time
tCES
tAH
tSH
Address Status Hold Time
Chip Enable Hold Time
ZZ Standby(1)
tCEH
tZZS
tZZREC
Notes:
ZZ Recovery(2)
2
2
2
2
2
2
2
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Configuration signal MODE is static and must not change during normal operation.
4. Guaranteed but not 100% tested. This parameter is periodically sampled.
5. Tested with load in Figure 2.
14
Integrated Circuit Solution Inc.
SSR005-0B
IS61LV6432
SNOOZE AND RECOVERY CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
t
SS
tSH
ADV
t
AS
tAH
A15-A0
RD1
RD2
GW
BWE
BW4-BW1
t
CES
tCEH
CE1
CE2
CE3
t
t
CES
CES
t
CEH
CEH
t
t
OEHZ
t
OEQ
OE
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
1a
t
KQLZ
t
KQX
KQHZ
t
KQ
t
DATAIN
ZZ
t
ZZS
tZZREC
Snooze with Data Retention
Single Read
Read
Integrated Circuit Solution Inc.
15
SSR005-0B
IS61LV6432
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency (MHz) Order Part Number
Package
166
133
117
100
83
IS61LV6432-166TQ 14*20*1.4mm LQFP
IS61LV6432-166PQ 14*20*2.7mm PQFP
IS61LV6432-133TQ 14*20*1.4mm LQFP
IS61LV6432-133PQ 14*20*2.7mm PQFP
IS61LV6432-117TQ 14*20*1.4mm LQFP
IS61LV6432-117PQ 14*20*2.7mm PQFP
IS61LV6432-5TQ
IS61LV6432-5PQ
14*20*1.4mm LQFP
14*20*2.7mm PQFP
IS61LV6432-6TQ
IS61LV6432-6PQ
14*20*1.4mm LQFP
14*20*2.7mm PQFP
75
IS61LV6432-7TQ
IS61LV6432-7PQ
14*20*1.4mm LQFP
14*20*2.7mm PQFP
66
IS61LV6432-8TQ
IS61LV6432-8PQ
14*20*1.4mm LQFP
14*20*2.7mm PQFP
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Frequency (MHz)
Order Part Number
Package
117
IS61LV6432-117TQI 14*20*1.4mm LQFP
IS61LV6432-117PQI 14*20*2.7mm PQFP
100
83
IS61LV6432-5TQI 14*20*1.4mm LQFP
IS61LV6432-5PQI 14*20*2.7mm PQFP
IS61LV6432-6TQI 14*20*1.4mm LQFP
IS61LV6432-6PQI 14*20*2.7mm PQFP
75
IS61LV6432-7TQI 14*20*1.4mm LQFP
IS61LV6432-7PQI 14*20*2.7mm PQFP
66
IS61LV6432-8TQI 14*20*1.4mm LQFP
IS61LV6432-8PQI 14*20*2.7mm PQFP
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
16
Integrated Circuit Solution Inc.
SSR005-0B
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