IS62LV1024L-45BI [ICSI]
128K x 8 LOW POWER AND LOW Vcc; 128K ×8低功耗和低Vcc的
| 型号： | IS62LV1024L-45BI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 128K x 8 LOW POWER AND LOW Vcc |
| 文件： | 总10页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS62LV1024L
IS62LV1024LL
128K x 8 LOW POWER and LOW Vcc
CMOS STATIC RAM
ꢀEATURES
DESCRIPTION
The ICSI IS62LV1024L and IS62LV1024LL are low power
and low Vcc,131,072-word by 8-bit CMOS static RAMs. They
are fabricated using ICSI's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative circuit
design techniques, yields higher performance and low power
consumption devices.
Access times of 45, 55, and 70 ns
Low active power: 60 mW (typical)
Low standby power: 15 µW (typical) CMOS
standby
Low data retention voltage: 2V (min.)
Available in Low Power (-L) and
Ultra Low Power (-LL)
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
TTL compatible inputs and outputs
Single 2.7V to 3.6V power supply
The IS62LV1024L and IS62LV1024LL are available in 32-pin
8*20mm TSOP-1, 8*13.4mm TSOP-1, 450mil SOP and 48-pin
6*8mm Tꢀ-BGA.
ꢀUNCTIONAL BLOCK DIAGRAM
512 X 2048
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE1
CE2
CONTROL
CIRCUIT
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
1
IS62LV1024L/LL
PIN CONꢀIGURATION
32-Pin SOP
PIN CONꢀIGURATION
32-Pin 8x20mm TSOP-1 and 8x13.4mm TSOP-1
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
3
4
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
4
5
5
A6
6
6
A5
7
A9
7
A4
8
A11
OE
8
A3
9
9
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
GND
A6
A5
A4
A1
A2
A3
48-Pin 6x8mm Tꢀ-BGA
PIN DESCRIPTIONS
A0-A16
CE1
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
1
2
3
4
5
6
CE2
CE2
WE
NC
A3
A4
A5
A6
A7
A0
I/O
A1
A2
A8
I/O
A
B
C
D
E
F
OE
5
1
WE
I/O
I/O
2
6
I/O0-I/O7
GND
Vcc
Vcc
NCNo onnectionC
GND
Vcc
Power
GND
Ground
I/O
7
NC
CE1
A11
NC
A16
A12
I/O
3
I/O
8
OE
A15
A13
I/O
4
G
H
A9
A10
A14
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
0°C to +70°C
2.7V to 3.6V
2.7V to 3.6V
Industrial
40°C to +85°C
2
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
TRUTH TABLE
Mode
WE CE1 CE2 OE
I/O Operation
Vcc Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Output Disabled H
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Read
Write
H
L
X
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VTERM
VCC
Terminal Voltage with Respect to GND
0.5 to Vcc + 0.5
0.3 to +4.6
40 to +85
65 to +150
0.7
Vcc related to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
V
TBIAS
TSTG
PT
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pꢀ
Input Capacitance
Output Capacitance
6
8
COUT
VOUT = 0V
pꢀ
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = 1.0 mA
VCC = Min., IOL = 2.1 mA
2.2
V
V
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
2.2
0.3
1
VCC + 0.3
V
0.4
1
V
GND ≤ VIN ≤ VCC
µA
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC
1
1
Notes:
1. VIL = 3.0V for pulse width less than 10 ns.
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
3
IS62LV1024L/LL
IS62LV1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45L ns
-55L ns
-70L ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC
Vcc Dynamic Operating
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
40
45
35
40
30
35
mA
Supply Current
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
0.3
0.4
0.3
0.4
0.3
0.4
mA
µA
VIN = VIH or VIL, CE1
≥
VIH Ind.
or CE2
≤ VIL, f = 0
ISB2
CMOS Standby
VCC = Max., f = 0
Com.
Ind.
50
75
50
75
50
75
Current (CMOS Inputs)
CE1
≥
≤
VCC 0.2V,
CE2
0.2V,
or VIN
≥ VCC 0.2V, VIN ≤ 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62LV1024LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45LL ns
-55LL ns
-70LL ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC
Vcc Dynamic Operating
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
40
45
35
40
30
35
mA
Supply Current
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
0.2
0.3
0.2
0.3
0.2
0.3
mA
µA
VIN = VIH or VIL, CE1
≥
VIH Ind.
or CE2
≤ VIL, f = 0
ISB2
CMOS Standby
VCC = Max., f = 0
Com.
Ind.
5
5
5
Current (CMOS Inputs)
CE1
≥
≤
VCC 0.2V,
10
10
10
CE2
0.2V,
or VIN
≥ VCC 0.2V, VIN ≤ 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-45
-55
-70
Symbol Parameter
Min.
45
10
0
Max.
Min.
55
10
5
Max.
Min.
70
10
5
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
tAA
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
45
55
70
tOHA
tACE1
tACE2
tDOE
45
45
20
55
55
25
70
70
35
(2)
tLZOE
OE to Low-Z Output
OE to High-Z Output
(2)
tHZOE
0
15
0
20
0
25
tLZCE1(2) CE1 to Low-Z Output
5
7
10
10
0
tLZCE2(2) CE2 to Low-Z Output
5
7
(2)
tHZCE
CE1 or CE2 to High-Z Output
0
15
0
20
25
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V
and output loading specified in 7igure 1.
2. Tested with the load in 7igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0.4V to 2.2V
5 ns
Input Pulse Level
Input Rise and ꢀall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See ꢀigures 1
AC TEST LOADS
1 TTL
1 TTL
OUTPUT
OUTPUT
100 pF
Including
jig and
5 pF
Including
jig and
scope
scope
)igure 1.
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
)igure 2.
5
IS62LV1024L/LL
AC WAVEꢀORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
DOUT
t
AA
t
OHA
t
OHA
DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CE1
t
ACE1/tACE2
CE2
tLZCE1/
tLZCE2
t
HZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
6
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low
Power)
-45
-55
-70
Symbol Parameter
Min.
45
35
35
35
0
Max.
Min.
55
50
50
50
0
Max.
Min.
70
60
60
60
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
tSCE1
tSCE2
tAW
CE1 to Write End
CE2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
tHA
tSA
0
0
0
(4)
tPWE
WE Pulse Width
35
25
0
40
25
0
55
30
0
tSD
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
tHD
(2)
tHZWE
5
15
5
20
0
25
(2)
tLZWE
5
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V
and output loading specified in 7igure 1.
2. Tested with the load in 7igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEꢀORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE1
t
HA
t
SCE1
t
SCE2
CE2
t
AW
(4)
t
PWE
WE
DOUT
DIN
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATA-IN VALID
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
7
IS62LV1024L/LL
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
t
SA
tHA
t
SCE1
CE1
CE2
t
SCE2
t
AW
(4)
t
PWE
WE
DOUT
DIN
t
HZWE
tLZWE
HIGH-Z
DATA UNDEFINED
t
HD
t
SD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Min.
Max.
Unit
Vcc for Data Retention
Data Retention Current
See Data Retention Waveform
2.0
3.6
V
IDR
Vcc = 2.0V, CE1
≥
Vcc 0.2V
Com. (-L)
Com. (-LL)
Ind. (-L)
30
5
µA
µA
µA
µA
50
10
Ind. (-LL)
tSDR
tRDR
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
0
ns
ns
tRC
DATA RETENTION WAVEꢀORM (CE1 Controlled)
t
Data Retention Mode
t
RDR
SDR
V
V
CC
DR
3.0V
2.2V
CE1 ≥ V
- 0.2V
CC
CE1
GND
8
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
DATA RETENTION WAVEꢀORM (CE2 Controlled)
Data Retention Mode
V
CC
3.0V
2.2V
t
t
RDR
SDR
CE2
V
DR
CE2 ≤ 0.2V
0.4V
GND
IS62LV1024L
IS62LV1024L
ORDERING INꢀORMATION
Commercial Range: 0°C to +70°C
ORDERING INꢀORMATION
Industrial Range: 40°C to +85°C
Speed (nsꢀ Order Part No.
Package
Speed (nsꢀ Order Part No.
Package
45
55
70
IS62LV1024L-45Q
IS62LV1024L-45T
IS62LV1024L-45H
IS62LV1024L-45B
450mil SOP
45
55
70
IS62LV1024L-45QI
IS62LV1024L-45TI
IS62LV1024L-45HI
IS62LV1024L-45BI
450mil SOP
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
IS62LV1024L-55Q
IS62LV1024L-55T
IS62LV1024L-55H
IS62LV1024L-55B
450mil SOP
IS62LV1024L-55QI
IS62LV1024L-55TI
IS62LV1024L-55HI
IS62LV1024L-55BI
450mil SOP
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
IS62LV1024L-70Q
IS62LV1024L-70T
IS62LV1024L-70H
IS62LV1024L-70B
450mil SOP
IS62LV1024L-70QI
IS62LV1024L-70TI
IS62LV1024L-70HI
IS62LV1024L-70BI
450mil SOP
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
9
IS62LV1024L/LL
IS62LV1024LL
IS62LV1024LL
ORDERING INꢀORMATION
Commercial Range: 0°C to +70°C
ORDERING INꢀORMATION
Industrial Range: 40°C to +85°C
Speed (nsꢀ Order Part No.
Package
Speed (nsꢀ Order Part No.
Package
45
55
70
IS62LV1024LL-45Q
IS62LV1024LL-45T
IS62LV1024LL-45H
IS62LV1024LL-45B
450mil SOP
45
55
70
IS62LV1024LL-45QI
IS62LV1024LL-45TI
IS62LV1024LL-45HI
IS62LV1024LL-45BI
450mil SOP
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
IS62LV1024LL-55Q
IS62LV1024LL-55T
IS62LV1024LL-55H
IS62LV1024LL-55B
450mil SOP
IS62LV1024LL-55QI
IS62LV1024LL-55TI
IS62LV1024LL-55HI
IS62LV1024LL-55BI
450mil SOP
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
IS62LV1024LL-70Q
IS62LV1024LL-70T
IS62LV1024LL-70H
IS62LV1024LL-70B
450mil SOP
IS62LV1024LL-70QI
IS62LV1024LL-70TI
IS62LV1024LL-70HI
IS62LV1024LL-70BI
450mil SOP
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm Tꢀ-BGA
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
"ax: 886-3-5783000
BRANCH O""ICE:
7", NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
"AX: 886-2-26962252
http://www.icsi.com.tw
10
Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
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