IS63LV1024-8TI [ICSI]
Standard SRAM, 128KX8, 8ns, CMOS, PDSO32,;
| 型号： | IS63LV1024-8TI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Standard SRAM, 128KX8, 8ns, CMOS, PDSO32, 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS63LV1024
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
FEATURES
DESCRIPTION
The ICSI IS63LV1024 is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The IS63LV1024 is fabricated using ICSI's high-
performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
High-speed access times:
8, 10, 12 and 15 ns
High-performance, low-power CMOS process
Multiple center power and ground pins for
greater noise immunity
Easy memory expansion with CE and OE
options
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
CE power-down
Fully static operation: no clock or refresh
required
The IS63LV1024 operates from a single 3.3V power supply
and all inputs are TTL-compatible.
TTL compatible inputs and outputs
Single 3.3V power supply
The IS63LV1024 is available in 32-pin 300mil SOJ, 400mil
SOJ, and 400mil TSOP-2 packages.
Packages available:
32-pin 300mil SOJ
32-pin 400mil SOJ
32-pin 400mil TSOP-2
FUNCTIONAL BLOCK DIAGRAM
128K X 8
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR019-0C
1
IS63LV1024
PIN CONFIGURATION
32-Pin SOJ
PIN CONFIGURATION
32-Pin TSOP-2
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/o7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A0
A1
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
2
2
3
A2
3
4
A3
4
5
6
CE
5
7
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
6
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
8
7
9
8
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
A5
A6
A7
A8
A5
A6
A7
A8
PIN DESCRIPTIONS
TRUTH TABLE
Mode
WE CE OE I/O Operation Vcc Current
A0-A16
CE
Address Inputs
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
OE
Output Disabled H
L
L
L
H
L
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
WE
Read
Write
H
L
I/O1-I/O8
Vcc
X
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
0.5 to Vcc + 0.5
55 to +125
65 to +150
1.0
°C
°C
W
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2
Integrated Circuit Solution Inc.
SR019-0C
IS63LV1024
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
3.3V ± 0.3V
3.3V ± 0.3V
40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = 4.0 mA
VCC = Min., IOL = 8.0 mA
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
V
2.2
VCC + 0.3
0.8
V
0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
2
5
2
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
Com.
Ind.
2
5
2
5
µA
Notes:
1. VIL = 3.0V for pulse width less than 10 ns.
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Max.
-10 ns
-12 ns
-15 ns
Symbol Parameter
Test Conditions
Min.
Min.
Max.
Min.
Max.
Min.
Max. Unit
ICC1
Vcc Operating
VCC = Max., CE = VIL
Com.
Ind.
160
170
150
160
140
150
130
140
mA
Supply
CurrentIOUT = 0 mA, f = Max.
ISB1
TTL Standby
CurrentV
VCC = Max.,
Com.
Ind.
30
40
30
40
30
40
30
40
mA
IN = VIH or VIL
(TTL Inputs)
CE
≥
VIH, f = 0
ISB2
CMOS Standby
Current
VCC = Max.,
CE VCC 0.2V,
VIN > VCC 0.2V, or
VIN 0.2V, f = 0
Com.
Ind.
10
15
10
15
10
15
10
15
mA
≤
(CMOS Inputs)
≤
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Input/Output Capacitance
6
8
CI/O
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Circuit Solution Inc.
SR019-0C
3
IS63LV1024
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min.
-10 ns
Min.
-12 ns
Min.
-15 ns
Min.
Symbol Parameter
Max.
8
Max.
10
10
5
Max.
12
12
6
Max.
15
15
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
8
3
10
3
12
3
15
3
tAA
Address Access Time
Output Hold Time
CE Access Time
tOHA
tACE
tDOE
tLZOE
8
0
0
0
0
OE Access Time
4
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
4
5
6
7
tHZOE
0
0
0
0
(2)
tLZCE
tHZCE
3
4
3
5
3
6
3
7
(2)
0
0
0
0
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
1.5V
Output Load
See Figures 1a and 1b
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
317 Ω
Z
OUT = 50 Ω
3.3V
OUTPUT
OUTPUT
50 Ω
351 Ω
5 pF
Including
jig and
scope
V
T
= 1.5V
Figure 1a.
Figure 1b.
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Integrated Circuit Solution Inc.
SR019-0C
IS63LV1024
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Circuit Solution Inc.
SR019-0C
5
IS63LV1024
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns
Min.
-10 ns
Min.
-12 ns
-15 ns
Min.
Symbol Parameter
Max.
Max.
Min.
Max.
Max.
Unit
ns
tWC
tSCE
tAW
Write Cycle Time
8
7
7
10
8
12
9
15
10
10
CE to Write End
ns
Address Setup Time to
Write End
8
9
ns
tHA
Address Hold from
Write End
0
0
0
0
ns
tSA
Address Setup Time
0
7
4
0
8
6
0
0
0
5
0
9
6
0
0
0
6
0
10
7
7
ns
ns
ns
ns
ns
ns
(4)
tPWE
tSD
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
4.5
0
tHD
0
(2)
tHZWE
0
0
(2)
tLZWE
0
0
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
6
Integrated Circuit Solution Inc.
SR019-0C
IS63LV1024
WRITE CYCLE NO. 2(CE Controlled)(1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ VIH.
Integrated Circuit Solution Inc.
SR019-0C
7
IS63LV1024
ORDERING INFORMATION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: 40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
8
8
8
IS63LV1024-8T
IS63LV1024-8J
IS63LV1024-8K
400mil TSOP-2
300mil SOJ
8
8
8
IS63LV1024-8TI
IS63LV1024-8JI
IS63LV1024-8KI
400mil TSOP-2
300mil SOJ
400mil SOJ
400mil SOJ
10
10
10
IS63LV1024-10T
IS63LV1024-10J
IS63LV1024-10K
400mil TSOP-2
300mil SOJ
10
10
10
IS63LV1024-10TI
IS63LV1024-10JI
IS63LV1024-10KI
400mil TSOP-2
300mil SOJ
400mil SOJ
400mil SOJ
12
12
12
IS63LV1024-12T
IS63LV1024-12J
IS63LV1024-12K
400mil TSOP-2
300mil SOJ
12
12
12
IS63LV1024-12TI
IS63LV1024-12JI
IS63LV1024-12KI
400mil TSOP-2
300mil SOJ
400mil SOJ
400mil SOJ
15
15
15
IS63LV1024-15T
IS63LV1024-15J
IS63LV1024-15K
400mil TSOP-2
300mil SOJ
15
15
15
IS63LV1024-15TI
IS63LV1024-15JI
IS63LV1024-15KI
400mil TSOP-2
300mil SOJ
400mil SOJ
400mil SOJ
Integrated Circuit Solution Inc.
HEADQUARTER:
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TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
8
Integrated Circuit Solution Inc.
SR019-0C
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