MK2049-01SITR [ICSI]
Communications Clock PLL; 通信时钟PLL
| 型号： | MK2049-01SITR |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Communications Clock PLL |
| 文件： | 总11页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK2049-01
Communications Clock PLL
Description
Features
• Packaged in 20 pin SOIC
The MK2049 is a Phase-Locked Loop (PLL) based
clock synthesizer, which accepts an 8 kHz clock
input as a reference and generates T1, E1, T3, E3,
and OC3 frequencies. The device can also accept a
T1, E1, T3, or E3 input clock and provide the
same output for loop timing. All outputs are
frequency locked together and to the input. This
allows for the generation of locked clocks to an
8 kHz backplane clock, simplifying clock
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock or
Loop Timing frequencies
distribution in communications systems.
• Locks to 8 kHz ±100 ppm (External mode)
• Exact internal ratios eliminate the need for external
dividers
MicroClock can customize this device for many
other different frequencies. Contact your
MicroClock representative for more details.
• Zero ppm synthesis error in all output clocks.
• Output clock rates include T1, E1, T3, E3, and
OC3÷8
For a fixed input-output phase relationship, refer
to the MK2049-02, -03, or -3x. The MK2049-3x
are 3.3 V devices.
• 5 V ±5% operation
• Offered in Commercial and Industrial temperature
versions
Block Diagram
VDD GND
4
4
4
FS3:0
Output
Buffer
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
CLK1
CLK2
8 kHz
External/
Loop
Timing
Mux
Clock
Input
Output
Buffer
Reference
Crystal
Output
Buffer
X1
X2
Crystal
Oscillator
CAP1
CAP2
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
Pin Assignment
Output Decoding Table – External Mode (MHz)
Input
FS3 FS2 FS1 FS0
CLK1
1.544
2.048
22.368
17.184
19.44
CLK2
3.088
4.096
44.736
34.368
38.88
Crystal
12.288
12.288
12.288
12.288
12.96
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1
2
3
4
5
6
7
8
9
FS1
X2
20 FS0
19
18
17
16
15
14
13
GND
CAP2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
GND
CAP1
VDD
GND
ICLK
Output Decoding Table – Loop Timing Mode (MHz)
Input
1.544
2.048
44.736
34.368
FS3 FS2 FS1 FS0
CLK1
1.544
2.048
22.368
17.184
CLK2
3.088
4.096
44.736
34.368
Crystal
12.288
12.288
12.288
12.288
12 FS3
11 FS2
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
8K 10
20 pin (300 mil) SOIC
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is applied to pins 2 and 3; clock input is applied to pin 13.
Pin Descriptions
Number
Name
FS1
Type Description
1
I
O
I
Frequency Select 1. Determines CLK input/outputs per tables above.
Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
Crystal conection. Connect to a 12.288 MHz or 12.96 MHz crystal.
Connect to +5V.
2
X2
3
X1
4
VDD
VDD
VDD
GND
CLK2
CLK1
8K
P
P
P
P
O
O
O
I
5
Connect to +5V.
6
Connect to +5V.
7
Connect to ground.
8
Clock 2 output determined by status of FS3:0 per tables above.
Clock 1 output determined by status of FS3:0 per tables above. CLK2 divided by 2.
Recovered 8 kHz clock output. On External mode only.
Frequency Select 2. Determines CLK input/outputs per tables above.
Frequency Select 3. Determines CLK input/outputs per tables above.
Input clock connection. Connect to 8 kHz backplane or to Loop Timing clock.
Connect to ground.
9
10
11
12
13
14
15
16
17
18
19
20
FS2
FS3
I
ICLK
GND
VDD
CAP1
GND
CAP2
GND
FS0
I
P
P
Connect to +5V.
LF Connect a 0.030 µF ceramic capacitor and a 7.5 MW resistor in series between this pin and CAP2.
Connect to ground.
LF Connect a 0.030 µF ceramic capacitor and a 7.5 MW resistor in series between this pin and CAP1.
P
P
I
Connect to ground.
Frequency Select 0. Determines CLK input/outputs per tables above.
Type: I = Input, O = output, P = power supply connection, LF = loop filter connection
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
VDD+0.5
70
V
V
Inputs and Clock Outputs
Ambient Operating Temperature
-0.5
0
°C
°C
°C
°C
MK2049-01SI only
Max of 10 seconds
-40
85
Soldering Temperature
Storage Temperature
250
-65
150
DC CHARACTERISTICS (VDD = 5 V unless noted)
Operating Voltage, VDD
4.75
2
5.25
0.8
V
V
Input High Voltage, VIH
Input Low Voltage, VIL
V
Output High Voltage
Output High Voltage
Output Low Voltage
IOH=-4mA
VDD-0.4
2.4
V
IOH=-25mA
IOL=25mA
V
0.4
V
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance, FS3:0
No Load, VDD=5.0V
Each output
20
±100
7
mA
mA
pF
AC CHARACTERISTICS (VDD = 5 V unless noted)
Input Frequency, External Mode
Input Crystal Frequency
ICLK
8.0000
12.2880
12.9600
kHz
MH z
MH z
ns
X1, X2
Input Crystal Frequency
X1, X2. Selection 0111
0.8 to 2.0V
Output Clock Rise Time
1.5
1.5
60
0
Output Clock Fall Time
2.0 to 0.8V
ns
Output Clock Duty Cycle, High Time
Actual mean frequency error versus target
At VDD/2
40
49 to 51
0
%
Any clock selection
ppm
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
OPERATING MODES
The MK2049-01 has two operating modes: External and Loop Timing. Although both modes use an input
clock to generate various output clocks, there are important differences in their input requirements.
External Mode
The MK2049-01 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as
narrow as 10 ns is acceptable.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1
and E1 inputs, the CLK1 output will be the same as the input frequency, with CLK2 at twice the input
frequency. For T3 and E3 inputs, CLK1 will be 1/2 the input frequency and CLK2 will be the same as the
input frequency.
FREQUENCY LOCKING TO THE INPUT
In both modes, the output clocks are frequency-locked to the input. The output will remain at the specified
output frequency as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.
INPUT AND OUTPUT SYNCHRONIZATION
The rising edges of CLK1 and CLK2 do not have a fixed phase alignment with the rising edge of ICLK.
Each time the device is powered-up, the phase relationship could change. Refer to one of the other
MK2049 versions (e.g., MK2049-02, -03, -34) if input-output phase alignment is important in your
application.
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
LAYOUT AND EXTERNAL COMPONENTS
The MK2049-01 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF must be connected between VDD and GND pins close to the chip (especially pins 4
and 7, 15 and 17), and 33 Wseries terminating resistors should be used on clock outputs with traces longer
than 1 inch (assuming 50 Wtraces). The loop filter components should be connected as close to the chip as
possible. Refer to the next section for more information.
PC Board Layout
A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins
are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as
possible and the two capacitors and resistor must be mounted next to the device as shown below. The
capacitor shown between pins 15 and 17, and the one between pins 5 and 7 are the power supply decoupling
capacitors. The high frequency output clocks on pins 8 and 9 should have a series termination of 33 W
connected close to the pin. Additional improvements will come from keeping all components on the same
side of the board, minimizing vias through other signal layers, and routing other signals away from the
MK2049. You may also refer to MAN05 for additional suggestions on layout of the crystal section.
The crystal traces should include pads for small capacitors from X1 and X2 to ground; these are used to
adjust the stray capacitance of the board to match the crystal load capacitance. The typical telecom reference
frequency is accurate to much less than 1 ppm, so the MK2049 may lock and run properly even if the board
capacitance is not adjusted with these fixed capacitors. However, ICS MicroClock recommends that the
adjustment capacitors be included to minimize the effects of variation in individual crystals, temperature,
and aging. The value of these capacitors (typically 0-4 pF) is determined once for a given board layout,
using the procedure described later in this section, titled “Determining the Crystal Frequency Adjustment
Capacitors”.
Cutout in ground and power plane.
Route all traces away from this area.
cap
Optional;
see text
G
1
2
3
20
19
18
cap
cap
resist.
cap
V
4
5
6
17
16
15
G
cap
cap
V
7
14
13
12
11
=connect to VDD
resist.
V
G
8
9
=connect to GND
resist.
10
Figure 1. MK2049-01 Layout Example
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
LAYOUT AND EXTERNAL COMPONENTS (continued)
Loop Filter Components
The external loop filter should be connected between CAP1 and CAP2 as shown in Figure 2 below, and as
close to the chip as possible. Be sure to follow the recommendations on capacitor types described on page 6.
CAP2
7.5 MW
1.5 nF
0.030 µF
CAP1
Figure 2. Loop Filter component values for most configurations
Typical component values are shown. Contact the ICS MicroClock applications
department at (408)297-1201 for the recommended values for your application.
Crystal Operation
The MK2049 operates by phase locking the input signal to a VCXO which consists of the special
recommended crystal and the integrated VCXO oscillator circuit on the MK2049. To achieve the best
performance and reliability, the layout guidelines shown on the previous page must be closely followed.
The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected
to it. The MK2049 has variable load capacitors on-chip which “pull”, or change the frequency of the crystal.
External stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To
achieve this, the layout should use short traces between the MK2049 and the crystal.
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
LAYOUT AND EXTERNAL COMPONENTS (continued)
Crystal Specifications
Parameter
Minimum
Typical
Maximum
Units
°C
Operating Temperature Range
Initial Accuracy at 25 C
Temperature stability
Aging, first year
0
25
70
20
30
5
-20
-30
-5
ppm
ppm
ppm
ppm
Aging, 10 years
-20
20
Load Capacitance
Note 1
Shunt Capacitance, C0
Motional Capacitance, C1
C0/C1 ratio
7
pF
pF
none
none
250
35
none
Ohms
Equivalent Series Resistance
*This ratio decreases for lower crystal frequencies.
Note 1: Nominal crystal load capacitance specification varies with frequency.
Contact the ICS MicroClock applications department at (408)297-1201.
Note 2: The third overtone mode of the crystal and all spurs must be >200 ppm
away from 3x the fundamental resonance shown in the table below.
For recommended crystal devices, please contact the ICS MicroClock application department
at 408-297-1201.
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
LAYOUT AND EXTERNAL COMPONENTS (continued)
Determining the Crystal Frequency Adjustment Capacitors
To determine the crystal adjustment capacitor values, you will need a PC board of your final layout, a
frequency counter capable of less than 1 ppm resolution and accuracy, two power supplies, and some samples
of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at
the specified load capacitance, C .
L
To determine the value of the crystal capacitors:
1. Connect VDD of the MK2049 to 5.0 V. Connect pin 18 of the MK2049 to the second power supply.
Adjust the voltage on pin 18 to 0.0 V. Measure and record the frequency of the CLK1 or CLK2 output .
2. Adjust the voltage on pin 18 to 3.0 V. Measure and record the frequency of the same output.
To calculate the centering error:
(f
- f
) + (f
- f
)
3.0V target
0.0V target
Centering
error
6
- error
= 10
xtal
f
target
Where f
target
= 44.736000 MHz, for example, and error
= actual initial accuracy (in ppm) of the
xtal
crystal being measured.
If the centering error is less than ±15 ppm, no adjustment is needed. If the centering error is more than
15 ppm negative, the PC board has too much stray capacitance and will need to be redone with a new layout
to reduce stray capacitance. (The crystal may be re-specified to a lower load capacitance instead. Contact ICS
MicroClock for details.) If the centering error is more than 15 ppm positive, add identical fixed centering
capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by:
External Capacitor = 2*(centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is
acceptably low (less than ±15 ppm).
The MicroClock Applications department can perform this procedure on your board. Call us at 408-295-
9800, and we will arrange for you to send us a PC board (stuffed or unstuffed) and one of your crystals. We
will calculate the value of capacitors needed.
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
Input Jitter
Measured Jitter Output (UIp-p)
Modulation Input Jitter
Output Jitter
Magnitude
(UIp-p)
1.07
Jitter
Attenuation
(dB)
Frequency
(Hz)
10
Magnitude
(UIp-p)
10
19.41
25.04
28.87
36.65
48.64
55.92
60.00
60.00
60.00
60.00
57.79
52.00
44.81
20
10
0.56
0.36
0.147
0.037
0.016
0.01
0.01
0.01
0.01
0.01
40
10
100
10
400
10
1000
2000
4000
8000
10000
16000
32000
64000
10
10
10
10
10
7.75
3.98
1.74
0.01
0.01
Table 1. Jitter results for a T1 (1.544 MHz) reference frequency, as
measured on the HP3785B (10 Hz - 40 kHz output filter).
Input Jitter
Measured Jitter Output (UIp-p)
Modulation Input Jitter
Output Jitter
Magnitude
(UIp-p)
0.071
0.07
Jitter
Attenuation
(dB)
Frequency
(Hz)
Magnitude
(UIp-p)
10.5
100
43.4
400
10.5
43.52
37.26
38.84
42.36
43.52
44.03
44.17
44.86
44.86
45.16
44.86
44.58
1000
10.5
0.144
0.12
0.08
2000
10.5
4000
10.5
8000
10.5
0.07
10000
16000
32000
64000
128000
192000
256000
10.5
10.5
10.5
10.5
10.5
10.5
10.5
0.066
0.065
0.06
0.06
0.058
0.06
0.062
Table 2. Jitter results for a T3 (44.736 MHz) reference frequency, as
measured on the HP3785B (10 Hz -1.1 MHz output filter).
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
Input Jitter
Measured Jitter Output (UIp-p)
Modulation Input Jitter
Output Jitter
Magnitude
(UIp-p)
0.018
Jitter
Attenuation
(dB)
Frequency
(Hz)
Magnitude
(UIp-p)
1.5
20
38.42
40.60
43.52
43.52
46.62
47.96
47.96
41.58
35.56
32.04
30.46
30.46
30.46
50
1.5
0.014
0.01
0.01
0.007
0.006
0.006
0.006
0.006
0.006
0.006
0.006
0.006
100
1.5
200
1.5
500
1.5
1000
2000
5000
10000
15000
25000
50000
75000
1.5
1.5
0.72
0.36
0.24
0.20
0.20
0.20
Table 3. Jitter results for an E1 (2.048 MHz) reference frequency, as
measured on the HP3785A (100 Hz -800 kHz output filter).
Input Jitter
Measured Jitter Output (UIp-p)
Modulation Input Jitter
Output Jitter
Magnitude
(UIp-p)
0.113
Jitter
Attenuation
(dB)
Frequency
(Hz)
Magnitude
(UIp-p)
1.5
100
22.46
24.06
25.79
26.74
26.62
20.5
34.22
30.7
29.12
29.12
29.12
29.12
200
1.5
0.094
0.077
0.069
0.07
0.068
0.007
0.007
0.007
500
1.5
1000
1.5
2000
1.5
5000
0.72
0.36
0.24
0.2
0.2
0.2
10000
15000
25000
50000
75000
100000
0.007
0.007
0.007
0.2
Table 4. Jitter results for an E3 (34.368 MHz) reference frequency, as
measured on the HP3785A (100 Hz - 800 kHz output filter).
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
MK2049-01
Communications Clock PLL
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
20 pin SOIC
Inches
Millimeters
Symbol Min
Max
0.104
--
Min
Max
2.65
--
A
A1
B
C
D
E
--
--
0.0040
0.10
0.33
0.18
E
H
0.013 0.020
0.007 0.013
0.51
0.33
13.00
7.60
INDEX
AREA
0.496 0.512 12.60
0.291 0.299
.050 BSC
7.40
e
1.27 BSC
1
2
H
h
0.394 0.419 10.01
10.64
0.74
1.27
0.01
0.029
0.25
0.41
h x 45°
D
L
0.016 0.050
A
A1
C
B
e
L
Ordering Information
Part/Order Number
Marking
Package
Temperature
MK2049-01S
MK2049-01STR
MK2049-01SI
MK2049-01S
MK2049-01S
MK2049-01SI
MK2049-01SI
20 pin SOIC
Add Tape & Reel
20 pin SOIC
0 to 70 °C
0 to 70 °C
-40 to 85 °C
-40 to 85 °C
MK2049-01SITR
Add Tape & Reel
While the information presented herein has been checked for both accuracy and reliability, ICS/MicroClock assumes no responsibility for either its use or for the infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS/MicroClock. ICS/MicroClock reserves the right to change any circuitry or specifications without notice. ICS/MicroClock
does not authorize or warrant any ICS/MicroClock product for use in life support devices or critical medical instruments.
MDS 2049-01 J
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Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
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