MK2308S-2I [ICSI]
ZERO DELAY LOW SKEW BUFFER; 零延迟低偏移缓冲器型号: | MK2308S-2I |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | ZERO DELAY LOW SKEW BUFFER |
文件: | 总5页 (文件大小:122K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MK2308-2
ZERO DELAY, LOW SKEW BUFFER
Description
Features
The MK2308-2 is a low jitter, low skew, high
• Packaged in 16-pin SOIC
performance Phase-Lock Loop (PLL) based zero delay
buffer for high speed applications. Based on ICS’
proprietary low jitter PLL techniques, the device
provides eight low skew outputs at speeds up to 160
MHz at 3.3 V. The MK2308-2 includes a bank of four
outputs running at 1/2X. In the zero delay mode, the
rising edge of the input clock is aligned with the rising
edges of all eight outputs. Compared to competitive
CMOS devices, the MK2308-2 has the lowest jitter.
• Zero input-output delay
• Four 1X outputs plus four 1/2X outputs
• Output to output skew is less than 250 ps
• Output clocks up to 160 MHz at 3.3 V
• Ability to generate 2X the input
• Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3 V
TM
• Spread Smart technology works with spread
spectrum clock generators
• Advanced, low power, sub micron CMOS process
• Operating voltage of 3.3 V or 5 V
Block Diagram
VDD
2
CLKA1
CLKA2
CLKA3
CLKA4
FBIN
PLL
BANK
A
CLKIN
/2
CLKB1
CLKB2
CLKB3
CLKB4
BANK
B
Control
Logic
2
S2, S1
2
GND
MDS 2308-2 B
1
Revision 111103
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK2308-2
ZERO DELAY, LOW SKEW BUFFER
Pin Assignment
Feedback Configuration Table
Feedback From
Bank A
CLKA1:A4
CLKIN
CLKB1:B4
CLKIN/2
CLKIN
CLKIN
CLKA1
CLKA2
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBIN
CLKA4
CLKA3
VDD
Bank B
2XCLKIN
GND
GND
CLKB1
CLKB2
S2
CLKB4
CLKB3
S1
16-pin (150 mil) SOIC
Output Clock Mode Select Table
S2 S1
Clocks A1:A4
Clocks B1:B4
Internet Generation
PLL Status
0
0
1
1
0
1
0
1
Tri-state (high impedance) Tri-state (high impedance)
None
On
On
Off
On
Running
Running
Running
Tri-state (high impedance)
Running
PLL
Buffer only (no zero delay)
PLL
Running
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
2 - 3
4
CLKIN
Input Clock input. Connect to input clock source.
CLKA1:A4 Output Clock A bank of four outputs.
VDD
GND
Power Power supply. Connect pin to same voltage as pin 13 (either 3.3 V or 5 V).
Power Connect to ground.
5
6 - 7
8
CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A.
S2
S1
Input Select input 2. Selects mode for outputs per table above.
Input Select input 1. Selects mode for outputs per table above.
9
10 - 11
12
CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A.
GND
VDD
Power Connect to ground.
13
Power Power supply. Connect pin to same voltage as pin 4 (either 3.3 V or 5 V).
14 - 15
16
CLKA1:A4 Output Clock A bank of four outputs.
FBIN Input Feedback input. Determines outputs per table above.
MDS 2308-2 B
2
Revision 111103
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK2308-2
ZERO DELAY, LOW SKEW BUFFER
External Components
The MK2308-2 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND, as close to the part as possible. A 33Ω
series terminating resistor should be used on each clock output to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2308-2. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70 °C
-65 to +150 °C
175 °C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260 °C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.0
+5.5
V
DC Electrical Characteristics
VDD=3.3 V ±10%, Temp 0 to +70° /-40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
5.5
V
V
V
V
V
V
V
V
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CLKIN pin only
CLKIN pin only
(VDD/2)+1 VDD/2
IH
V
VDD/2 (VDD/2)-1
IL
V
2
IH
V
0.8
0.4
IL
V
I
I
I
= -18 mA
= 18 mA
= -5 mA
2.4
OH
OH
OL
OH
V
OL
V
VDD-0.4
OH
MDS 2308-2 B
3
Revision 111103
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK2308-2
ZERO DELAY, LOW SKEW BUFFER
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Supply Current
100 MHz, CLKIN
IDD
No Load
S1=S2=1
44
mA
Short Circuit Current
Input Capacitance
I
Each output
S1, S1, FBIN
± 65
7
mA
pF
OS
C
IN
AC Electrical Characteristics
VDD = 3.3V ±10%, Temp 0 to +70°/ -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Frequency
FBIN to CLKA1
S1=S2=1
20
160
MHz
Output Frequency
FBIN to CLKA1
S1=S2=1
20
160
MHz
Output Rise Time
t
0.8 to 2.0 V, C =30 pF
1.5
1.5
60
ns
ns
%
OR
L
Output Fall Time
t
0.8 to 2.0 V, C =30 pF
OF
L
Output Clock Duty Cycle
at 1.4V
40
50
Device to Device skew, equally
loaded
rising edges at VDD/2
700
ps
Output to Output skew, equally
loaded
rising edges at VDD/2
200
ps
Maximum Absolute Jitter
Cycle to Cycle Jitter
300
ps
ps
30 pF loads
66.67 MHz outputs
400
400
400
±250
1
15 pF loads
66.67 MHz outputs
ps
ps
ps
ms
Skew from Output Bank A to
Output Bank B
All outputs equally
loaded
Delay CLKIN Rising Edge to
FBIN Rising Edge
measured at VDD/2
PLL Lock Time
t
Stable power supply,
valid clocks on CLKIN,
FBIN
LOCK
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
120
115
105
58
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 2308-2 B
4
Revision 111103
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
MK2308-2
ZERO DELAY, LOW SKEW BUFFER
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
16
Symbol
Min
Max
1.75
0.25
0.51
0.25
10.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
9.80
3.80
.0532
.0040
.013
.0688
.0098
.020
E
H
INDEX
AREA
.0075
.3859
.1497
.0098
.3937
.1574
1.27 BASIC
0.050 BASIC
1
2
H
h
5.80
0.25
0.40
0°
6.20
.2284
.010
.016
0°
.2440
.020
.050
8°
0.50
1.27
8°
D
L
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping
Package
Temperature
packaging
MK2308S-2
MK2308S-2T
MK2308S-2I
MK2308S-2IT
MK2308S-2
MK2308S-2T
MK2308S-2I
MK2308S-2IT
Tubes
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
0 to 70° C
0 to 70° C
Tape and Reel
Tubes
-40 to +85° C
-40 to +85° C
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit
Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of
third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice.
ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 2308-2 B
5
Revision 111103
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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