MK3725 [ICSI]
DUAL OUTPUT 3.3 VOLT VCXO; 双输出3.3伏VCXO
| 型号： | MK3725 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DUAL OUTPUT 3.3 VOLT VCXO |
| 文件： | 总6页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK3725
DUAL OUTPUT 3.3 VOLT VCXO
Description
Features
The MK3725 is a low cost, high-performance, two
output 3.3 Volt VCXO and PLL clock synthesizer
designed to replace expensive VCXOs and crystals.
The patented on-chip Voltage Controlled Crystal
Oscillator accepts a 0 to 3.3 V input voltage to cause
the output clocks to vary by ±115 ppm minimum. Using
our analog Phase Locked Loop (PLL) techniques, the
device uses an external, fundamental mode pullable
crystal input to produce output clocks of 2x the input
frequency.
• Packaged in 8-pin SOIC
• Operating voltage of 3.3 V (±5%)
• Two pullable output clocks of 24-36 MHz
• Uses a fundamental mode 12-18 MHz pullable
crystal
• On-chip patented VCXO with pull range of 230 ppm
(minimum)
• VCXO tuning voltage of 0 to 3.3 V
• 12 mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
The frequency of the on-chip VCXO is adjusted by an
external control voltage input into pin VIN. Because
VIN is a high impedance input, it can be driven directly
from an PWM RC integrator circuit.
Block Diagram
VDD
VIN
X1
Voltage
Controlled
Crystal
Frequency
Clock
Doubler
2
24-36 MHz
Oscillator
X2
12-18 MHz
Pullable
Crystal
GND
MDS 3725 A
1
Revision 100803
Integrated Circuit Systems z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
MK3725
DUAL OUTPUT 3.3 VOLT VCXO
Pin Assignment
X 1
V D D
V I N
8
7
6
5
1
2
3
4
X 2
V D D
C L K
C L K
G N D
8 P i n ( 1 5 0 m i l ) S O I C
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
X1
Input
Crystal connection. Connect to a 12-18 MHz external pullable
crystal.
2
3
VDD
VIN
Power Connect to +3.3 V.
Input
Voltage input to VCXO. Zero to 3.3 V analog input which controls
the oscillation frequency of the VCXO.
4
5
6
7
8
GND
CLK
CLK
VDD
X2
Input
Connect to ground.
Output VCXO clock output. 2x input frequency.
Output VCXO clock output. 2x input frequency.
Power Connect to +3.3 V.
Output Crystal connection. Connect to a 12-18 MHz external pullable
crystal.
MDS 3725 A
2
Revision 100803
Integrated Circuit Systems z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
MK3725
DUAL OUTPUT 3.3 VOLT VCXO
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
External Component Selection
The MK3725 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD (pin 2 & 7) and GND (pin 4), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
Series Termination Resistor
Use series termination when the PCB trace between
the clock outputs and the loads are over 1 inch. To
series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3725 to 3.3 V. Connect pin 3
of the MK3725 to the second power supply. Adjust the
voltage on pin 3 to 0V. Measure and record the
frequency of the CLK output.
2. Adjust the voltage on pin 3 to 3.3 V. Measure and
record the frequency of the same output.
Quartz Crystal
To calculate the centering error:
The MK3725 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (as described in application
note MAN05) must be used, and the layout guidelines
discussed in the following section must be followed.
(f3.0V – ft arget) + (f0V – ft arget
)
Error = 106x
– errorxtal
------------------------------------------------------------------------------
ft arget
Where:
= nominal crystal frequency
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The MK3725 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the MK3725 is designed to have zero frequency
error when the total of on-chip + stray capacitance is
14 pF.
f
target
error
=actual initial accuracy (in ppm) of the crystal
xtal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS MicroClock for details.) If the
centering error is more than 25 ppm positive, add
identical fixed centering capacitors from each crystal
pin to ground. The value for each of these caps (in pF)
is given by:
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3725. There should be no vias between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal.
Crystal Tuning Load Capacitors
External Capacitor =
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
2 x (centering error)/(trim sensitivity)
MDS 3725 A
3
Revision 100803
Integrated Circuit Systems z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
MK3725
DUAL OUTPUT 3.3 VOLT VCXO
Trim sensitivity is a parameter which can be supplied by
your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than ±25 ppm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3725. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70°C
Ambient Operating Temperature
Storage Temperature
-65 to +150°C
260°C
Soldering Temperature
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
0
+3.15
+3.45
V
Refer to MAN05
MDS 3725 A
4
Revision 100803
Integrated Circuit Systems z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
MK3725
DUAL OUTPUT 3.3 VOLT VCXO
DC Electrical Characteristics
VDD=3.3 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
3.15
2.4
Typ.
Max.
Units
Operating Voltage
VDD
3.45
V
V
V
V
Output High Voltage
Output Low Voltage
V
I
I
I
= -12 mA
= 12 mA
= -4 mA
OH
OH
OL
OH
V
0.4
OL
Output High Voltage (CMOS
Level)
V
VDD-0.4
OH
Operating Supply Current
Short Circuit Current
IDD
No load
12
mA
mA
V
I
±50
OS
VIN, VCXO Control Voltage
Nominal output impedance
V
0
3.3
IA
Z
20
Ω
OUT
AC Electrical Characteristics
VDD=3.3 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Crystal Pullability
VCXO Gain
Symbol
Conditions
Min. Typ. Max. Units
F
0V< VIN < 3.3 V, Note 1
VIN = VDD/2 + 1 V, Note 1
+ 115
ppm
ppm/V
ns
P
120
1.0
1.0
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
t
20% to 80%, C =15 pF
L
OR
t
80% to 20%, C =15 pF
ns
OF
L
t
Measured at VDD/2,
45
55
%
D
C =15 pF
L
Maximum Output Jitter,
short term
t
C =15 pF
±60
ps
J
L
Note 1: External crystal device must conform with Pullable Crystal Specifications listed in MAN05
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
150
140
120
40
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 3725 A
5
Revision 100803
Integrated Circuit Systems z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
MK3725
DUAL OUTPUT 3.3 VOLT VCXO
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
4.80
3.80
.0532
.0040
.013
.0688
.0098
.020
E
H
.0075
.1890
.1497
.0098
.1968
.1574
INDEX
AREA
1.27 BASIC
0.050 BASIC
H
h
5.80
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
1
2
0.25
0.40
0°
L
D
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping
packaging
Tubes
Package
Temperature
MK3725S
MK3725
MK3725
8-pin SOIC
8-pin SOIC
0 to +70° C
0 to +70° C
MK3725STR
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 3725 A
6
Revision 100803
Integrated Circuit Systems z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com
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