MK3732-08RITR [ICSI]
ADSL Clock Source; ADSL时钟源
| 型号： | MK3732-08RITR |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | ADSL Clock Source |
| 文件： | 总4页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK3732-08
ADSL Clock Source
Description
Features
The MK3732-08 is a low cost, low jitter, high
performance VCXO and PLL clock synthesizer
designed to replace expensive discrete VCXOs and
multipliers. The on-chip Voltage Controlled Crystal
Oscillator (VCXO) accepts a 0 to 3.3 V input voltage to
cause the output clocks to vary by ±100 ppm. Using
ICS/MicroClock’s patented VCXO and analog/digital
Phase-Locked Loop (PLL) techniques, the device
uses an inexpensive 17.664 MHz or 24.576 MHz
pullable crystal input to produce one or two output
clocks.
• Packaged in 20 pin SSOP (QSOP)
• Replaces a VCXO and oscillator
• Uses an inexpensive pullable crystal
• On-chip patented VCXO with pull range of
230 ppm (±115 ppm) minimum
• VCXO tuning voltage of 0 to 3.3 V
• Advanced, low power, sub-micron CMOS process
• 3.3V operating voltage
• Available in industrial temperature range
ICS manufactures the largest variety of xDSL clock
synthesizers for all applications. Consult ICS to
eliminate VCXOs, crystals and oscillators from your
board.
Block Diagram
VDD
GND
3
S2:S0
Output
Buffer
CLK1
CLK2
REFEN
PD
Output
Buffer
PLL/Clock
Synthesis
Circuitry
VIN
Voltage
X1
Output
Buffer
Controlled
Crystal
17.664 MHz
or 24.576 MHz
pullable
REF
Oscillator
crystal
X2
OE
MDS 3732-08 C
1
Revision 091201
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • (408) 295-9818 fax • www.icst.com
MK3732-08
ADSL Clock Source
Pin Assignment
Clock Select Table
S2 S1 S0
Input
24.576 *
17.664
17.664
17.664
17.664
17.664
17.664
17.664
17.664
17.664
17.664
17.664
CLK1
2.208
20.00
20.19
70.66
70.66
58.88
35.328
2.208
20.19
4.04
CLK2
OFF
1
2
3
4
5
6
7
8
20
19
X1
NC
X2
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
M
1
OFF
NC
35.328
35.328
35.328
35.328
52.992
35.328
OFF
18
17
16
15
14
S1
VDD
VDD
VDD
VIN
0
REF
REFEN
S0
M
1
0
M
1
GND
GND
GND
PD
OE
13
12
S2
0
35.328
61.82
56.52
CLK2
9
M
1
35.328
35.328
11
CLK1
10
0=connect directly to GND; M=leave unconnected (floating);
1=connect directly to VDD
20 pin (150 mil) SSOP
* In this mode, 12.288 MHz is present on REF
Pin Descriptions
Number Name Type Description
1
2, 19
3, 4, 5
6
X1
NC
XI Crystal connection. Connect to a pullable crystal of 17.664 MHz or 24.576 MHz..
-
No Connect. Do not connect anything to this pin.
Power Supply. Connect to +3.3V.
VDD
VIN
GND
PD
P
VI Voltage Input to VCXO. Zero to 3.3V signal which controls the VCXO frequency.
Connect to ground.
I(PU) Power Down active low. Turns entire chip off, clocks stop low.
7, 8, 9
10
P
11
CLK1
CLK2
S2
O
O
Clock Output #1 per table above.
Clock Output #2 per table above.
12
13
I(PU) Select input #2. Selects outputs per table above.
I(PU) Output Enable. Tri-states outputs when low.
TI Select input #0. Selects outputs per table above.
14
OE
15
S0
16
REFEN I(PU) Reference Clock Enable. Enables REF Output when low. Connect to VDD for lowest jitter.
17
REF
S1
O
Reference Clock Output. This is the crystal oscillator output clock.
18
I(PU) Select input #1. Selects outputs per table above.
20
X2
XO Crystal connection. Connect to a pullable crystal of 17.664 MHz or 24.576 MHz.
Key: I(PU) = Input with internal pull-up resistor; TI = Tri-level Input; O = Output; P = Power Supply Connection;
VI = Analog Voltage Input; XI, XO = Crystal Pins.
External Components
The MK3732-08 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01µF should be connected between VDD and GND pins 3 and 7, pins 4 and 8, and pins 5 and 9, as close to the
MK3732-08 as possible. A series termination resistor of 33 W may be used for each clock output. The input crystal
must be connected as close to the chip as possible. The input crystal should be a fundamental mode, parallel
resonant, pullable, AT cut.
Consult ICS for recommended suppliers. IMPORTANT - Consult the Application Note MAN05 for layout guidelines.
MDS 3732-08 C
2
Revision 091201
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • (408) 295-9818 fax • www.icst.com
MK3732-08
ADSL Clock Source
Electrical Specifications
Parameter
Conditions
Minimum
Typical Maximum Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
VDD+0.5
70
V
Inputs and Clock Outputs
Ambient Operating Temperature
Referenced to GND
Commercial version
Industrial version
-0.5
0
V
°C
°C
°C
°C
-40
85
Soldering Temperature
Storage temperature
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 3.3V unless noted)
Core Operating Voltage, VDD
3.14
2
3.3
3.46
0.8
V
V
Input High Voltage, VIH, binary inputs
Input Low Voltage, VIL, binary inputs
V
Input High Voltage, VIH, trinary input
Input Low Voltage, VIL, trinary input
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
S0, pin 15
S0, pin 15
IOH=-12mA
IOL=12mA
IOH=-4mA
No Load
VDD-0.5
2.4
V
0.5
V
V
0.4
V
VDD -0.4
V
19
±50
5
mA
mA
pF
ppm
V
Each output
S2:S0, OE
Both clocks
Input Capacitance
Frequency synthesis error
VIN, VCXO control voltage
0
0
3.3
AC CHARACTERISTICS (VDD = 3.3V unless noted)
Input Crystal Frequency
17.664
2.208
24.576
70.656
1.5
MHz
MHz
ns
Output Clock Frequency
Output Clock Rise Time
0.8 to 2.0V
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
Maximum Absolute Short Term Jitter
Phase Noise, relative to carrier
Output pullability, note 2
At VDD/2
40
60
%
15 pF load at output
10 kHz offset, no REF
0V < VIN < 3.3V
±125
-115
ps
dBc/Hz
ppm
±115
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
affect device reliability.
2. With an ICS approved pullable crystal.
Pullable Crystal Specifications:
Correlation (load) Capacitance
C0/C1
14 pF
250 max
ESR
35 W max
Operating Temperature
Initial Accuracy
0 to 70 °C or -40 to 85 °C
±20 ppm
Temperature plus Aging Stability
±50 ppm
MDS 3732-08 C
3
Revision 091201
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • (408) 295-9818 fax • www.icst.com
MK3732-08
ADSL Clock Source
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
20 pin SSOP
Inches
Millimeters
Min Max
Symbol Min
Max
A
A1
b
0.053 0.069 1.35
0.004 0.010 0.10
0.008 0.012 0.20
0.007 0.010 0.19
0.337 0.344 8.56
1.75
0.25
0.30
0.25
8.74
E1
E
c
D
e
INDEX
AREA
.025 BSC
0.635 BSC
1
2
E
0.228 0.244 5.79
0.150 0.157 3.81
0.016 0.050 0.41
6.20
3.99
1.27
E1
L
D
A
A1
c
b
L
e
Ordering Information
Part/Order Number
MK3732-08R
Marking
Shipping packaging
tubes
Package
Temperature
0 to 70 °C
MK3732-08R
MK3732-08R
MK3732-08RI
MK3732-08RI
20 pin SSOP
20 pin SSOP
20 pin SSOP
20 pin SSOP
MK3732-08RTR
MK3732-08RI
tape and reel
tubes
0 to 70 °C
-40 to 85 °C
-40 to 85 °C
MK3732-08RITR
tape and reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems,
Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third
parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or
other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the
right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.
MDS 3732-08 C
4
Revision 091201
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • (408) 295-9818 fax • www.icst.com
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