PSICS9169-01 [ICSI]
Frequency Generator and Integrated Buffers for Intel Pentium and Pentium ProTM mPs; 频率发生器和缓冲器集成英特尔奔腾和Pentium ProTM MPS
| 型号： | PSICS9169-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator and Integrated Buffers for Intel Pentium and Pentium ProTM mPs |
| 文件： | 总10页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9169-01
FrequencyGeneratorandIntegratedBuffersforIntelPentium
and Pentium ProTM µP's
General Description
Features
The ICS9169-01 generates all clocks required for high speed
RISC or CISC microprocessor systems such as 486, Pentium/
Pentium Pro™, PowerPC™, etc. Four different reference
frequency multiplying factors are externally selectable with
smooth frequency transitions. These multiplying factors can
becustomizedforspecificapplications.Atestmodeisprovided
to drive all clocks directly.
•
Generates four processor, six bus, three 14.318 MHz
and one 48 MHz clock for ISA bus, audio, super I/O
and bus bridge devices
Supports the Intel MARS chip set
Synchronous clocks skew matched to 250ps window on
PCLKs and 500ps window on BCLKs
Test clock mode eases system design
Selectable multiplying ratios
Custom configurations available
Output frequency ranges to 100 MHz (depending on
option)
3.0V - 5.5 V supply range
28-pin SOIC and 28-pin SSOP (209-mil) packages
•
•
•
•
•
•
High drive BCLK outputs typically provide greater than 1V/
ns slew rate into 30pF loads. PCLK outputs typically provide
better than 1V/ns slew rate into 20pF loads while maintaining
50±5% duty cycle. The REF clock outputs typically provide
better than 0.5V/ns slew rates.
•
•
Applications
•
Ideal for high-speed RISC or CISC systems such as 486,
Pentium, PentiumPro, PowerPC, etc.
Block Diagram
PLL
CLOCK
GEN
48 MHz
X2
XTAL OSC
X1
REF(0:2)
OEN
FS0
FS1
PCLK(0:3)
BCLK(0:5)
SYNC
REG
PLL
CLOCK
GEN
Pentium is a trademark of Intel Corporation
PowerPC is a trademark of Motorola Corporation
9169-01RevE 08/28/98
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9169-01
Pin Configuration
Functionality
FS1
FS0
*VCO
X1, REF
PCLK(0:3)
(MHz)
(MHz)
14.31818
14.31818
14.31818
TCLK
0
0
1
1
0
1
0
1
230/33x X1
212/23x X1
176/21x X1
Test mode
50 (49.7)
66 (66.5)
60 (59.9)
TCLK/2
*VCO range is limited from 60 - 200 MHz
PCLK(0:3)
VCO/2
BCLK(0:5)
PCLK/2
48 MHz
48 MHz
TCLK/2
TCLK/2
TCLK/4
28 Pin SOIC
28 Pin SSOP
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 12.16 MHz crystal, nominally 14.31818
XTAL output which includes XTAL load capacitance.
2
X1
IN
3
X2
OUT
PWR
4, 11, 23
GND
Ground for logic, PCLK and fixed frequency output buffers.
GND
VDD
PWR
PWR
Ground for BCLK output buffers.
17
1, 8, 26
Power for logic, PCLK and fixed frequency output buffers.
14, 20
VDD
PWR
Power for BCLK output buffers.
Processor clock outputs which are a multiple of the input reference frequency
as shown in the table above.
6, 7, 9, 10
13, 12
PCLK(0:3)
FS(0:1)
OUT
IN
Frequency multiplier select pins. See table above. These inputs have internal
pull-up devices.
15, 16, 18
19, 21, 22
BCLK(0:5)
OEN
OUT
IN
Bus clock outputs are fixed at 1/2 the PCLK frequency.
5
OEN tristates all outputs when low. This input has an internal pull-up device.
24
48MHz
OUT
OUT
Fixed 48 MHz clock (with 14.318 MHz input).
REF is a buffered copy of the crystal oscillator or reference input clock,
nominally 14.31818 MHz.
28, 27, 25
REF(0:2)
Note 1: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being
supplied with 3.3 volts
2
ICS9169-01
Absolute Maximum Ratings
Supply Voltage.................................................................................................................................................................. 7.0 V
Logic Inputs............................................................................................................................ GND - 0.5 V to VDD + 0.5 V
.
Stresses a
stess spec
operation
periods m
Ambient Operating Temperature ........................................................................................................................... 0 to +70 C
Storage Temperature ......................................................................................................................................... -65 to +150 C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stess
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics at 3.3 V
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
VIL
VIH
IIL
-
-
0.2VDD
V
V
0.7VDD
-28.0
-5.0
-
-10.5
-
-
-
µA
µA
VIN = 0 V
IIH
VIN = VDD
5.0
VOL = 0.8 V;
for PCLKs & BCLKs
Output Low Current1
Output High Current1
IOL
IOH
30.0
-
47.0
-
mA
mA
VOL = 2.0 V; for
PCLKs & BCLKs
-66.0
-42.0
Output Low Current1
Output High Current1
Output Low Voltage1
IOL
IOH
VOL
VOL=0.8V; for fixed CLKs
25.0
38.0
-47.0
0.3
-
mA
mA
V
VOL=2.0V; for fixed CLKs
-
-
-30.0
0.4
IOL = 15 mA; for PCLKs & BCLKs
IOH = -30 mA;
for PCLKs & BCLKs
Output High Voltage1
Output Low Voltage1
Output High Voltage1
VOH
VOL
VOH
2.4
-
2.8
0.3
2.8
-
0.4
-
V
V
V
IOL=12.5mA; for fixed CLKs
IOH = -20mA;
for fixed CLKs
2.4
Supply Current
IDD
@ 66.5 MHz; all outputs unloaded
-
55
110
mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
ICS9169-01
Electrical Characteristics at 3.3 V
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
AC Characteristics
TEST CONDITIONS
PARAMETER
Rise Time1
SYMBOL
MIN
-
TYP
0.9
MAX
1.5
UNITS
ns
20pF load, 0.8 to 2.0V
PCLK & BCLK
Tr1
20pF load, 2.0 to 0.8V
PCLK & BCLK
20pF load, 20% to 80%
PCLK & BCLK
20pF load, 80% to 20%
PCLK & BCLK
Fall Time1
Rise Time1
Fall Time1
Duty Cycle1
Tf1
Tr2
Tf2
Dt
-
-
0.8
1.5
1.4
50
1.4
2.5
2.4
55
ns
ns
ns
%
-
20pF load
@ VOUT = 1.4 V
45
PCLK & BCLK Clocks;
Load=20pF,
Jitter, One Sigma1
Jitter, Absolute1
Tj1s1
Tjab1
-
50
-
150
250
ps
ps
FOUT >25 MHz
PCLK & BCLK Clocks;
Load=20pF,
-250
FOUT >25 MHz
Jitter, One Sigma1
Jitter, Absolute1
Input Frequency1
Tj1s2
Tjab2
Fj
Fixed CLK; Load=20pF
Fixed CLK; Load=20pF
-
1
2
3
5
%
%
-5
12.0
14.318
16.0
MHz
Logic Input
CIN
Logic input pins
X1, X2 pins
-
-
5
-
-
pF
pF
Capacitance1
Crystal Oscillator
Capacitance1
CINX
18
From VDD=1.6V to 1st
crossing of 66.5 MHz VDD
supply ramp < 40 ms
Power-on Time1
ton
-
2.5
4.5
ms
Frequency Settling
Time1
From 1st crossing of
ts
-
-
2.0
4.0
ms
ps
acquisition to < 1% settling
Clock Skew
Window1
PCLK to PCLK;
Load=20pF; @1.4V
Tsk1
150
250
Clock Skew
Window1
BCLK to BCLK;
Tsk2
Tsk3
-
300
2.6
500
5
ps
ns
Load=20pF; @1.4V
Clock Skew
Window1
PCLK to BCLK;
Load=20pF; @1.4V
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9169-01
Electrical Characteristics at 5.0 V
VDD = 4.5 - 5.5 V, TA = 0 - 70 oC unless otherwise stated
DC Characteristics
TEST CONDITIONS
PARAMETER
SYMBOL
VIL
MIN
-
TYP
-
MAX
0.8
UNITS
V
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
VIH
IIL
2.4
-45
-5.0
-
-15
-
-
-
V
µA
µA
VIN = 0 V
IIH
VIN = VDD
5.0
VOL = 0.8 V;
for PCLKs & BCLKs
VOL = 2.0 V;
Output Low Current1
IOL
IOH
36.0
62.0
-
mA
Output High Current1
Output Low Current1
Output High Current1
-
30.0
-
-152
50.0
-90.0
-
mA
mA
mA
for PCLKs & BCLKs
IOL
IOH
VOL = 0.8V; for fixed CLKs
VOL=2.0V; for fixed CLKs
-110.0
-65.0
IOL = 20 mA;
for PCLKs & BCLKs
IOH = -70 mA;
for PCLKs & BCLKs
IOL = 15mA; for fixed CLKs
Output Low Voltage1
VOL
VOH
-
0.25
4.0
0.4
-
V
V
Output High Voltage1
2.4
Output Low Voltage1
Output High Voltage1
VOL
VOH
-
0.2
4.7
0.4
-
V
V
IOH=-50mA; for fixed CLKs
2.4
Supply Current1
IDD
@ 66.5 MHz; all outputs unloaded
-
80.0
160.0
mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
ICS9169-01
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1) All clock outputs should have series
terminating resistor. Not shown in
all places to improve readibility of
diagram.
2) 47 ohm / 56pf RC termination should
be used at 50MHz and higher clock
loads.
3) Optional crystal load capacitors are
recommended.
CapacitorValues:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
ConnectionstoVDD:
6
ICS9169-01
Electrical Characteristics at 5.0 V
VDD = 4.5 - 5.5 V, TA = 0 - 70 oC unless otherwise stated
AC Characteristics
TEST CONDITIONS
20pF load, 0.8 to 2.0V
PARAMETER
Rise Time1
SYMBOL
MIN
-
TYP
0.55
MAX
0.95
UNITS
ns
Tr1
PCLK & BCLK
20pF load, 2.0 to 0.8V
PCLK & BCLK
Fall Time1
Rise Time1
Fall Time1
Duty Cycle1
Duty Cycle1
Tf1
Tr2
Tf2
Dt1
Dt2
-
-
0.52
1.2
1.1
50
0.90
2.1
2.0
55
ns
ns
ns
%
%
20pF load, 20% to 80%
PCLK & BCLK
20pF load, 80% to 20%
PCLK & BCLK
-
20pF load @ VOUT = 50% of VDD
20pF load @ VOUT = 1.4 V
45
50
55
60
PCLK & BCLK Clocks; Load=20pF;
R=33 Ω FOUT > 25 MHz
Jitter, One Sigma1
Tj1s1
-
50
150
ps
PCLK & BCLK Clocks; Load=20pF;
R=33 Ω FOUT > 25 MHz
Jitter, Absolute1
Tjab1
Tjis2
-250
-
-
250
3
ps
%
Fixed CLK; Load=20pF
R=33 Ω
Jitter, One Sigma1
1
Fixed CLK; Load=20pF
R=33 Ω
Jitter, Absolute1
Tjab2
Fi
-5
12.0
-
2
14.318
5
5
16.0
-
%
MHz
pF
Input Frequency1
Logic Input Capacitance1
CIN
Logic input pins
X1, X2 pins
Crystal Oscillator
Capacitance1
CINX
ton
-
-
18
-
pF
ms
From V=1.6V to 1st crossing of 66.5
MHz VDD supply ramp < 40 ms
Power-on Time1
2.5
4.5
From 1st crossing of acquisition to
< 1% settling
Frequency Settling Time1
ts
-
2.0
4.0
ms
PCLK to PCLK;
Clock Skew Window1
Clock Skew Window1
Clock Skew Window1
Tsk1
Tsk2
Tsk3
-
-
150
300
2.6
250
500
5
ps
ps
ns
Load=20pF; @1.4V
BCLK to BCLK;
Load=20pF; @1.4V
PCLK to BCLK;
Load=20pF; @1.4V
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
7
ICS9169-01
L ± 0.008
0.018
5˚ Typ. ± 5
5˚ Typ.
0.029 Typ.
0.047R
.0.328 ± 0.010
0.296 ± 0.005
0.406 ± 0.010
0.015
x 45˚
Pin 1
0.101
± 0.010
0.092
± 0.005
0.020
0.010
0.041
± 0.003
LEAD COUNT
DIMENSION L
28L
0.704
0.050
Pitch typ.
0.008
± 0.006
SOIC Packaggee
Ordering Information
ICS9169M-01
Example:
ICS XXXX M-PPP
Pattern Number (2 or 3-digit number for parts with ROM code pattern)
Package Type
M = SOIC
Device Type (consists of 3 or 4-digit numbers)
Prefix
ICS, AV=Standard Device
8
ICS9169-01
D/2
1.14
1.14
2.36 DIA. PIN
E/2
H
TOP VIEW
BOTTOM VIEW
D
SEATING PLANE
A
2
C
A
SEE
DETAIL A
A
1
C
e
B
E
SIDE VIEW
END VIEW
PARTING
LINE
α
DETAIL A
L
SSOP Package
9
ICS9169-01
Package dimensions - SSOP package
SYMBOL
COMMON DIMENSIONS
NOTE
4
D
6
NOTE VARIATIONS
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
A
0.68
0.73
0.78
AA
AB
0.239
0.239
0.244
0.244
0.249
0.249
14
16
0.002
0.005
0.008
A
B
0.066
0.010
0.068
0.012
0.070
0.015
AC
AD
0.278
0.318
0.284
0.323
0.289
0.328
20
24
C
D
E
0.005
0.006
See Variations
0.209
0.008
AE
0.397
0.397
0.402
0.402
0.407
0.407
28
30
4
4
AF
0.205
0.212
e
0.0256 BSC
0.307
H
L
N
0.301
0.022
0.311
0.037
0.030
5
6
See Variations
0
4
8
Table dimensions in inches
Ordering Information
ICS9169F-01
Example:
ICS XXXX M-PPP
Pattern Number (2 or 3-digit number for parts with ROM code pattern)
Package Type
F=SSOP
Device Type (consists of 3 or 4-digit numbers)
Prefix
ICS, AV=Standard Device
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
10
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