1AI01
更新时间：2024-09-18 08:45:11
品牌：ICSI
描述：FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR
概述
数据手册1AI01 概述
FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V 125MHZ LVPECL CLOCK GENERATOR FEMTOCLOCKS -TM CRYSTAL - TO- 3.3V ， 2.5V 125MHZ LVPECL时钟发生器
1AI01 数据手册
通过下载1AI01数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS843021I-01 is a Gigabit Ethernet Clock • 1 differential 3.3V LVPECL output
ICS
Generator and a member of the HiPerClocksTM
family of high performance devices from ICS.The
ICS843021I-01 uses a 25MHz crystal to
synthesize 125MHz. The ICS843021I-01 has
• Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
HiPerClockS™
• Output frequency: 125MHz, using a 25MHz crystal
• VCO range: 490MHz - 640MHz
excellent phase jitter performance, over the 1.875MHz – 20MHz
integration range. The ICS843021I-01 is packaged in a small
8-pin TSSOP, making it ideal for use in systems with limited
board space.
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical) (for 3.3V)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
OE
VCC
XTAL_OUT
XTAL_IN
VEE
Q0
1
2
3
4
8
7
6
5
nQ0
VCC
OE
25MHz
XTAL_IN
Q0
÷4
(fixed)
Phase
Detector
OSC
VCO
nQ0
XTAL_OUT
ICS843021I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
÷20
(fixed)
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
1
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Power
Description
1, 6
VCC
Core supply pin.
XTAL_OUT,
XTAL_IN
2, 3
4
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Negative supply pin.
VEE
Power
Active high output enable. When logic HIGH, the outputs are enabled and
Pullup active. When logic LOW, the outputs are disabled and are in a high
impedance state. LVCMOS/LVTTL interface levels.
5
OE
Input
7, 8
nQ0, Q0
Output
Differential clock outputs. LVPECL interface levels.
Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
RPULLUP
51
KΩ
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
2
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA= -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
IEE
Core Supply Voltage
3.465
3.465
V
V
Analog Supply Voltage
Power Supply Current
3.135
3.3
60
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA= -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VCC
VCCA
IEE
Core Supply Voltage
2.625
2.625
V
V
Analog Supply Voltage
Power Supply Current
2.375
2.5
57
mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA= -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
V
V
Input Low Voltage
-0.3
0.8
5
Input High Current OE
Input Low Current OE
VCC = VIN = 3.465V or 2.5V
µA
µA
IIL
VCC = 3.465V or 2.5V, VIN = 0V
-150
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA= -40°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
3
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA= -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
MHz
RMS Phase Jitter (Random);
NOTE 1
Intergration Range:
1.875MHz - 20MHz
tjit(Ø)
0.41
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plot following this section.
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA= -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
125
MHz
RMS Phase Jitter (Random);
NOTE 1
Intergration Range:
1.875MHz - 20MHz
tjit(Ø)
0.42
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plot following this section.
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
4
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
TYPICAL PHASE NOISE AT 125MHZ (3.3V OR 2.5V)
0
-10
-20
-30
-40
-50
-60
Gigabit Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz (3.3V) = 0.41ps (typical)
1.875MHz to 20MHz (2.5V) = 0.42ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Gigabit Ethernet Filter to raw data
100
1k
10k
100k
OFFSET FREQUENCY (HZ)
1M
10M
100M
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
5
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
2V
SCOPE
SCOPE
VCC
VCC
Qx
Qx
LVPECL
VEE
LVPECL
VEE
nQx
nQx
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
Phase Noise Mask
Clock
20ꢀ
Outputs
tR
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
nQ0
Q0
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
6
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
The ICS843021I-01 has been characterized with 18pF parallel resonant crystal and were chosen to minimize the ppm error.
resonant crystals. The capacitor values, C1 and C2, shown in The optimum C1 and C2 values can be slightly adjusted for
Figure 1 below were determined using a 25MHz, 18pF parallel different board layouts.
XTAL_OUT
C1
27p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 1. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Z
o = 50Ω
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Z
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
7
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
8
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
APPLICATION SCHEMATIC
Figure 4 shows an example of ICS843021I-01 application two termination examples are shown in this schematic.
schematic. In this example, the device is operated at Additional termination approaches are shown in the LVPECL
Termination Application Note.
VCC = 3.3V. The decoupling capacitor should be located as
close as possible to the power pin. The input is driven by a
25MHz quartz crystal. For the LVPECL output drivers, only
VCC = 3.3V
3.3V
C2
27pF
R3
133
R5
133
U1
Zo = 50 Ohm
1
8
7
6
5
VCC
Q0
nQO
Vcc
OE
X1
25MHz
18pF
2
3
4
XTAL_OUT
XTAL_I N
VEE
+
-
OE
Zo = 50 Ohm
843021I-01
C1
27pF
R4
R6
82.5
82.5
VCC
C3
10uF
C4
.1uF
C5
.1uF
Zo = 50
Zo = 50
+
-
R2
50
R1
50
R3
50
Optional Termination
FIGURE 4. ICS843021I-01 SCHEMATIC EXAMPLE
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
9
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843021I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843021I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 60mA = 207.9mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 207.9mW + 30mW = 237.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.238W * 90.5°C/W = 106.5°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
10
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mWL
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
11
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS843021I-01 is: 1765
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
12
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
13
PRELIMINARY
ICS843021I-01
Integrated
Circuit
Systems, Inc.
F
EMTO
C
LOCKS™ CRYSTAL
-
TO-3.3V, 2.5V
125MH
Z
LVPECL CLOCK
GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS843021AGI-01
ICS843021AGI-01T
Marking
Package
Count
100 per tube
2500
Temperature
-40°C to 85°C
-40°C to 85°C
1AI01
1AI01
8 lead TSSOP
8 lead TSSOP on Tape and Reel
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
843021AGI-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
14
1AI01 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 1AM | AVICTEK | SOT-23 Plastic-Encapsulate Transistors | 获取价格 |
|
| 1AM-NCC-12 | ETC | MOTOR LUFT NABENMONT LINKSDR 4 FLUEG | 获取价格 |
|
| 1AM-NCW-14 | ETC | MOTOR LUFT NABENMONT RECHTSDR 4 FLUEG | 获取价格 |
|
| 1AM-NRV-39A | ETC | MOTOR LUFT NABENMONT UMKEHRBAR 4 FLUEG | 获取价格 |
|
| 1AM-NRV-56-GR11 | ETC | MOTOR GETR FRONTMONT UMKEHRBAR 4 FLUEG | 获取价格 |
|
| 1AM-NRV-60-GR11 | ETC | MOTOR GETR FRONTMONT UMKEHRBAR 8 FLUEG | 获取价格 |
|
| 1APK6800M12.5X25 | RUBYCON | CAPACITOR, ALUMINUM ELECTROLYTIC, NON SOLID, POLARIZED, 10V, 6800uF, THROUGH HOLE MOUNT, RADIAL LEADED | 获取价格 |
|
| 1APX3300M10X20 | RUBYCON | CAPACITOR, ALUMINUM ELECTROLYTIC, NON SOLID, POLARIZED, 10V, 3300uF, THROUGH HOLE MOUNT, RADIAL LEADED | 获取价格 |
|
| 1APX6800M16X25 | RUBYCON | CAPACITOR, ALUMINUM ELECTROLYTIC, NON SOLID, POLARIZED, 10V, 6800uF, THROUGH HOLE MOUNT, RADIAL LEADED | 获取价格 |
|
| 1AS12VDC.9D | CIT | Low coil power consumption | 获取价格 |
|
1AI01 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
