ICS4231M-03T [ICSI]
Low EMI Clock Generator; 低EMI时钟发生器
| 型号： | ICS4231M-03T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low EMI Clock Generator |
| 文件： | 总6页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS4231-03
Low EMI Clock Generator
Description
Features
The ICS4231-03 generates a low EMI output clock
from a clock or crystal input. The device uses ICS’
proprietary mix of analog and digital Phase Locked
Loop (PLL) technology to spread the frequency
spectrum of the output, thereby reducing the frequency
amplitude peaks by several dB.
• Pin and function compatible to Cypress W42C31-03
• Packaged in 8-pin SOIC (Pb free available)
• Provides a spread spectrum output clock
• Accepts a clock or crystal input and provides same
frequency dithered output
• Input clock frequency of 10 to 33 MHz
The ICS4231-03 offers four different center and down
spread selections. Refer to the MK1714-01/02 for the
widest selection of input frequencies and multipliers.
• Peak reduction by 8dB - 14dB typical on 3rd - 19th
odd harmonics
• Spread percentage selections of ±1.875%, ±1.0%,
ICS offers a complete line of EMI reducing clock
generators. Consult us when you need to remove
crystals and oscillators from your board.
and -2.0%
• Operating voltage of 5V
• Advanced, low-power CMOS process
Block Diagram
VDD
FS1:0
OE#
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
CLK
X1/CLKIN
Clock Buffer/
Crystal
Oscillator
X2
GND
MDS 4231-03 A
1
Revision 110404
Integrated Circuit Systems● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS4231-03
LOW EMI CLOCK GENERATOR
Pin Assignment
Output Enable Function Table
OE#
(Pin 8)
Output Status
X1/CLKIN
X2
1
2
3
4
8
7
6
5
OE#
FS1
0
1
Running
Tri-state
GND
FS0
VDD
CLKOUT
0 = connect to GND
1 = connect directly to VDD
8 pin (150 mil) SOIC
Note: OE# pin has an internal pull-down resistor
Frequency Range and Spread Table
FS1
FS0
Clock Input
Frequency
(MHz)
Crystal Input
Frequency
(MHz)
Spread Amount
(Pin 7) (Pin 4)
0
0
1
1
0
1
0
1
10-20
10-20
20-33
20-33
10-20
10-20
20-25
20-25
±1.875%
±1.0%
±1.875%
-2.0%
Note: FS1:0 have internal pull-up resistors
Pin Descriptions
Pin
Pin
Pin Type
Pin Description
Number
Name
1
2
3
4
X1/CLKIN
X2
Input
Crystal or Clock Input.
Output Crystal output. Float for a clock input.
GND
FS0
Power
Input
Connect to ground.
Select pin for input frequency and spread amount. See table above. Internal
pull up resistor.
5
6
7
CLKOUT
VDD
Output Spread spectrum clock output per table above.
Power
Input
Connect to 5V.
FS1
Select pin for input frequency and spread amount. See table above. Internal
pull up resistor.
8
OE#
Input
Output Enable. Active Low. See table above. Internal pull-down resistor.
MDS 4231-03 A
2
Revision 110404
Integrated Circuit Systems● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS4231-03
LOW EMI CLOCK GENERATOR
value of these capacitors is given by the following
equation:
External Components
The ICS4231-03 requires a minimum number of
external components for proper operation.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 6 and 3, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
Series Termination Resistor
2) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock output.
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50Ω trace (a commonly used
trace impedance) place a 33Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS4231-03. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS4231-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7V
-0.5V to VDD+0.5V
0 to +70°C
-65 to +150°C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
MDS 4231-03 A
3
Revision 110404
Integrated Circuit Systems● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS4231-03
LOW EMI CLOCK GENERATOR
DC Electrical Characteristics
Unless stated otherwise, VDD = 5V, ±10%, Ambient Temperature 0 to +70°C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
Conditions
Min.
Typ.
5
Max.
5.5
Units
V
4.5
IDD
No load, at 3.3V
18
32
mA
V
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
Load Capacitance
V
0.7VDD
2.5
IH
V
0.15VDD
V
IL
V
I
I
= -24mA
= 24mA
V
OH
OH
V
0.4
7
V
OL
OL
C
All pins except X1, X2
5
pF
pF
IN
X1, X2, as seen by the
xtal, Note 1
17
Output Impedance
Input Pull-Up Resistor
Power-Up Time
Rout
20
Ω
500
KΩ
ms
First locked clock
cycle after Power
Good
5
Note 1: Pins X1 and X2 each have 34 pF capacitance. When used with a crystal, the total combined
capacitance as seen by the crystal is 17 pF. If driving X1 with a clock input, the load capacitance will be
34 pF.
AC Electrical Characteristics
Unless stated otherwise, VDD = 5V±10%, Ambient Temperature 0 to +70° C, C =15pf
L
Parameter
Symbol
Conditions
Min.
10
Typ. Max. Units
Input Frequency
Input Clock
33
33
60
55
5
MHz
MHz
%
Output Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Output Rise Time
Output Fall Time
Jitter
10
Time above VDD/2
Note 1
40
45
50
2
%
t
0.8 to 2.4V, note 1
2.4 to 0.8V, note 1
cycle-to-cycle
ns
OR
t
2
5
ns
OF
300
ps
Harmonic Reduction
8
dB
Note 1: Measured with 15pF load
MDS 4231-03 A
4
Revision 110404
Integrated Circuit Systems● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS4231-03
LOW EMI CLOCK GENERATOR
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
150
140
120
40
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Marking Diagram
8
5
4231M-03
######
YYWW
1
4
Marking Diagram (Pb free)
8
5
4231M03L
######
YYWW
1
4
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week
that the part was assembled.
3. “L” denotes Pb (lead) free package.
4. Bottom marking: country of origin.
MDS 4231-03 A
5
Revision 110404
Integrated Circuit Systems● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
ICS4231-03
LOW EMI CLOCK GENERATOR
Package Outline and Package Dimensions (8 pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
1.35
0.10
0.33
0.19
4.80
3.80
.0532
.0040
.013
.0075
.1890
.1497
.0688
.0098
.020
.0098
.1968
.1574
E
H
INDEX
AREA
1.27 BASIC
0.050 BASIC
1
2
H
h
L
5.80
0.25
0.40
0°
6.20
.2284
.010
.016
0°
.2440
.020
.050
8°
0.50
1.27
8°
D
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping
packaging
Tubes
Tape and Reel
Tubes
Package
Temperature
ICS4231M-03
ICS4231M-03T
ICS4231M-03LF
ICS4231M-03LFT
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
see page 5
Tape and Reel
“LF” denotes Pb free packaging.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 4231-03 A
6
Revision 110404
Integrated Circuit Systems● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201● www.icst.com
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