M902-01I187.5000 [ICSI]

VCSO BASED GBE CLOCK GENERATOR; VCSO基于GBE时钟发生器
M902-01I187.5000
型号: M902-01I187.5000
厂家: INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述:

VCSO BASED GBE CLOCK GENERATOR
VCSO基于GBE时钟发生器

时钟发生器
文件: 总8页 (文件大小:317K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
P r o d u c t D a t a S h e e t  
Integrated  
Circuit  
Systems, Inc.  
M902-01  
VCSO BASED GBE CLOCK GENERATOR  
GENERAL DESCRIPTION  
PIN ASSIGNMENT (9 x 9 mm SMT)  
The M902-01 is a PLL (Phase Locked Loop) based  
clock generator that uses an  
internal VCSO (Voltage Controlled  
SAW Oscillator) to produce a very  
low jitter output clock. It is ideal for  
Gigabit Ethernet. The output clock  
(frequency of 156.25 or 187.50MHz  
for example) is provided from two  
XTAL_2  
NC  
NC  
NC  
28  
29  
30  
31  
32  
33  
34  
35  
36  
18  
17  
16  
15  
14  
13  
12  
11  
10  
LVPECL clock output pairs. (Specify frequency at time  
of order.) The accuracy of the output frequency is  
assured by the internal PLL, which phase-locks the  
internal VCSO to the reference input frequency (25 or  
30MHz for example). The input reference can either  
be an external crystal, utilizing the internal crystal  
oscillator, or a stable external clock source such as  
a packaged crystal oscillator.  
NC  
NC  
NC  
VCC  
DNC  
DNC  
DNC  
nFOUT1  
FOUT1  
GND  
nFOUT0  
FOUT0  
VCC  
M902-01  
( T o p V i e w )  
GND  
FEATURES  
Output clock frequency from 125MHz to 190MHz  
(Consult factory for frequency availability)  
Figure 1: Pin Assignment  
Two identical LVPECL output pairs  
Integrated SAW (surface acoustic wave) delay line  
Low jitter 0.5ps rms (over 12kHz-20MHz)  
Ideal for Gigabit Ethernet clock reference  
Output-to-output skew < 100ps  
Example Output Frequency Configurations  
Ref Clock  
Frequency  
(MHz)  
Output  
Frequency1  
(MHz)  
PLL  
Application  
Ratio  
External XTAL or LVCMOS reference input  
Selectable external feed-through clock input  
STOP clock control (Logic 1 stops output clocks)  
Industrial temperature grade available  
Single 3.3V power supply  
20  
25  
30  
125.00  
156.25  
187.50  
GbE  
25/4  
10GbE  
12GbE  
Table 1: Example Output Frequency Configurations  
Note 1: Specify output clock frequency at time of order  
Small 9 x 9 mm SMT (surface mount) package  
SIMPLIFIED BLOCK DIAGRAM  
M902-01  
VSCO  
External  
Crystal  
Frequency  
Multiplying  
PLL  
XTAL  
OSC  
LVPECL  
Output  
Clock Pairs  
(e.g., 156.25  
O
or  
Divider  
Reference  
Clock Input  
(e.g., 25 or 30MHz)  
1
or 187.50MHz)  
External  
Loop Filter  
External External  
Output  
Clock STOP  
Control  
Clock  
Clock  
Input  
Select  
Figure 2: Simplified Block Diagram  
M902-01 Datasheet Rev 2.1  
Revised 24Jun2004  
M902-01 VCSO Based GbE Clock Generator  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
M902-01  
Integrated  
Circuit  
Systems, Inc.  
VCSO BASED  
GB  
E CLOCK  
G
ENERATOR  
P r o d u c t D a t a S h e e t  
DETAILED BLOCK DIAGRAM  
RLOOP CLOOP  
RPOST  
External  
Loop Filter  
Components  
CPOST  
CPOST  
RLOOP CLOOP  
nOP_IN OP_OUT  
RPOST  
M902-01  
OP_IN  
RIN  
nOP_OUT  
nVC  
VC  
Phase  
Detector  
SAW Delay Line  
XTAL_1 / REF_IN  
XTAL  
OSC  
R Divider  
R = 4  
XTAL_2  
RIN  
Loop Filter  
Amplifier  
Phase  
Shifter  
VCSO  
M Divider  
M = 25  
O
1
FOUT1  
nFOUT1  
Phase Locked Loop (PLL)  
EXT_CLK  
FOUT0  
nFOUT0  
EN_EXT_CLK  
STOP  
Figure 3: Detailed Block Diagram  
PIN DESCRIPTIONS  
Number Name  
1, 2, 3, 10, 14, 26 GND  
I/O  
Ground  
Configuration  
Description  
Power supply ground connections.  
4
9
OP_IN  
nOP_IN  
Input  
External loop filter connections. See Figure 5,  
External Loop Filter, on pg. 4.  
5
8
nOP_OUT  
OP_OUT  
Output  
6
7
nVC  
VC  
Input  
11, 19, 33  
VCC  
Power  
Power supply connection, connect to +3.3V.  
12  
13  
FOUT0  
nFOUT0  
Clock output pairs, differential LVPECL output  
(156.25 MHz for the M902-01-156.2500)  
Output  
No internal terminator  
15  
16  
FOUT1  
nFOUT1  
17, 18  
20, 21, 22  
29, 30, 31, 32  
NC  
No internal connection  
Logic 1 enables the EXT_CLK input.  
Use Logic 0 for normal operation.  
1
23  
24  
25  
EN_EXT_CLK  
EXT_CLK  
STOP  
Input  
Input  
Input  
Internal pull-down resistor  
External clock feed-through: 0 to 200 MHz  
Logic 1 stops clock outputs.  
Use Logic 0 for normal operation.  
1
Internal pull-down resistor  
External crystal connection. Also accepts  
LVCMOS/LVTTL compatible clock source.  
27  
XTAL_1 / REF_IN  
Input  
Input  
External crystal connection. Leave unconnected  
when driving pin 27 with external clock reference.  
28  
XTAL_2  
DNC  
34, 35, 36  
Do Not Connect.  
Table 2: Pin Descriptions  
Note 1: For typical value of internal pull-down resistor, see DC Characteristics, Pull-down on pg. 6.  
M902-01 Datasheet Rev 2.1  
2 of 8  
Revised 24Jun2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
M902-01  
Integrated  
Circuit  
Systems, Inc.  
VCSO BASED  
GB  
E CLOCK  
G
ENERATOR  
P r o d u c t D a t a S h e e t  
The PLL  
FUNCTIONAL DESCRIPTION  
The PLL (Phase Locked Loop) includes the phase  
detector, the VCSO, a feedback divider (labeled  
“M Divider”), and a reference divider (“R Divider”).  
The M902-01 is a PLL (Phase Locked Loop) based  
clock generator that generates output clocks  
synchronized to an input reference clock.  
The feedback divider divides the VCSO output  
frequency by a fixed value “M” to match the reference  
frequency provided to the phase detector by the  
reference divider.  
The M902-01 combines the flexibility of a VCSO  
(Voltage Controlled SAW Oscillator) with the stability of  
a crystal oscillator.  
Input Reference  
By controlling the frequency and phase of the VCSO,  
the phase detector precisely locks the frequency and  
phase of the feedback divider output to that of the  
reference divider output.  
The input reference can either be an external, discrete  
crystal or a stable external clock source such as a  
packaged (temperature-compensated) crystal  
oscillator.  
The relationship between the VCSO output frequency,  
the M Divider, the R Divider and the input reference  
frequency is defined as follows:  
If an external crystal is used with the on-chip crystal  
oscillator circuit (XTAL OSC), the external crystal  
should be a parallel-resonant, fundamental mode  
crystal. Apply it to the XTAL_1 / REF_IN and XTAL_2 input  
pins. External crystal load trim capacitors are also  
required. (See “Crystal Specifications” on pg. 4.)  
M
R
----  
Fvcso = Fxtal ×  
For the M902-01-156.2500 (see “Ordering Information” on pg. 8):  
VCSO output frequency = 156.25MHz  
If an external LVCMOS/LVTTL clock source is used,  
Input reference frequency = 25MHz  
apply it to the XTAL_1 / REF_IN input pin.  
M=25  
R= 4  
In either case, the reference clock is supplied to the  
phase detector of the PLL. The M902-01 includes a  
reference divider that divides the input reference  
frequency by a fixed value “R” and provides the result to  
the phase detector.  
Therefore, for the M902-01-156.2500:  
25  
---------  
4
156.25MHz = 25MHz 
×  
The EX_CLK pin is available for a clock feed-through  
mode for testing. See “External Clock Feed-through”  
on pg. 3.  
M
----  
The product of the input crystal frequency and  
falls within the lock range of the VCSO.  
R
External Clock Feed-through  
The EXT_CLK pin provides an input for an external  
single-ended clock that directly drives the LVPECL  
clock outputs. This pin is intended for system debugging  
and performance evaluation..  
EN_EXT_CLK Logic 1 enables the EXT_CLK input.  
Use Logic 0 for normal operation.  
EXT_CLK  
Apply an external LVCMOS/LVTTL clock source  
for 0 to 200 MHz feed-through operation.  
Leave inactive for normal operation.  
1
Note 1: In applications where EXT_CLK is active while the SAW PLL  
signal path is enabled, it is necessary to gate the EXT_CLK to  
minimize jitter in the LVPECL output pairs. See the PCB Design  
Guidelines for ICS SAW PLLs application note at  
www.icst.com/products/appnotes/M000-AN-001.PCBdesign.pdf  
STOP Clock  
The STOP pin puts the output clock into a static condition.  
Logic 1 Output clocks are static  
Logic 0 Output clocks enabled for normal operation  
M902-01 Datasheet Rev 2.1  
3 of 8  
Revised 24Jun2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
M902-01  
Integrated  
Circuit  
Systems, Inc.  
VCSO BASED  
GB  
E CLOCK  
G
ENERATOR  
P r o d u c t D a t a S h e e t  
External Loop Filter  
APPLICATION INFORMATION  
This section includes information on the optional  
external crystal and on the external loop filter.  
To provide stable PLL operation, and thereby a low jitter  
output clock, the M902-01 requires the use of an  
external loop filter. This is provided via the provided  
filter pins (see Figure 5).  
The subsections on the loop filter provide example  
component values and also briefly describe the SAW  
PLL simulator tool and additional application  
information available at www.icst.com.  
RLOOP CLOOP  
RPOST  
CPOST  
CPOST  
External Crystal Specifications  
If an external crystal is used with the on-chip crystal  
oscillator circuit (XTAL OSC), the external crystal  
should have the following general specifications:  
RLOOP CLOOP  
nOP_IN OP_OUT  
RPOST  
OP_IN  
nOP_OUT  
nVC  
VC  
Crystal Specifications  
4
9
8
5
6
7
Parameter  
Crystal Type  
Min Typ Max Unit  
AT-cut quartz  
Figure 5: External Loop Filter  
The loop filter is implemented as a differential circuit  
to minimize system noise interference. Due to the  
differential signal path design, the implementation  
requires two identical complementary RC filters as  
shown here. See Table 4, External Loop Filter  
Component Values, below.  
Fundamental  
Mode of Oscillation  
Nominal Frequency Range  
16  
40  
f
MHz  
ppm  
0
1
f/f  
Frequency Tolerance @  
+
25 o  
C
±15  
±50  
±5  
0
f/fC / TA Frequency Stability -40 to +85 o  
C
ppm  
1
1
f/f / y Aging, per year (first) @  
+
25 o  
C
ppm  
0
External Loop Filter Component Values  
ESR  
CS  
50  
7
Equivalent Series Resistance  
Shunt Capacitance  
PLLBandwidth Damping R loop C loop R post C post  
pF  
(kHz)  
Factor  
(k)  
(µF)  
(k)  
(pF)  
Spurious Response (non-harmonic)  
-40 dBc  
0.5  
1.5 1  
2.1 2  
3.0  
3.3  
1.1  
4.5  
4.2  
1.5  
4.7  
4.70  
1.00  
0.10  
0.10  
0.03  
20  
10  
10  
20  
20  
150  
150  
150  
270  
120  
CL  
Load Capacitance,  
parallel load resonant  
16  
32  
pF  
4.7  
0.1  
1.0  
P
Drive Level  
mW  
0
6.4  
20.0  
Table 3: External Loop Filter Component Values  
3
33.0  
10.6  
Note 1: These frequency tolerance specifications are suitable for  
Table 4: External Loop Filter Component Values  
a ±100 ppm clock output frequency requirement.  
Note 1: Optimum loop bandwidth when using an external reference  
crystal. Will help to attenuate interference on the crystal’s  
sinusoidal clock waveform and therefore will minimize  
device output clock jitter.  
Note 2: Alternative loop filter setting when using an external refer-  
ence crystal. Smaller C loop lowers loop damping factor with  
negligible increase in output jitter.  
The external crystal will be applied to the XTAL_1 / REF_IN  
and XTAL_2 input pins. External crystal load capacitors  
are also required.  
Recommended External Crystal Configuration  
Note 3: Optimum loop bandwidth when using an external reference  
crystal oscillator. The square wave clock reference does not  
require as much jitter attenuation, which allows for a wider  
loop bandwidth and improved system noise tolerance.  
M902-01  
M9xx-0x  
XTAL_1 / REF_IN  
XTAL_2  
C1  
C2  
Refer to the M902-01 product web page at  
www.icst.com/products/summary/m902-01.htm for  
additional product information.  
XTAL OSC  
XTAL  
Figure 4: Recommended External Crystal Configuration  
XTAL= 25 or 30 MHz, Load Capacitance Specification = 18 pF  
C1  
C2  
=
=
27 pF  
33 pF  
External load capacitors C1 and C2 present a load of 15 pf  
to the crystal (they are seen in series by the crystal through  
the common ground connection). With the additional of PCB  
trace capacitance and M902-01 input capacitance, the total  
load to the crystal is about 18 pf.  
M902-01 Datasheet Rev 2.1  
4 of 8  
Revised 24Jun2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
M902-01  
Integrated  
Circuit  
VCSO BASED  
P r o d u c t D a t a S h e e t  
SAW PLL Application Notes Available  
GB  
E CLOCK  
G
ENERATOR  
Systems, Inc.  
PLL Simulator Tool Available  
A free PC software utility is available on the ICS website  
(www.icst.com). The M2000 Timing Modules PLL  
Simulator is a downloadable application that simulates  
PLL jitter and wander transfer characteristics. This  
enables the user to set appropriate external loop  
component values in a given application.  
The ICS web site (www.icst.com) also has application  
notes on:  
PCB layout guidelines (including special detailed  
instructions for preventing issues such as external  
reference crosstalk)  
Any new special device application details that may  
become available  
Refer to the SAW PLL Simulator Software web page at  
www.icst.com/products/calculators/m2000filterSWdesc.htm  
for additional information.  
Instructions for using PLL simulator software  
Guidelines for PCB fabrication (including recom-  
mended PCB footprint, solder mask, and furnace  
profile)  
Refer to the SAW PLL Application Notes web page at  
www.icst.com/products/appnotes/SawPllAppNotes.htm  
for application notes and any additional product  
information that may become available.  
1
ABSOLUTE MAXIMUM RATINGS  
Symbol Parameter  
Rating  
Unit  
VI  
Input Voltage  
-0.5 to VCC +0.5  
V
VO  
I O  
VCC  
TS  
Output Voltage  
-0.5 to VCC +0.5  
V
mA  
V
25  
4.6  
Output Current  
Power Supply Voltage  
Storage Temperature  
-45 to +100  
oC  
Table 5: Absolute Maximum Ratings  
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the  
device. These ratings are stress specifications only. Functional operation of product at these conditions  
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or  
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods  
may affect product reliability  
.
RECOMMENDED CONDITIONS OF OPERATION  
Symbol Parameter  
Min  
Typ  
Max Unit  
3.135  
3.3  
3.465  
VCC  
Positive Supply Voltage  
V
TA  
Ambient Operating Temperature  
oC  
oC  
0
Commercial  
Industrial  
+70  
+85  
-40  
Table 6: Recommended Conditions of Operation  
M902-01 Datasheet Rev 2.1  
5 of 8  
Revised 24Jun2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
M902-01  
Integrated  
Circuit  
Systems, Inc.  
VCSO BASED  
GB  
E CLOCK  
G
ENERATOR  
P r o d u c t D a t a S h e e t  
ELECTRICAL SPECIFICATIONS  
DC Characteristics  
1
1
Unless stated otherwise, VCC  
=
3.3V +  
5
%,TA = 0 oC to +70 oC (commercial) , TA = -40 oC to +85 oC (industrial) , Output Frequency=156.25MHz1  
,
LVPECL outputs terminated with 50to VCC - 2V  
Symbol Parameter  
Power Supply VCC Positive Supply Voltage  
Min  
3.135  
Typ  
3.3  
Max  
3.465  
Unit  
V
300  
ICC  
Power Supply Current  
mA  
2
Logic Inputs  
VIH  
VIL  
IIH  
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
Input High Voltage  
Input Low Voltage  
Input High Current  
Input Low Current  
V
+0.3  
V
cc  
0.8  
150  
-0.3  
V
EN_EXT_CLK, EXT_CLK,  
STOP  
µA  
µA  
V
IIL  
-5.0  
Reference  
Clock  
Input  
VIH  
VIL  
IIH  
(V / 2 ) +0.5  
V +0.3  
cc  
cc  
-0.3  
-5.0  
(V / 2 ) -0.5 V  
cc  
XTAL_1 / REF_IN  
(XTAL_2 disconnected)  
150  
µA  
µA  
IIL  
EN_EXT_CLK, EXT_CLK,  
Input Capacitance, All Inputs STOP,  
XTAL_1 / REF_IN, XTAL_2  
All Inputs  
Pull-down  
CIN  
4
pF  
R
Internal Pull-down Resistor  
Output High Voltage  
EN_EXT_CLK, STOP  
51  
kΩ  
V
pulldown  
Differential  
Output  
VOH  
VOL  
VP-P  
V
V
-1.4  
-2.0  
V
V
-1.0  
cc  
cc  
cc  
FOUT, nFOUT (0-1)  
Output Low Voltage  
-1.7  
V
cc  
0.5  
0.85  
Peak to Peak Output Voltage  
V
Table 7: DC Characteristics  
Note 1: See Ordering Information on pg. 8  
AC Characteristics  
1
1
Unless stated otherwise, VCC  
=
3.3V +  
5
%,TA = 0 oC to +70 oC (commercial) , TA = -40 oC to +85 oC (industrial) , Output Frequency=156.25MHz1  
,
LVPECL outputs terminated with 50to VCC - 2V  
Symbol Parameter  
Min  
125  
Typ  
156.25  
Max  
190  
Unit  
MHz  
Test Conditions  
FOUT  
Output Frequency Range  
25  
FIN  
Nominal Input Frequency, XTAL_1 / REF_IN  
VCSO Pull-Range  
MHz  
ppm  
APR  
Φn  
±100  
±150  
Single Side Band  
Phase Noise  
1kHz Offset  
10kHz Offset  
100kHz Offset  
-90  
-110  
-135  
0.5  
dBc/Hz  
dBc/Hz  
dBc/Hz  
ps  
@156.25MHz  
1.0  
55  
J(t)  
tDC  
tR  
Jitter (rms)  
12kHz to 20MHz  
45  
50  
450  
450  
Output Duty Cycle, High Time  
%
FOUT, nFOUT (0-1)  
350  
350  
550  
550  
100  
200  
Output Rise Time  
Output Fall Time  
Output Skew  
ps  
ps  
ps  
MHz  
20% to 80%  
20% to 80%  
FOUT, nFOUT (0-1)  
Between Any Pair  
EXT_CLK  
tF  
tS  
EXT_CLK Frequency  
0
Table 8: AC Characteristics  
Note 1: See Ordering Information on pg. 8  
M902-01 Datasheet Rev 2.1  
6 of 8  
Revised 24Jun2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
M902-01  
Integrated  
Circuit  
Systems, Inc.  
VCSO BASED  
GB  
E CLOCK  
G
ENERATOR  
P r o d u c t D a t a S h e e t  
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER  
Mechanical Dimensions:  
Refer to the M902-01 product web page at  
www.icst.com/products/summary/m902-01.htm  
for recommended PCB footprint, solder mask,  
furnace profile, and related information.  
Figure 6: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier  
M902-01 Datasheet Rev 2.1  
7 of 8  
Revised 24Jun2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  
P r o d u c t D a t a S h e e t  
M902-01  
Integrated  
Circuit  
Systems, Inc.  
VCSO BASED  
GBE CLOCK  
G
ENERATOR  
ORDERING INFORMATION  
Part Numbering Scheme  
Example Part Numbers  
Output Freq. (MHz) Temperature Order Part Number  
Part Number:  
M902-01-xxx.xxxx  
Device Number  
commercial  
industrial  
M902-01-125.0000  
M902-01 125.0000  
M902-01-156.2500  
M902-01 156.2500  
M902-01-187.5000  
M902-01 187.5000  
Temperature  
125.00  
156.25  
187.50  
0
to +70 o  
C (commercial)  
I-==- 40 to +85 o  
C
(industrial)  
I
commercial  
industrial  
Output Frequency (MHz)  
See Table 9, right. Consult ICS for other frequencies.  
I
commercial  
Figure 7: Part Numbering Scheme  
industrial  
I
Table 9: Example Part Numbers  
Consult factory for frequency availability.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)  
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would  
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial  
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary  
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any  
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or  
critical medical instruments.  
M902-01 Datasheet Rev 2.1  
8 of 8  
Revised 24Jun2004  
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400  

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