PA7024JI-25 [ICT]
EE PLD, 25ns, CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | PA7024JI-25 |
| 厂家： | 
InnoChips Technology |
| 描述： | EE PLD, 25ns, CMOS, PQCC28, PLASTIC, LCC-28 时钟 栅 输入元件 可编程逻辑 |
| 文件： | 总6页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Commercial/
Industrial
TM
PA7024 PEEL Array
Programmable Electrically Erasable Logic Array
Features
■
CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
■
High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
28-pin PLCC packages
-Optional JN package for 22V10 power/ground
compatibility
- Industrial grade available for 4.5 to 5.5V Vcc
and -40 to +85°C temperatures
■
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
■
■
Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and
other wide-gate functions
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
■
Development and Programmer Support
- ICT PLACE Development Software
Flexible Logic Cell
- Multiple output functions per cell
- Fitters for ABEL, CUPL and other software
-Programming support by ICT PDS-3 and popular third-
party programmers
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
-Sum of products logic for output enable
General Description
The PA7024 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free design-
ers from the limitations of ordinary PLDs by providing the
architectural flexibility and speed needed for today’s pro-
grammable logic designs. The PA7024 is by far the most
powerful 24-pin PLD available today with 20 I/O pins, 2
input/global-clocks and 40 registers/latches (20 buried logic
cells and 20 I/O registers/latches). Its logic array imple-
ments 84 sum-of-product logic functions that share 80
product terms. The PA7024’s logic and I/O cells (LCCs,
IOCs) are extremely flexible, offering two output functions
per logic cell (a total of 40 for all 20 logic cells). Logic cells
are configurable as D, T, and JK registers with independent
or global clocks, resets, presets, clock polarity, and other
special features. This makes them suitable for a wide vari-
ety of combinatorial, synchronous and asynchronous logic
applications. With pin compatibility and super-set function-
ality to most 24-pin PLDs, (22V10, EP610/630, GAL6002),
the PA7024 can implement designs that exceed the archi-
tectures of such devices. The PA7024 supports speeds as
fast as 10ns/15ns (tpdi/tpdx) and 71.4MHz (fMAX) at mod-
erate power consumption 120mA (85mA typical). Packag-
ing includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure
1). Development and programming support for the PA7024
is provided by ICT and popular third-party development tool
manufacturers.
Figure 1: Pin Configuration
Figure 2. Block Diagram
SOIC
DIP
PLCC-JN
PLCC-J
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PA7024
This device has been designed and tested for the recommended
operating conditions. Proper operation outside these levels is not
guaranteed. Exposure to absolute maximum ratings may cause per-
manent damage.
Table 1. Absolute Maximum Ratings
Symbol
Parameter
Conditions
Ratings
Unit
VCC
Supply Voltage
Relative to Ground
-0.5 to + 7.0
V
Voltage Applied to Any Pin2
Output Current
Relative to Ground1
Per pin (IOL, IOH)
VI, VO
-0.5 to VCC + 0.6
V
IO
±25
-65 to + 150
+300
mA
°C
TST
TLT
Storage Temperature
Lead Temperature
Soldering 10 seconds
°C
Table 2. Operating Ranges
Symbol
Parameter
Conditions
Min
Max
Unit
Commercial
4.75
4.5
0
5.25
5.5
+70
+85
20
VCC
Supply Voltage
V
Industrial
Commercial
Industrial
TA
Ambient Temperature
°C
-40
TR
Clock Rise Time
Clock Fall Time
VCC Rise Time
See Note 2
See Note 2
See Note 2
ns
ns
TF
20
TRVCC
250
ms
Table 3. D.C. Electrical Characteristics over the recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VOH
VOHC
VOL
VOLC
VIH
Output HIGH Voltage - TTL
Output HIGH Voltage - CMOS
Output LOW Voltage - TTL
Output LOW Voltage - CMOS
Input HIGH Level
VCC = Min, IOH = -4.0mA
VCC = Min, IOH = -10µA
VCC = Min, IOL = 16mA
VCC = Min, IOL = 10µA
2.4
V
VCC - 0.3
V
0.5
0.15
V
V
2.0
VCC + 0.3
0.8
V
VIL
Input LOW Level
-0.3
V
IIL
Input Leakage Current
Output Leakage Current
VCC = Max, GND VIN VCC
±10
µA
µA
mA
≤
≤
IOZ
I/O = High-Z, GND VO VCC
±10
≤
≤
Output Short Circuit Current4
ISC
VCC = 5V, VO = 0.5V, TA= 25°C
-30
-120
-15
-20
-25
I-25
120
120
120
130
6
3,11
VIN = 0V or VCC
f = 25MHz
11
85 (typ.)17
VCC Current
mA
ICC
All outputs disabled4
7
Input Capacitance5
Output Capacitance5
pF
pF
CIN
TA = 25°C, VCC = 5.0V
@ f = 1 MHz
7
12
COUT
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PA7024
Over the operating range
Table 1. A.C Electrical Characteristics Combinatorial
-15
-20
I -25
Max
6,12
Symbol
Parameter
Min
Max
Min
Max
Min
Unit
tPDI
tPDX
tIA
Propagation delay Internal (tAL + tLC)
Propagation delay External (tIA + tAL +tLC + tLO)
Input or I/O pin to array input
10
15
2
13
20
2
17
25
2
ns
ns
ns
ns
ns
tAL
Array input to LCC
9
12
1
16
1
LCC input to LCC output10
LCC output to output pin
tLC
1
tLO
3
3
5
5
6
6
ns
ns
Output Disable, Enable from LCC output7
Output Disable, Enable from input pin7
tOD, tOE
tOX
15
20
25
ns
Combinatorial Timing - Waveforms and Block Diagram
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PA7024
Table 1. A.C. Electrical Characteristics Sequential over the operating range
-15
-20
I-25
Max
Unit
6,12
Symbol
Parameter
Min
Max
Min
9
Max
Min
15
Internal set-up to system clock8 - LCC14
(tAL + tSK + tLC - tCK)
tSCI
6
8
ns
Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI)
tSCX
tCOI
11
17
ns
ns
System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC)
System-clock to Output Ext. - LCC (tCOI + tLO)
Input hold time from system clock - LCC
8
8
8
tCOX
tHX
12
13
13
ns
ns
ns
0
3
0
3
0
4
LCC Input set-up to async. clock13 - LCC
Clock at LCC or IOC - LCC output
tSK
tAK
tHK
tSI
1
4
0
1
4
0
1
4
0
ns
ns
ns
LCC input hold time from system clock - LCC
Input set-up to system clock - IOC/INC14 (tSK - tCK)
Input hold time from system clock - IOC/INC14 (tSK - tCK)
Array input to IOC PCLK clock
tHI
4
4
4/3
ns
ns
ns
tPK
6
7
7
7
9
7
Input set-up to PCLK clock18 - IOC/INC (tSK-tPK-tIA)16
tSPI
0
5
0
6
0
7
Input hold from PCLK clock18 - IOC/INC (tPK+tIA-tSK)16
System-clock delay to LCC/IOCINC
tHPI
ns
tCK
ns
tCW
System-clock low or high pulse width
7
7
8
ns
fMAX1
fMAX2
fMAX3
fMAX4
fTGL
Max. system-clock frequency Int/Int 1/(tSCI + tCOI)
Max. system-clock frequency Ext/Int 1/(tSCX + tCOI)
Max. system-clock frequency Int/Ext 1/(tSCI + tCOX)
Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX)
71.4
62.5
55.5
50.0
71.4
58.8
52.6
45.5
41.6
71.4
43.5
40.0
35.7
33.3
62.5
MHz
MHz
MHz
MHz
MHz
Max. system-clock toggle frequency 1/(tCW + tCW)9
LCC presents/reset to LCC output
tPR
1
1
2
ns
ns
ns
ns
ns
ns
ns
µs
tST
Input to Global Cell present/reset (tIA + tAL + tPR)
Asynch. preset/reset pulse width
12
15
20
tAW
8
8
8
tRT
Input to LCC Reg-Type (RT)
6
1
7
8
1
9
10
2
tRTV
tRTC
tRW
tRESET
LCC Reg-Type to LCC output register change
Input to Global Cell register-type change (tRT + tRTV)
Asynch. Reg-Type pulse width
12
10
10
10
Power-on reset time for registers in clear state2
5
5
5
4 of 6
PA7024
Sequential Timing - Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for
periods less than 20ns.
2. Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced
at 10% and 90% levels.
3. I/O pins are 0V or VCC.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless otherwise
specified).
7. tOE is measured from input transition to VREF ±0.1V (See test loads for
VREF value). tOD is measured from input transition to VOH -0.1Vor VOL
+0.1V.
8. “System-clock” refers to pin 1 or 13 (2 or 16 PLCC) high speed clocks.
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
12. Test loads are specified in Section 5 of this Data Book.
13. “Async. clock” refers to the clock from the Sum term (OR gate).
14. The “LCC” term indicates that the timing parameter is applied to the
LCC register. The “IOC” term indicates that the timing parameter is
applied to the IOC register. The “LCC/IOC/INC” term indicates that the
timing parameter is applied to both the LCC, IOC and INC registers.
15. The term “Input” without any reference to another term refers to an
(external) input pin.
16. The parameter tSPI indicates that the PCLK signal to the IOC register is
always slower than the data from the pin or input by the absolute value
of (tSK -tPK -tIA). This means that no set-up time for the data from the
pin or input is required, i.e. the external data and clock can be sent to
the device simultaneously. Additionally, the data from the pin must
remain stable for tHPI time, i.e. to wait for the PCLK signal to arrive at
the IOC register.
17. Typical (typ) ICC is measured at TA =25°C, Freq = 25MHz, VCC =5V.
5 of 6
PA7024
Ordering Information
Part Number
Speed
Temperature
Package
PA7024P-15
PA7024J-15
PA7024JN-15
PA7024S-15
PA7024P-20
PA7024J-20
PA7024JN-20
PA7024S-20
PA7024PI-25
PA7024JI-25
PA7024JNI-25
PA7024SI-25
P24
J28
10/15ns
C
JN28
S24
P24
J28
13/20ns
C
JN28
S24
P24
J28
17/25ns
17/25ns
17/25ns
17/25ns
I
I
I
I
JN28
S24
Device
Suffix
Part Number
PA7024J-20
Package
Speed
P = Plastic 300mil DIP
-15 = 10ns/15ns tpdi/tpdx
-20 = 13ns/20ns tpdi/tpdx
-25 = 17ns/25ns tpdi/tpdx
J = Plastic (J) Leaded Chip Carrier
JN = PLCC Alternate Pin Out
S = SOIC 300mil Gullwing
Temperature Range
(Blank) = Commercial 0 to 70°C
I = Industrial -40 to +85°C
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