1493AGI-19LFT [IDT]
Clock Generator, 66MHz, CMOS, PDSO28, 4.40 MM, ROHS COMPLIANT, TSSOP-28;
| 型号： | 1493AGI-19LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 66MHz, CMOS, PDSO28, 4.40 MM, ROHS COMPLIANT, TSSOP-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS1493A-19
CLOCK GENERATOR FOR AUTOMOTIVE APPLICATION
Description
Features
The ICS1493A-19 is a low cost frequency generator
used for automotive application. Using patented
Phase-Locked-Loop (PLL) techniques, the device uses
a 19.35 MHz fundamental crystal source to produce
seven clock outputs and one reference clock output.
The output clocks are at 12.288 MHz, 14.7456 MHz,
22.5792 MHz, 48 MHz, 66.60 MHz, and 33.30 MHz
with a 19.35 MHz reference clock output. The 66.60
MHz and 33.30 MHz clocks have a spread select
option. Operating voltage of the ICS1493A-19 is 3.3 V.
• Packaged in 28-pin TSSOP (4.4mm body)
• Low power CMOS technology
• Input crystal frequency of 19.35 MHz
• 3.3 V operating voltage
• Seven output clocks: 12.288 /33.30 MHz, 14.7456
MHz, 22.5792 MHz, 48 MHz, 66.60 MHz (3 copies)
• One reference clock output at 19.35 MHz
• Spread select option on the 66.60 MHz clock (3
copies) and 33.30 MHz clock outputs
ICS makes many frequency generators. Contact us for
all of your clocking needs.
• Output enable pin stops clocks low (tri-state with
weak pull-down resistors)
• Zero ppm synthesis error for 48 MHz, 19.35 MHz
clocks; 0.5 ppm error for 12.288 MHz, 14.7456 MHz,
22.5792 MHz clocks; 1 ppm error for 66.60 MHz and
33.30 MHz clocks.
• Industrial temperature range (-40°C to +85°C)
Block Diagram
VDD
8
3
PLLA with
Spread
66.60M
SSEN
Spectrum
12.288M/
33.30M
PLLB
14.7456M
48M
PLLC
PLLD
22.5792M
19.35M
X1
Crystal
Oscillator
19.35 MHz
Crystal
X2
7
External tuning
capacitors required
FSEL
OE
GND
MDS 1493A-19 C
1
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS1493A-19
CLOCK GENERATOR FOR AUTOMOTIVE APPLICATION
Pin Assignment
Spread Enable Table 1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
X1
1
X2
GNDX
2
VDDX
FSEL
SSEN
66.60/33.30 MHz Clock
No spread (default)
-1.0%
3
CLK19
0
1
GND14&19
4
OE
VDD14&19
CLK14
VDD48
GND48
CLK48
VDD22
GND22
CLK22
VDD66
CLK66
5
SSEN
VDDPLL
GNDPLL
CLK66
VDD66
CLK33
Output Enable Function Table 2
6
7
OE
0
Output Status
Stopped low
8
9
1
Running (default)
10
11
12
13
14
Frequency Select Table 3
VDD33
GND33
GND66
CLK66
FSEL
Clock Selected (MHz)
0
1
12.288
33.30 (default)
28-pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
X1
Input
Crystal connection. Connect to a 19.35 MHz fundamental crystal.
GNDX
CLK19
Power Crystal oscillator circuit ground.
3
Output 19.35 MHz reference clock output. Internal weak pull-down resistor.
4
GND14&19 Power Connect to 14.7456 MHz and 19.35 MHz clock output ground.
VDD14&19 Power Output driver power for 14.7456 MHz clock output.
5
6
CLK14
VDD48
GND48
CLK48
VDD22
GND22
CLK22
VDD66
CLK66
CLK66
Output 14.7456 MHz clock output. Internal weak pull-down resistor.
Power Output driver power for 48 MHz clock output.
7
8
Power Connect to 48 MHz clock output ground.
9
Output 48 MHz clock output. Internal weak pull-down resistor.
Power Output driver power for 22.5792 MHz clock output.
Power Connect to 22.5792 MHz clock output circuit ground.
Output 22.5792 MHz clock output. Internal weak pull-down resistor.
Power Output driver power for 66.60 MHz clock output.
Output 66.60 MHz clock output. Internal weak pull-down resistor.
Output 66.60 MHz clock output. Internal weak pull-down resistor.
10
11
12
13
14
15
MDS 1493A-19 C
2
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS1493A-19
CLOCK GENERATOR FOR AUTOMOTIVE APPLICATION
Pin
Number
Pin
Name
Pin
Type
Pin Description
16
17
18
19
GND66
GND33
VDD33
Power Connect to 66.60 MHz clock output circuit ground.
Power Connect to 33.30 MHz clock output circuit ground.
Power Output driver power for 33.30 MHz clock output.
Output 33.30 /12.288 MHz clock output. Internal weak pull-down resistor.
CLK33
/12.288
20
21
22
23
24
VDD66
CLK66
Power Output driver power for 66.60 MHz clock output.
Output 66.60 MHz clock output. Internal weak pull-down resistor.
Power Connect to PLL circuit ground.
GNDPLL
VDDPLL
SSEN
Power VDD for PLL circuits Connect to 3.3 V.
Input
Input
Input
Spread enable pin for 66.60 MHz clock. See table 1 above. Internal
pull-down resistor.
25
OE
Enables output when =1 and disables (pulled low) when =0. See table
above 2. Internal pull-up resistor.
26
27
28
FSEL
VDDX
X2
Frequency select pin, internal pull-up. See Table 3.
Power VDD for crystal oscillator circuit. Connect to 3.3.V.
Input Crystal connection. Connect to a 19.35 MHz fundamental crystal.
MDS 1493A-19 C
3
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS1493A-19
CLOCK GENERATOR FOR AUTOMOTIVE APPLICATION
External Components
Decoupling Capacitor
PCB Layout Recommendations
As with any high-performance mixed-signal IC, the
ICS1493A-19 must be isolated from system power
supply noise to perform optimally.
Observe the following guidelines for optimum device
performance and lowest output phase noise:
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pins as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces. Instead, they should be separated and away
from other traces.
Crystal Load Capacitors
3) Place the 33Ωseries termination resistor (if needed)
close to the clock output to minimize EMI.
The device crystal connections should include pads for
capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS1493A-19. This includes signal
traces just underneath the device, or on layers adjacent
to the ground plane layer used by the device.
The value (in pF) of these crystal caps should equal
(C - 6 pF)*2. In this equation, C = crystal load
L
L
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2 = 20 pF].
MDS 1493A-19 C
4
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS1493A-19
CLOCK GENERATOR FOR AUTOMOTIVE APPLICATION
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS1493A-19. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
-0.5 V to 7 V
-0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
° C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
+3.0
+3.3
+3.6
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
Conditions
Min.
Typ.
3.3
Max.
Units
3.0
3.6
0.8
0.4
V
mA
V
IDD
No load
80
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
V
2
IH
V
V
IL
V
V
I
I
I
= -4 mA
= -12 mA
= 12 mA
VDD-0.4
2.4
V
OH
OH
OH
OH
OL
V
V
V
OL
OS
I
Clock outputs,15 and
21
80
70
mA
Short Circuit Current
I
Clock outputs 3, 6, 9,
12, 14, and 19
mA
OS
Input Capacitance
C
Input
5
pF
Ω
IN
Nominal Output Impedance
Internal Pull-up Resistor
Z
20
OUT
R
FSEL, OE pins
200
kΩ
PU
MDS 1493A-19 C
5
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS1493A-19
CLOCK GENERATOR FOR AUTOMOTIVE APPLICATION
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Internal Pull-down Resistor
R
All clock outputs
except SSEN pin
200
kΩ
Pd
SSEN pin
100
kΩ
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ. Max. Units
f
19.35
1.1
1.1
50
MHz
ns
IN
Output Rise Time
Output Fall Time
t
20% to 80%, C =12 pF
1.5
1.5
55
60
175
1
OR
L
t
80% to 20%, C =12 pF
ns
OF
L
Output Clock Duty Cycle
at VDD/2, C =12 pF
45
40
%
L
at VDD/2, Pin 3, C =12 pF
50
%
L
Output-to-Output Skew
Output Enable Time
Output Disable Time
Power-up Time
Pins 14, 15, and 21 only
OE going high to output valid
OE going low to output Invalid
Power on to output valid
Spread rate
ps
ms
ms
ms
kHz
ps
1
20
Spread Modulation
Jitter, Cycle-to-cycle
32
All clocks except reference clock
19.35 MHz
300
Jitter, Cycle-to-cycle
Jitter, Peak-to-peak
Reference clock 19.35 MHz
500
150
ps
ps
Peak-to-peak, all clocks except
reference clock 19.35 MHz
Jitter, Peak-to-peak
Peak-to-peak, reference clock
19.35 MHz
250
ps
ppm
ms
Output Frequency
Synthesis Error
All clocks
10
Transition Time
t
Measured from a change of FSEL
until clock stable within 1%
1
TR
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
83
75
61
60
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
MDS 1493A-19 C
6
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS1493A-19
CLOCK GENERATOR FOR AUTOMOTIVE APPLICATION
Marking Diagram
28
15
14
1493AGI-19LF
######
YYWW
1
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “LF” denotes Pb (lead) free package.
4. Bottom marking: (origin)
Origin = country of origin if not USA.
MDS 1493A-19 C
7
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
ICS1493A-19
CLOCK GENERATOR FOR AUTOMOTIVE APPLICATION
Package Outline and Package Dimensions (28-pin TSSOP, 4.4mm body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches*
28
Symbol
Min
Max
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
9.80
--
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
9.60
6.40 BASIC
4.30 4.50
0.65 Basic
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.378 0.386
0.252 BASIC
0.169 0.177
0.0256 Basic
1 2
E1
e
L
D
0.45
0.75
0.018
0.030
α
0°
8°
0°
8°
aaa
--
0.10
--
0.004
*For reference only. Controlling dimensions in mm.
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
ICS1493AGI-19LF
ICS1493AGI-19LFT
Marking
Shipping Packaging
Tubes
Package
28-pin TSSOP
28-pin TSSOP
Temperature
-40° to +85° C
-40° to +85° C
see page 7
Tape and Reel
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for
either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other
applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or
specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
MDS 1493A-19 C
8
Revision 051310
Integrated Device Technology, Inc. ● www.idt.com
相关型号：
1494560000
PCB terminal, TOP connection, Soldered connection, Clamping range, max.: 6 mm², Pitch: 7.62 mm, No. of poles: 2, 180°, Box
WEIDMULLER
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