2305-1DC8 [IDT]
PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8;
| 型号： | 2305-1DC8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8 光电二极管 |
| 文件： | 总11页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT2305
3.3V ZERO DELAY
CLOCK BUFFER
FEATURES:
DESCRIPTION:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five outputs
• Zero Input-Output Delay
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
• Output Skew < 250ps
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one
referenceinput,anddrivesoutfivelowskewclocks.The-1Hversionofthis
device operates, up to 133MHz frequency and has a higher drive than the
-1 device. All parts have on-chip PLLs which lock to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305 enters power down. In
• Low jitter <200 ps cycle-to-cycle
• IDT2305-1 for Standard Drive
• IDT2305-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Power down mode
• Available in SOIC package
this mode, the device will draw less than 25μA, the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power.
The IDT2305 is characterized for both Industrial and Commercial
operation.
FUNCTIONALBLOCKDIAGRAM
8
CLKOUT
3
CLK1
PLL
1
Control
Logic
REF
2
CLK2
CLK3
CLK4
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DECEMBER 2007
1
c
2007 Integrated Device Technology, Inc.
DSC 5174/8
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Rating
Max.
–0.5to+4.6
–0.5to+5.5
–0.5to
VDD+0.5
–50
Unit
V
VDD
SupplyVoltageRange
InputVoltageRange(REF)
InputVoltageRange
(2)
VI
V
1
REF
8
7
6
5
CLKOUT
CLK4
VI
V
CLK2
2
(exceptREF)
IIK (VI < 0)
InputClampCurrent
ContinuousOutputCurrent
ContinuousCurrent
mA
mA
mA
W
VDD
3
4
CLK1
GND
IO (VO = 0 to VDD)
VDD or GND
TA = 55°C
±50
CLK3
±100
MaximumPowerDissipation
0.7
(3)
(instillair)
TSTG
StorageTemperatureRange
CommercialTemperature
Range
–65to+150
0 to +70
° C
° C
SOIC
TOP VIEW
Operating
Temperature
Operating
Temperature
NOTES:
IndustrialTemperature
Range
-40to+85
° C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
PINDESCRIPTION
Pin Name
Pin Number
Type
IN
FunctionalDescription
REF(1)
1
2
3
4
5
6
7
Inputreferenceclock,5Volttolerantinput
Output clock
CLK2(2)
CLK1(2)
GND
Out
Out
Output clock
Ground
Out
Ground
CLK3(2)
Output clock
VDD
CLK4(2)
PWR
Out
3.3V Supply
Output clock
(2)
CLKOUT
8
Out
Outputclock,internalfeedbackonthis pin
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
2
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
OPERATINGCONDITIONS-COMMERCIAL
Symbol
VDD
TA
Parameter
Min.
3
Max.
3.6
70
Unit
V
SupplyVoltage
OperatingTemperature(AmbientTemperature)
LoadCapacitance <100MHz
0
°C
pF
CL
—
—
—
30
Load Capacitance 100MHz - 133MHz
InputCapacitance
10
CIN
7
pF
DCELECTRICALCHARACTERISTICS-COMMERCIAL
Symbol
VIL
Parameter
Conditions
Min.
—
2
Max.
0.8
—
Unit
V
InputLOWVoltageLevel
Input HIGH Voltage Level
InputLOWCurrent
Input HIGH Current
OutputLOWVoltage
VIH
V
IIL
VIN = 0V
—
—
—
50
µ A
µ A
V
IIH
VIN = VDD
100
0.4
VOL
StandardDrive
High Drive
IOL = 8mA
IOL = 12mA (-1H)
IOH = -8mA
VOH
OutputHIGHVoltage
StandardDrive
High Drive
2.4
—
V
IOH = -12mA (-1H)
IDD_PD
IDD
Power Down Current
SupplyCurrent
REF = 0MHz
—
—
12
32
µ A
mA
UnloadedOutputsat66.66MHz
SWITCHINGCHARACTERISTICS(2305-1)-COMMERCIAL(1,2)
Symbol
Parameter
Conditions
Min.
10
Typ. Max.
Unit
t1
OutputFrequency
10pFLoad
30pFLoad
—
—
50
—
—
—
0
133
100
60
MHz
10
Duty Cycle = t2 ÷ t1
RiseTime
Measured at 1.4V, FOUT = 66.66MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
Alloutputsequallyloaded
40
%
ns
ns
ps
ps
ps
ps
t3
t4
t5
t6
t7
tJ
—
—
—
—
—
—
2.5
2.5
250
350
700
200
FallTime
OutputtoOutputSkew
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
0
Cycle-to-Cycle Jitter, pk - pk
Measuredat66.66MHz,loadedoutputs
—
tLOCK
PLLLockTime
Stable power supply, valid clock presented on REF pin
—
—
1
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
3
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
SWITCHINGCHARACTERISTICS(2305-1H)-COMMERCIAL(1,2)
Symbol
Parameter
OutputFrequency
Conditions
Min.
10
Typ. Max.
Unit
t1
10pFLoad
30pFLoad
—
—
133
100
MHz
10
Duty Cycle = t2 ÷ t1
Duty Cycle = t2 ÷ t1
RiseTime
Measured at 1.4V, FOUT = 66.66MHz
Measured at 1.4V, FOUT <50MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
Alloutputsequallyloaded
40
45
—
—
—
—
—
1
50
50
—
—
—
0
60
55
%
%
t3
1.5
1.5
250
350
700
—
200
1
ns
t4
FallTime
ns
t5
OutputtoOutputSkew
ps
t6
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2
ps
t7
t8
Device-to-Device Skew
OutputSlewRate
Measured at VDD/2 on the CLKOUT pins of devices
0
ps
Measured between 0.8V and 2V using Test Circuit #2
Measuredat66.66MHz,loadedoutputs
—
—
—
V/ns
ps
tJ
Cycle-to-Cycle Jitter, pk - pk
PLLLockTime
—
—
tLOCK
Stable power supply, valid clock presented on REF pin
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
OPERATINGCONDITIONS-INDUSTRIAL
Symbol
VDD
TA
Parameter
Min.
3
Max.
3.6
+85
30
Unit
SupplyVoltage
V
°C
pF
OperatingTemperature(AmbientTemperature)
LoadCapacitance <100MHz
-40
—
—
—
CL
Load Capacitance 100MHz - 133MHz
InputCapacitance
10
CIN
7
pF
DCELECTRICALCHARACTERISTICS-INDUSTRIAL
Symbol
VIL
Parameter
Conditions
Min.
—
2
Max.
Unit
V
InputLOWVoltageLevel
Input HIGH Voltage Level
InputLOWCurrent
Input HIGH Current
OutputLOWVoltage
0.8
—
50
VIH
V
IIL
VIN = 0V
—
—
—
µ A
µ A
V
IIH
VIN = VDD
100
0.4
VOL
StandardDrive
High Drive
IOL = 8mA
IOL = 12mA (-1H)
IOH = -8mA
VOH
OutputHIGHVoltage
StandardDrive
High Drive
2.4
—
V
IOH = -12mA (-1H)
IDD_PD
IDD
Power Down Current
SupplyCurrent
REF = 0MHz
—
—
25
35
µ A
mA
UnloadedOutputsat66.66MHz
4
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
SWITCHINGCHARACTERISTICS(2305-1)-INDUSTRIAL(1,2)
Symbol
Parameter
Conditions
Min.
10
Typ. Max.
Unit
t1
OutputFrequency
10pFLoad
30pFLoad
—
—
50
—
—
—
0
133
100
60
MHz
10
Duty Cycle = t2 ÷ t1
RiseTime
Measured at 1.4V, FOUT = 66.66MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
Alloutputsequallyloaded
40
%
ns
ns
ps
ps
ps
ps
t3
t4
t5
t6
t7
tJ
—
—
—
—
—
—
2.5
2.5
250
350
700
200
FallTime
OutputtoOutputSkew
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
0
Cycle-to-Cycle Jitter, pk - pk
Measuredat66.66MHz,loadedoutputs
—
tLOCK
PLLLockTime
Stable power supply, valid clock presented on REF pin
—
—
1
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
SWITCHINGCHARACTERISTICS(2305-1H)-INDUSTRIAL(1,2)
Symbol
Parameter
OutputFrequency
Conditions
Min.
10
Typ. Max.
Unit
t1
10pFLoad
30pFLoad
—
—
133
100
MHz
10
Duty Cycle = t2 ÷ t1
Duty Cycle = t2 ÷ t1
RiseTime
Measured at 1.4V, FOUT = 66.66MHz
Measured at 1.4V, FOUT <50MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
Alloutputsequallyloaded
40
45
—
—
—
—
—
1
50
50
—
—
—
0
60
55
%
%
t3
1.5
1.5
250
350
700
—
200
1
ns
t4
FallTime
ns
t5
OutputtoOutputSkew
ps
t6
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2
ps
t7
t8
Device-to-Device Skew
OutputSlewRate
Measured at VDD/2 on the CLKOUT pins of devices
0
ps
Measured between 0.8V and 2V using Test Circuit #2
Measuredat66.66MHz,loadedoutputs
—
—
—
V/ns
ps
tJ
Cycle-to-Cycle Jitter, pk - pk
PLLLockTime
—
—
tLOCK
Stable power supply, valid clock presented on REF pin
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
5
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loadingcanaffectandadjustthe input/outputdelay.The OutputLoadDifference diagramillustrates the PLL's relative loadingwithrespecttothe other
outputs thatcanadjustthe Input-Output(I/O)Delay.
Fordesigns utilizingzeroI/ODelay, alloutputs includingCLKOUTmustbe equallyloaded. Evenifthe outputis notused, itmusthave a capacitive
load equaltothatontheotheroutputsinordertoobtaintruezeroI/ODelay.IfI/ODelayadjustmentsareneeded,usetheOutputLoadDifferencediagram
tocalculate loadingdifferences betweenthe CLKOUTpinandotheroutputs.Forzerooutput-to-outputskew,alloutputs mustbe loadedequally.
REF TO CLKA/CLKB RELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS
1500
1000
500
0
-30
-25
-20
-10
0
5
30
-15
-5
10
15
20
25
-500
-1000
-1500
OUTPUT LOAD DIFFERENCE BETWEEN CLKOUT PIN AND CLKA/CLKB PINS (pF)
6
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
SWITCHINGWAVEFORMS
1.4V
t1
Output
t2
1.4V
1.4V
1.4V
1.4V
Output
t5
Output to Output Skew
Duty Cycle Timing
3.3V
0V
VDD/2
REF
2V
0.8V
t4
0.8V
t3
2V
Output
VDD/2
Output
t6
Input to Output Propagation Delay
All Outputs Rise/Fall Time
CLKOUT
Device 1
VDD/2
CLKOUT
Device 2
VDD/2
t7
Device to Device Skew
TESTCIRCUITS
VDD
VDD
1KΩ
1KΩ
CLKOUT
CLKOUT
10pF
0.1μF
0.1μF
OUTPUTS
OUTPUTS
CLOAD
VDD
VDD
0.1μF
0.1μF
GND
GND
GND
GND
Test Circuit 2 (t8, Output Slew Rate On -1H Devices)
Test Circuit 1 (all Parameters Except t8)
7
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305-1
Duty Cycle vs VDD
Duty Cycle vs VDD
(for 30pf loads over frequency - 3.3V, 25C)
(for 10pF loads over frequency - 3.3V, 25C)
60
58
56
60
58
56
54
52
54
52
33MHz
33MHz
50
48
46
44
50
48
46
44
66MHz
100MHz
66MHz
100MHz
133MHz
42
40
42
40
3
3.4
3
3.4
3.1
3.3
3.5
3.6
3.1
3.3
3.5
3.6
3.2
3.2
VDD (V)
VDD (V)
Duty Cycle vs Frequency
(for 30pf loads over temperature - 3.3V)
Duty Cycle vs Frequency
(for 10pF loads over temperature - 3.3V)
60
58
56
60
58
56
54
52
54
52
-40C
-40C
50
48
46
44
0C
50
48
46
44
0C
25C
70C
85C
25C
70C
85C
42
40
42
40
20
40
80
100
120
140
60
20
40
80
100
120
140
60
Frequency (MHz)
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 30pf loads over frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 10pF loads over frequency - 3.3V, 25C)
140
120
140
120
100
80
100
80
33MHz
33MHz
66MHz
66MHz
100MHz
100MHz
60
60
40
20
0
40
20
0
0
2
4
8
0
2
6
4
8
6
Number of Loaded Outputs
Number of Loaded Outputs
NOTES:
1. Duty Cycle is taken from typical chip measured at 1.4V.
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F);
V = Supply Voltage (V); f = Frequency (Hz))
8
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2305-1H
Duty Cycle vs VDD
(for 30pf loads over frequency - 3.3V, 25C)
Duty Cycle vs VDD
(for 10pF loads over frequency - 3.3V, 25C)
60
58
56
60
58
56
54
52
54
52
33MHz
33MHz
50
48
46
44
50
48
46
44
66MHz
100MHz
66MHz
100MHz
133MHz
42
40
42
40
3
3.4
3
3.4
3.1
3.3
3.5
3.6
3.1
3.3
3.5
3.6
3.2
3.2
VDD (V)
VDD (V)
Duty Cycle vs Frequency
(for 30pf loads over temperature - 3.3V)
Duty Cycle vs Frequency
(for 10pF loads over temperature - 3.3V)
60
58
56
60
58
56
54
52
54
52
-40C
-40C
50
48
46
44
0C
50
48
46
44
0C
25C
70C
85C
25C
70C
85C
42
40
42
40
20
40
80
100
120
140
60
20
40
80
100
120
140
60
Frequency (MHz)
Frequency (MHz)
IDD vs Number of Loaded Outputs
(for 30pf loads over frequency - 3.3V, 25C)
IDD vs Number of Loaded Outputs
(for 10pF loads over frequency - 3.3V, 25C)
160
140
160
140
120
120
100
80
100
80
60
33MHz
33MHz
66MHz
100MHz
66MHz
100MHz
60
40
20
0
40
20
0
0
2
0
2
4
8
6
4
8
6
Number of Loaded Outputs
Number of Loaded Outputs
NOTES:
1. Duty Cycle is taken from typical chip measured at 1.4V.
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);
f = Frequency (Hz))
9
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PACKAGE OUTLINE AND PACKAGE DIMENSIONS - SOIC
N
C
L
E
H
INDEX
AREA
h x 45°
1
2
α
D
A
A1
SEATING
PLANE
e
B
.10 (.004)
150 mil (Narrow Body) SOIC
In Millimeters
VARIATIONS
N
D (inch)(1)
MAX
In Inches (1)
D (mm)
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
4.80
8.55
9.80
MAX
MIN
SYMBOL
8
5.00
8.75
.1890
.3367
.3859
.1968
.3444
.3937
MIN
1.35
0.10
0.33
0.19
MAX
1.75
0.25
0.51
0.25
MIN
MAX
.0688
.0098
.0200
.0098
14
A
A1
B
C
D
E
e
.0532
.0040
.0130
.0075
16
10.00
NOTE:
1. For reference only. Controlling dimensions are in mm.
SEE VARIATIONS
SEE VARIATIONS
3.80
4.00
.1497
.1574
1.27 BASIC
0.050 BASIC
H
h
5.80
0.25
0.40
6.20
0.50
1.27
.2284
.010
.016
.2440
.020
.050
L
N
α
SEE VARIATIONS
0° 8°
SEE VARIATIONS
0° 8°
NOTE:
1. For reference only. Controlling dimensions are in mm.
10
IDT2305
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
ORDERINGINFORMATION
XXXXX
XX
X
IDT
Package Process
Device Type
o
o
Commercial (0 C to +70 C)
Blank
I
o
o
Industrial (-40 C to +85 C)
DC
DCG
Small Outline
SOIC - Green
Zero Delay Clock Buffer
High Drive Output
2305-1
2305-1H
Ordering Code
PackageType
OperatingRange
Commercial
IDT2305-1DC
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
IDT2305-1DCG
IDT2305-1DCI
IDT2305-1DCGI
IDT2305-1HDC
IDT2305-1HDCI
Commercial
Industrial
Industrial
Commercial
Industrial
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
clockhelp@idt.com
www.idt.com
11
相关型号：
2305-1HDC8
PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8
IDT
2305-1HDCI8
PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8
IDT
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