2309A-1HDC [IDT]
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-16;
| 型号： | 2309A-1HDC |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-16 光电二极管 |
| 文件： | 总8页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT2309A
3.3V ZERO DELAY
CLOCK BUFFER
FEATURES:
DESCRIPTION:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer,
designedtoaddresshigh-speedclockdistributionapplications. Thezero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2309A-1 for Standard Drive
• IDT2309A-1H for High Drive
The IDT2309A is a 16-pin version of the IDT2305A. The IDT2309A
acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.
The-1Hversionofthisdeviceoperatesupto133MHzfrequencyandhas
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT2309Aenterspowerdown. Inthismode,thedevicewilldrawlessthan
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages
12μAforCommercialTemperaturerangeandlessthan25μAforIndustrial
temperature range, and the outputs are tri-stated.
The IDT2309A is characterized for both Industrial and Commercial
operation.
FUNCTIONALBLOCKDIAGRAM
16
CLKOUT
2
CLKA1
PLL
1
REF
3
CLKA2
14
CLKA3
15
CLKA4
8
S2
Control
Logic
9
S1
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 2010
1
c
2010 Integrated Device Technology, Inc.
DSC - 6588/5
IDT2309A
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Rating
Max.
–0.5to+4.6
–0.5to+5.5
–0.5to
VDD+0.5
–50
Unit
V
VDD
SupplyVoltageRange
InputVoltageRange(REF)
InputVoltageRange
(except REF)
REF
CLKA1
CLKA2
VDD
1
2
16
15
14
13
12
11
CLKOUT
CLKA4
CLKA3
VDD
(2)
VI
VI
V
V
3
IIK (VI < 0)
IO (VO = 0 to VDD)
VDD or GND
TA = 55°C
(instillair)(3)
TSTG
InputClampCurrent
ContinuousOutputCurrent
ContinuousCurrent
mA
mA
mA
W
4
5
6
±50
GND
GND
±100
MaximumPowerDissipation
0.7
CLKB1
CLKB2
S2
CLKB4
CLKB3
S1
7
8
10
9
StorageTemperatureRange
CommercialTemperature
Range
–65to+150
0 to +70
°C
°C
Operating
Temperature
Operating
IndustrialTemperature
Range
-40to+85
°C
SOIC/ TSSOP
TOP VIEW
Temperature
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
PINDESCRIPTION
Pin Name
REF(1)
Pin Number
Type
IN
FunctionalDescription
Inputreferenceclock, 5Volttolerantinput
Output clock for bank A
Output clock for bank A
3.3V Supply
1
2
CLKA1(2)
CLKA2(2)
VDD
Out
Out
PWR
GND
Out
Out
IN
3
4, 13
5, 12
6
GND
Ground
CLKB1(2)
CLKB2(2)
S2(3)
Output clock for bank B
Output clock for bank B
Select input Bit 2
7
8
S1(3)
9
IN
Select input Bit 1
CLKB3(2)
CLKB4(2)
CLKA3(2)
CLKA4(2)
CLKOUT(2)
10
11
14
15
16
Out
Out
Out
Out
Out
Output clock for bank B
Output clock for bank B
Output clock for bank A
Output clock for bank A
Outputclock, internalfeedbackonthispin
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
2
IDT2309A
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
FUNCTIONTABLE(1)
S2
L
S1
L
CLKA
Tri-State
Driven
Driven
CLKB
Tri-State
Tri-State
Driven
CLKOUT(2)
Driven
Output Source
PLL Shut Down
PLL
PLL
REF
N
N
Y
L
H
L
Driven
H
Driven
H
H
Driven
Driven
Driven
PLL
N
NOTES:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
DCELECTRICALCHARACTERISTICS-COMMERCIAL
Symbol
VIL
Parameter
Conditions
Min.
—
2
Max.
0.8
—
Unit
V
InputLOWVoltageLevel
Input HIGH Voltage Level
InputLOWCurrent
Input HIGH Current
OutputLOWVoltage
VIH
V
IIL
VIN = 0V
—
—
—
50
μA
μA
V
IIH
VIN = VDD
100
0.4
VOL
StandardDrive
High Drive
StandardDrive
High Drive
IOL = 8mA
IOL = 12mA (-1H)
IOH = -8mA
VOH
Output HIGH Voltage
2.4
—
V
IOH = -12mA (-1H)
IDD_PD
IDD
Power Down Current
SupplyCurrent
REF = 0MHz (S2 = S1 = H)
Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND
—
—
12
32
μA
mA
OPERATINGCONDITIONS-COMMERCIAL
Symbol
Parameter
Min.
3
Max.
3.6
70
Unit
V
VDD
SupplyVoltage
TA
OperatingTemperature(AmbientTemperature)
Load Capacitance < 100MHz
0
°C
pF
CL
—
—
—
30
Load Capacitance 100MHz - 133MHz
InputCapacitance
10
CIN
7
pF
SWITCHINGCHARACTERISTICS(2309A-1)-COMMERCIAL(1,2)
Symbol
Parameter
Conditions
Min.
10
10
40
—
—
—
—
1
Typ.
—
—
50
—
—
—
0
Max.
Unit
t1
OutputFrequency
10pFLoad
30pFLoad
133
100
60
MHz
Duty Cycle = t2 ÷ t1
RiseTime
Measured at 1.4V, FOUT = 66.66MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
Alloutputsequallyloaded
%
t3
t4
2.5
2.5
250
350
8.7
700
200
ns
ns
ps
ps
ns
ps
ps
FallTime
t5
OutputtoOutputSkew
Delay, REF Rising Edge to CLKOUT Rising Edge(2) MeasuredatVDD/2
Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2 in PLL bypass mode (IDT2309A only)
t6A
t6B
t7
5
Device-to-Device Skew
Cycle-to-Cycle Jitter
Measured at VDD/2 on the CLKOUT pins of devices
Measuredat66.66MHz,loadedoutputs
—
—
0
tJ
—
tLOCK PLLLockTime
Stable power supply, valid clock presented on REF pin
—
—
1
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
3
IDT2309A
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
SWITCHINGCHARACTERISTICS(2309A-1H)-COMMERCIAL(1,2)
Symbol
Parameter
Conditions
Min.
10
Typ.
—
Max.
133
Unit
t1
OutputFrequency
10pFLoad
30pFLoad
MHz
10
—
100
Duty Cycle = t2 ÷ t1
Duty Cycle = t2 ÷ t1
RiseTime
Measured at 1.4V, FOUT = 66.66MHz
Measured at 1.4V, FOUT <50MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
Alloutputsequallyloaded
40
45
—
—
50
50
—
—
60
55
%
%
ns
ns
t3
t4
1.5
1.5
FallTime
t5
t6A
t6B
t7
OutputtoOutputSkew
—
—
1
—
0
250
350
8.7
ps
ps
ns
ps
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2
Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309A only)
5
Device-to-Device Skew
OutputSlewRate
Cycle-to-Cycle Jitter
PLLLockTime
Measured at VDD/2 on the CLKOUT pins of devices
Measured between 0.8V and 2V using Test Circuit 2
Measuredat66.66MHz,loadedoutputs
—
0
700
t8
tJ
1
—
—
—
—
200
1
V/ns
ps
—
—
tLOCK
Stable power supply, valid clock presented on REF pin
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
DCELECTRICALCHARACTERISTICS-INDUSTRIAL
Symbol
VIL
Parameter
Conditions
Min.
—
2
Max.
Unit
InputLOWVoltageLevel
Input HIGH Voltage Level
InputLOWCurrent
Input HIGH Current
OutputLOWVoltage
0.8
—
V
V
VIH
IIL
VIN = 0V
—
—
—
50
μA
μA
V
IIH
VIN = VDD
100
0.4
VOL
StandardDrive
High Drive
StandardDrive
High Drive
IOL = 8mA
IOL = 12mA (-1H)
IOH = -8mA
VOH
Output HIGH Voltage
2.4
—
V
IOH = -12mA (-1H)
IDD_PD
IDD
Power Down Current
SupplyCurrent
REF = 0MHz (S2 = S1 = H)
Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND
—
—
25
35
μA
mA
OPERATINGCONDITIONS-INDUSTRIAL
Symbol
Parameter
Min.
3
Max.
Unit
V
VDD
SupplyVoltage
3.6
+85
30
TA
OperatingTemperature(AmbientTemperature)
Load Capacitance < 100MHz
-40
—
°C
pF
CL
Load Capacitance 100MHz - 133MHz
InputCapacitance
—
10
CIN
—
7
pF
4
IDT2309A
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
SWITCHINGCHARACTERISTICS(2309A-1)-INDUSTRIAL(1,2)
Symbol
Parameter
Conditions
Min.
10
10
40
—
—
—
—
1
Typ.
—
—
50
—
—
—
0
Max.
133
100
60
Unit
t1
OutputFrequency
10pFLoad
30pFLoad
MHz
Duty Cycle = t2 ÷ t1
RiseTime
Measured at 1.4V, FOUT = 66.66MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
Alloutputsequallyloaded
%
t3
t4
2.5
ns
ns
ps
ps
ns
ps
ps
FallTime
2.5
t5
OutputtoOutputSkew
250
350
8.7
t6A
t6B
t7
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2
Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309A only)
5
Device-to-Device Skew
Cycle-to-Cycle Jitter
Measured at VDD/2 on the CLKOUT pins of devices
Measuredat66.66MHz,loadedoutputs
—
—
0
700
200
tJ
—
tLOCK
PLLLockTime
Stable power supply, valid clock presented on REF pin
—
—
1
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
SWITCHINGCHARACTERISTICS(2309A-1H)-INDUSTRIAL(1,2)
Symbol
Parameter
Conditions
Min.
10
Typ.
—
Max.
133
Unit
t1
OutputFrequency
10pFLoad
30pFLoad
MHz
10
—
100
Duty Cycle = t2 ÷ t1
Duty Cycle = t2 ÷ t1
RiseTime
Measured at 1.4V, FOUT = 66.66MHz
Measured at 1.4V, FOUT <50MHz
Measured between 0.8V and 2V
Measured between 0.8V and 2V
Alloutputsequallyloaded
40
45
—
—
50
50
—
—
60
55
%
%
ns
ns
t3
t4
1.5
1.5
FallTime
t5
t6A
t6B
t7
OutputtoOutputSkew
—
—
1
—
0
250
350
8.7
ps
ps
ns
ps
Delay, REF Rising Edge to CLKOUT Rising Edge MeasuredatVDD/2
Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2 in PLL bypass mode (IDT2309A only)
5
Device-to-Device Skew
OutputSlewRate
Cycle-to-Cycle Jitter
PLLLockTime
Measured at VDD/2 on the CLKOUT pins of devices
Measured between 0.8V and 2V using Test Circuit 2
Measuredat66.66MHz,loadedoutputs
—
0
700
t8
tJ
1
—
—
—
—
200
1
V/ns
ps
—
—
tLOCK
NOTES:
Stable power supply, valid clock presented on REF pin
ms
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
5
IDT2309A
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other
outputs that can adjust the Input-Output (I/O) Delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.
SWITCHINGWAVEFORMS
t1
1.4V
Output
t2
1.4V
1.4V
1.4V
1.4V
Output
t5
Output to Output Skew
Duty Cycle Timing
VDD/2
3.3V
0V
REF
2V
0.8V
t4
0.8V
t3
2V
Output
VDD/2
Output
t6
Input to Output Propagation Delay
All Outputs Rise/Fall Time
CLK
VDD/2
OUT
Device 1
CLK
OUT
Device 2 t7
VDD/2
Device to Device Skew
6
IDT2309A
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
TESTCIRCUITS
VDD
VDD
1K
1K
CLK
OUT
CLK
OUT
0.1 F
0.1 F
0.1 F
OUTPUTS
OUTPUTS
C
10pF
LOAD
VDD
GND
VDD
0.1 F
GND
GND
GND
Test Circuit 2 (t8, Output Slew Rate On -1H Devices)
Test Circuit 1 (all Parameters Except t8)
7
IDT2309A
3.3VZERODELAYCLOCKBUFFER
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
ORDERINGINFORMATION
XXXXX
XX
X
Package Process
Device Type
o
o
Blank
I
Commercial (0 C to +70 C)
o o
Industrial (-40 C to +85 C)
DCG
SOIC - Green
PGG
TSSOP - Green
2309A-1 Zero Delay Clock Buffer with High Drive
2309A-1H
Ordering Code
PackageType
OperatingRange
2309A-1DCG
2309A-1DCGI
16-Pin SOIC
16-Pin SOIC
Commercial
Industrial
2309A-1HDCG
2309A-1HDCGI
2309A-1HPGG
2309A-1HPGGI
16-Pin SOIC
16-Pin SOIC
16-Pin TSSOP
16-Pin TSSOP
Commercial
Industrial
Commercial
Industrial
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
clockhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
8
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