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23S09T-1DCG

更新时间：2025-07-09 12:30:29
品牌：IDT
描述：2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

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23S09T-1DCG 概述

2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE 2.5V零延迟时钟缓冲器，扩频兼容 时钟发生器

23S09T-1DCG 数据手册

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IDT23S09T  
2.5V ZERO DELAY  
CLOCK BUFFER, SPREAD  
SPECTRUM COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five and one bank of  
four outputs  
The IDT23S09T is a high-speed phase-lock loop (PLL) clock buffer,  
designedtoaddresshigh-speedclockdistributionapplications. Thezero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Separate output enable for each output bank  
• Output Skew < 250ps  
• Low jitter <200 ps cycle-to-cycle  
• No external RC network required  
• Operates at 2.5V VDD  
TheIDT23S09Tisa16-pinversionoftheIDT23S05T. TheIDT23S09T  
acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.  
All parts have on-chip PLLs which lock to an input clock on the REF pin.  
The PLL feedback is on-chip and is obtained from the CLKOUT pad. In  
the absence of an input clock, the IDT23S09T enters power down, and  
• Spread spectrum compatible  
• Available in SOIC package  
theoutputsaretri-stated.Inthismode,thedevicewilldrawlessthan12µA.  
FUNCTIONALBLOCKDIAGRAM  
16  
CLKOUT  
2
CLKA1  
PLL  
1
REF  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
S2  
Control  
Logic  
9
S1  
6
CLKB1  
7
CLKB2  
10  
CLKB3  
11  
CLKB4  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
MAY 2010  
1
c
2003 Integrated Device Technology, Inc.  
DSC 6396/8  
IDT23S09T  
2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE  
COMMERCIALTEMPERATURERANGE  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Rating  
Max.  
–0.5to+4.6  
–0.5to+5.5  
–0.5to  
VDD+0.5  
–50  
Unit  
V
VDD  
SupplyVoltageRange  
InputVoltageRange(REF)  
InputVoltageRange  
(except REF)  
REF  
CLKA1  
CLKA2  
VDD  
1
2
16  
15  
14  
13  
12  
11  
CLKOUT  
CLKA4  
CLKA3  
VDD  
(2)  
VI  
VI  
V
V
3
IIK (VI < 0)  
IO (VO = 0 to VDD)  
VDD or GND  
TA = 55°C  
(instillair)(3)  
TSTG  
InputClampCurrent  
ContinuousOutputCurrent  
ContinuousCurrent  
mA  
mA  
mA  
W
4
5
6
±50  
GND  
GND  
±100  
MaximumPowerDissipation  
0.7  
CLKB1  
CLKB2  
S2  
CLKB4  
CLKB3  
S1  
7
8
10  
9
StorageTemperatureRange  
CommercialTemperature  
Range  
–65to+150  
0 to +70  
°C  
°C  
Operating  
Temperature  
NOTES:  
SOIC  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. The input and output negative-voltage ratings may be exceeded if the input and output  
clamp-current ratings are observed.  
3. The maximum package power dissipation is calculated using a junction temperature  
of 150°C and a board trace length of 750 mils.  
TOP VIEW  
APPLICATIONS:  
•
•
•
•
•
SDRAM  
Telecom  
Datacom  
PC Motherboards/Workstations  
Critical Path Delay Designs  
PINDESCRIPTION  
Pin Name  
REF(1)  
Pin Number  
Type  
IN  
FunctionalDescription  
Inputreferenceclock, 3.3Vtolerantinput  
Output clock for bank A  
Output clock for bank A  
2.5V Supply  
1
2
CLKA1(2)  
CLKA2(2)  
VDD  
Out  
Out  
PWR  
GND  
Out  
Out  
IN  
3
4, 13  
5, 12  
6
GND  
Ground  
CLKB1(2)  
CLKB2(2)  
S2(3)  
Output clock for bank B  
Output clock for bank B  
Select input Bit 2  
7
8
S1(3)  
9
IN  
Select input Bit 1  
CLKB3(2)  
CLKB4(2)  
CLKA3(2)  
CLKA4(2)  
CLKOUT(2)  
10  
11  
14  
15  
16  
Out  
Out  
Out  
Out  
Out  
Output clock for bank B  
Output clock for bank B  
Output clock for bank A  
Output clock for bank A  
Outputclock, internalfeedbackonthispin  
NOTES:  
1. Weak pull down.  
2. Weak pull down on all outputs.  
3. Weak pull ups on these inputs.  
2
IDT23S09T  
2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE  
COMMERCIALTEMPERATURERANGE  
FUNCTIONTABLE(1)  
S2  
L
S1  
L
CLKA  
Tri-State  
Driven  
Driven  
CLKB  
Tri-State  
Tri-State  
Driven  
CLKOUT(2)  
Driven  
Output Source  
PLL Shut Down  
PLL  
PLL  
REF  
N
N
Y
L
H
L
Driven  
H
Driven  
H
H
Driven  
Driven  
Driven  
PLL  
N
NOTES:  
1. H = HIGH Voltage Level.  
L = LOW Voltage Level  
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.  
DCELECTRICALCHARACTERISTICS  
Symbol  
VIL  
Parameter  
Conditions  
Min.  
—
Max.  
0.7  
—
Unit  
V
InputLOWVoltageLevel  
Input HIGH Voltage Level  
InputLOWCurrent  
Input HIGH Current  
OutputLOWVoltage  
Output HIGH Voltage  
Power Down Current  
SupplyCurrent  
VIH  
1.7  
—
V
IIL  
VIN = 0V  
50  
µA  
µA  
V
IIH  
VIN = VDD  
—
100  
0.3  
—
VOL  
VOH  
IDD_PD  
IDD  
Standard Drive, IOL = 8mA  
—
Standard Drive, IOH = -8mA  
2
V
REF = 0MHz (S2 = S1 = H)  
—
12  
µA  
mA  
Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND  
—
32  
OPERATINGCONDITIONS  
Symbol  
VDD  
TA  
Parameter  
Min.  
2.3  
0
Max.  
2.7  
70  
Unit  
V
SupplyVoltage  
OperatingTemperature(AmbientTemperature)  
Load Capacitance 10MHz - 133MHz  
InputCapacitance  
°C  
pF  
CL  
—
15  
CIN  
—
7
pF  
SWITCHINGCHARACTERISTICS(1,2)  
Symbol  
Parameter  
Conditions  
Min.  
10  
40  
—
—
—
—
1
Typ.  
—
50  
—
—
—
0
Max.  
Unit  
t1  
OutputFrequency  
15pFLoad  
133  
60  
MHz  
%
Duty Cycle = t2 ÷ t1  
RiseTime  
Measured at VDD/2, FOUT = 66.66MHz  
Measured between 0.7V and 1.7V  
Measured between 0.7V and 1.7V  
Alloutputsequallyloaded  
t3  
t4  
2.5  
2.5  
250  
350  
8.7  
700  
200  
ns  
FallTime  
ns  
t5  
OutputtoOutputSkew  
ps  
t6A  
t6B  
t7  
Delay, REF Rising Edge to CLKOUT Rising Edge(2) MeasuredatVDD/2  
Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2 in PLL bypass mode  
ps  
5
ns  
Device-to-Device Skew  
Cycle-to-Cycle Jitter  
Measured at VDD/2 on the CLKOUT pins of devices  
Measuredat66.66MHz,loadedoutputs  
—
—
0
ps  
tJ  
—
ps  
tLOCK  
PLLLockTime  
Stable power supply, valid clock presented on REF pin  
—
—
1
ms  
NOTES:  
1. REF Input has a threshold voltage of VDD/2.  
2. All parameters specified with loaded outputs.  
3
IDT23S09T  
2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE  
COMMERCIALTEMPERATURERANGE  
ZERO DELAY AND SKEW CONTROL  
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative  
loading can affect and adjust the input/output delay.  
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive  
load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.  
SPREAD SPECTRUM COMPATIBLE  
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter  
offtheSpreadSpectrumfeatureofthereferenceinput, assumingitexists. WhenazerodelaybufferisnotdesignedtopasstheSpreadSpectrumfeature  
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.  
4
IDT23S09T  
2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE  
COMMERCIALTEMPERATURERANGE  
TESTCIRCUIT  
VDD  
CLK  
OUT  
0.1 F  
OUTPUTS  
C
LOAD  
VDD  
0.1 F  
GND  
GND  
Test Circuit for All Parameters  
SWITCHINGWAVEFORMS  
t1  
VDD/2  
t5  
Output  
Output  
t2  
VDD/2  
VDD/2  
VDD/2  
VDD/2  
Output to Output Skew  
Duty Cycle Timing  
VDD/2  
2.5V  
0V  
REF  
0.7V  
t4  
1.7V  
1.7V  
0.7V  
t3  
Output  
VDD/2  
Output  
t6  
Input to Output Propagation Delay  
All Outputs Rise/Fall Time  
CLK  
VDD/2  
OUT  
Device 1  
CLK  
OUT  
Device 2 t7  
VDD/2  
Device to Device Skew  
5
IDT23S09T  
2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE  
COMMERCIALTEMPERATURERANGE  
ORDERINGINFORMATION  
XXXXX  
XX  
X
IDT  
Package Process  
Device Type  
o
o
Blank  
Commercial (0 C to +70 C)  
DCG  
SOIC - Green  
23S09T-1  
2.5V Zero Delay Clock Buffer, Spread Spectrum Compatible  
Part / Order Number  
Shipping Packaging  
Package  
Temperature  
23S09T-1DCG  
23S09T-1DCG8  
Tubes  
TapeandReel  
16-pinSOIC  
16-pinSOIC  
0° to +70° C  
0° to +70° C  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
for Tech Support:  
clockhelp@idt.com  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
6

23S09T-1DCG 替代型号

型号 制造商 描述 替代类型 文档
23S09T-1DCG8 IDT 2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE 完全替代
CY2309SXI-1H CYPRESS Low-Cost 3.3V Zero Delay Buffer 功能相似

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