251PMLF_技术文档

Field Programmable SS VersaClock Synthesizer

ICS251

DATASHEET

Description

Features

The ICS251 is a low cost, single-output, field programmable

clock synthesizer. The ICS251 can generate an output

frequency from 314 kHz to 200 MHz and may employ Spread

Spectrum techniques to reduce system electro-magnetic

interference (EMI).

• 8-pin SOIC package

• Four addressable registers

• Input crystal frequency of 5 to 27 MHz

• Clock input frequency of 3 to 150 MHz

• Output clock frequencies up to 200 MHz

• Configurable Spread Spectrum Modulation

• Operating voltage of 3.3 V

™

Using IDT’s VersaClock software to configure the PLL and

output, the ICS251 contains a One-Time Programmable

(OTP) ROM to allow field programmability. Programming

features include 4 selectable configuration registers.

• Replaces multiple crystals and oscillators

• Controllable output drive levels

The device employs Phase-Locked Loop (PLL) techniques to

run from a standard fundamental mode, inexpensive crystal,

or clock. It can replace multiple crystals and oscillators,

saving board space and cost.

• Advanced, low-power CMOS process

• Available in RoHS compliant packaging

The device also has a power-down feature that tri-states the

clock outputs and turns off the PLLs when the PDTS pin is

taken low.

The ICS251 is also available in factory programmed custom

versions for high-volume applications.

Block Diagram

VDD

OTP ROM

2

with PLL

S1:0

Divider

Values

PLL Clock Synthesis,

Spread Spectrum and

Control Circuitry

CLK

Crystal or

clock input

X1/ICLK

Crystal

Oscillator

X2

GND

External capacitors are

required with a crystal input.

PDTS (output and PLL)

ICS251 REVISION E 05/19/14

1

ICS251 DATASHEET

Pin Assignment

Output Clock Selection Table

S1

S0

CLK (MHz)

Spread

Percentage

User

Configurable

User

Configurable

User

Configurable

User

Configurable

S 0

V D D

1

2

3

4

8

7

6

5

P D T S

G N D

User

Configurable

User

Configurable

User

Configurable

User

Configurable

0

1

0

1

0

1

X 1 / I C L K

X 2

S 1

C L K

8-pin (150 mil) SOIC

Pin Descriptions

Pin Description

Number

Name

Type

1

2

3

4

5

6

7

S0

VDD

X1/ICLK

X2

Input

Power

XI

Select pin 0 for frequency selection on CLK. Internal pull-up resistor.

Connect to +3.3 V.

Connect this pin to a crystal or external clock input.

Connect this pin to a crystal, or float for clock input.

XO

CLK

S1

Output Clock output. Weak internal pull-down when tri-state.

Input

Select pin 1 for frequency selection on CLK. Internal pull-up resistor.

Connect this to Ground.

GND

Power

Powers down entire chip. Tri-states CLK outputs when low. No internal pull-up

resistor. The pin must be tied either directly or through the external resistor to

VDD or GND. External resistor value must be less than 15kOhm.

8

PDTS

Input

External Components

The ICS251 requires a minimum number of external

components for proper operation.

increased in this trimming process, it is important to keep stray

capacitance to a minimum by using very short PCB traces

(and no vias) been the crystal and device. Crystal capacitors

must be connected from each of the pins X1 and X2 to ground.

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50 trace (a commonly

used trace impedance), place a 33 resistor in series with the

clock line, as close to the clock output pin as possible. The

nominal impedance of the clock output is 20.

The value (in pF) of these crystal caps should equal (C -6

L

pF)*2. In this equation, C = crystal load capacitance in pF.

L

Example: For a crystal with a 16 pF load capacitance, each

crystal capacitor would be 20 pF [(16-6) x 2] = 20.

Decoupling Capacitor

As with any high-performance mixed-signal IC, the ICS251

must be isolated from system power supply noise to perform

optimally.

A decoupling capacitor of 0.01µF must be connected between

VDD and the PCB ground plane.

Crystal Load Capacitors

The device crystal connections should include pads for small

capacitors from X1 to ground and from X2 to ground. These

capacitors are used to adjust the stray capacitance of the

board to match the nominally required crystal load

capacitance. Because load capacitance can only be

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

2

REVISION E 05/19/14

ICS251 DATASHEET

PCB Layout Recommendations

IDT VersaClock Software

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

IDT applies years of PLL optimization experience into a user

friendly software that accepts the user’s target reference clock

and output frequencies and generates the lowest jitter, lowest

power configuration, with only a press of a button. The user

does not need to have prior PLL experience or determine the

optimal VCO frequency to support multiple output

frequencies.

1) The 0.01µF decoupling capacitor should be mounted on the

component side of the board as close to the VDD pin as

possible. No vias should be used between the decoupling

capacitor and VDD pin. The PCB trace to VDD pin should be

kept as short as possible, as should the PCB trace to the

ground via. Distance of the ferrite bead and bulk decoupling

from the device is less critical.

VersaClock software quickly evaluates accessible VCO

frequencies with available output divide values and provides

an easy to understand, bar code rating for the target output

frequencies. The user may evaluate output accuracy,

performance trade-off scenarios in seconds.

2) The external crystal should be mounted just next to the

device with short traces. The X1 and X2 traces should not be

routed next to each other with minimum spaces, instead they

should be separated and away from other traces.

Spread Spectrum Modulation

The ICS251 utilizes frequency modulation (FM) to distribute

energy over a range of frequencies. By modulating the output

clock frequencies, the device effectively lowers energy across

a broader range of frequencies; thus, lowering a system’s

electro-magnetic interference (EMI). The modulation rate is

the time from transitioning from a minimum frequency to a

maximum frequency and then back to the minimum.

3) To minimize EMI, the 33 series termination resistor (if

needed) should be placed close to the clock output.

4) An optimum layout is one with all components on the same

side of the board, minimizing vias through other signal layers.

Other signal traces should be routed away from the ICS251.

This includes signal traces just underneath the device, or on

layers adjacent to the ground plane layer used by the device.

Spread Spectrum Modulation can be applied as either “center

spread” or “down spread”. During center spread modulation,

the deviation from the target frequency is equal in the positive

and negative directions. The effective average frequency is

equal to the target frequency. In applications where the clock

is driving a component with a maximum frequency rating,

down spread should be applied. In this case, the maximum

frequency, including modulation, is the target frequency. The

effective average frequency is less than the target frequency.

ICS251 Configuration Capabilities

The architecture of the ICS251 allows the user to easily

configure the device to a wide range of output frequencies, for

a given input reference frequency.

The frequency multiplier PLL provides a high degree of

precision. The M/N values (the multiplier/divide values

available to generate the target VCO frequency) can be set

within the range of M = 1 to 2048 and N = 1 to 1024.

The ICS251 operates in both center spread and down spread

modes. For center spread, the frequency can be modulated

between +/- 0.125% to +/-2.0%. For down spread, the

frequency can be modulated between -0.25% to -4.0%.

The ICS251 also provides separate output divide values, from

2 through 20, to allow the two output clock banks to support

widely differing frequency values from the same PLL.

Both output frequency banks will utilize identical spread

spectrum percentage deviations and modulation rates, if a

common VCO frequency can be identified.

Each output frequency can be represented

as:

Spread Spectrum Modulation Rate

REFFreq

M

N

-------------------------------------- ----

OutputFreq = _OutputDivide

The spread spectrum modulation frequency applied to the

output clock frequency may occur at a variety of rates. For

applications requiring the driving of “down-circuit” PLLs, Zero

Delay Buffers, or those adhering to PCI standards, the spread

spectrum modulation rate should be set to 30-33 kHz. For

other applications, a 120 kHz modulation option is available.

Output Drive Control

The ICS251 has two output drive settings. Low drive should

be selected when outputs are less than 100 MHz. High drive

should be selected when outputs are greater than 100 MHz.

(Consult the AC Electrical Characteristics for output rise and

fall times for each drive option.)

REVISION E 05/19/14

3

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

ICS251 DATASHEET

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS251. These ratings, which are

standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or

any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are

guaranteed only over the recommended operating temperature range.

Parameter

Condition

Min.

-0.5

-65

Typ.

Max.

4.6

Units

V

Supply Voltage, VDD

Inputs

Referenced to GND

VDD+ 0.5

150

V

Clock Outputs

V

Storage Temperature

Soldering Temperature

Junction Temperature

C

Max 10 seconds

260

125

Recommended Operation Conditions

Parameter

Min.

0

Typ.

Max.

+70

+85

+3.45

4

Units

C

Ambient Operating Temperature (ICS251M)

Ambient Operating Temperature (ICS251MI)

Power Supply Voltage (measured in respect to GND)

Power Supply Ramp Time

-40

C

+3.15

+3.3

V

ms

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

4

REVISION E 05/19/14

ICS251 DATASHEET

DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85C

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Operating Voltage

VDD

3.15

3.3

3.45

V

Configuration Dependent -

See VersaClock^TM

mA

33.3333 MHz output, PDTS

= 1, no load

Note 1

14

mA

Operating Supply Current

Input High Voltage

IDD

PDTS = 0

S1:S0

500

A

V

Input High Voltage

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

VDD/2+1

VDD-0.5

VDD/2+1

Input Low Voltage

S1:S0

0.4

V

Input High Voltage, PDTS

Input Low Voltage, PDTS

Input High Voltage

V

ICLK

V

Input Low Voltage

VDD/2-1

V

Output High Voltage (CMOS

High)

V_OH

V_OL

I_OH= -4 mA

VDD-0.4

V

I_OH= -8 mA (Low Drive); I_OH

= -12 mA (High Drive)

2.4

VDD-0.4

Output High Voltage

Output Low Voltage

I_OL= 8 mA (Low Drive);

I_OL= 12 mA (High Drive)

0.4

Short Circuit Current

I_OS

Z_O

±70

20

mA



Nominal Output Impedance

Internal pull-up resistor

Internal pull-down resistor

Input Capacitance

R_PUP

R_PD

C_IN

S1:S0, PDTS

CLK output

inputs

190

120

4

k

pF

Note 1: Example with 25 MHz crystal input with output of 33.3 MHz, no load, and VDD = 3.3 V.

REVISION E 05/19/14

5

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

ICS251 DATASHEET

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85C

Parameter

Symbol

Conditions

Fundamental Crystal

Input Clock

Min.

5

Typ. Max. Units

27

MHz

ns

Input Frequency

F_IN

3

150

200

Output Frequency

Output Rise Time

Output Fall Time

Duty Cycle

0.314

t_OR

t_OF

20% to 80%, Note 1

80% to 20%, Note 1

Note 2

1

ns

40

49-51

60

10

%

PLL lock time from

power-up

4

ms

PDTS goes high until stable

CLK output, Spread

Spectrum Off

.6

2

7

ms

Power-up time

PDTS goes high until stable

CLK output, Spread

Spectrum On

4

ms

PDTS goes high until

spread spectrum is stable,

Spread Spectrum On

10

50

One Sigma Clock Period Jitter

Maximum Absolute Jitter

Configuration Dependent

50

ps

Deviation from Mean.

Configuration Dependent

t_ja

+200

Note 1: Measured with 15 pF load.

Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.

Thermal Characteristics

Parameter

Symbol

_JA

Conditions

Min.

Typ. Max. Units

C/W

Still air

150

140

120

40

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

_JA

1 m/s air flow

3 m/s air flow

_JA

_JC

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

6

REVISION E 05/19/14

ICS251 DATASHEET

Marking Diagram

Marking Diagram (Pb free)

8

5

8

5

251PML

######

YYWW

251PM

######

YYWW

1

4

1

8

4

8

5

251PMIL

######

YYWW

251PMI

######

YYWW

1

4

1

4

Notes:

1. ###### is the lot number.

2. YYWW is the last two digits of the year and week that the part was assembled.

3. “I” denotes industrial temp. range (if applicable).

4. “L” denotes RoHS compliant package.

5. Bottom marking: country of origin.

REVISION E 05/19/14

7

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

ICS251 DATASHEET

Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)

Package dimensions are kept current with JEDEC Publication No. 95

Millimeters

Inches

Min

8

Symbol

Min

1.35

0.10

0.33

0.19

4.80

3.80

Max

1.75

0.25

0.51

0.25

5.00

4.00

Max

.0688

.0098

.020

A

A1

B

C

D

E

e

.0532

.0040

.013

E

H

.0075

.1890

.1497

.0098

.1968

.1574

INDEX

AREA

1.27 BASIC

0.050 BASIC

H

h

5.80

0.25

0.40

0

6.20

0.50

1.27

8

.2284

.010

.016

0

.2440

.020

.050

8

1

2

L

D



A

h x 45

A1

C

- C -

e

SEATING

PLANE



B

L

.10 (.004)

C

Ordering Information

Part / Order Number

Marking

Shipping Packaging

Tubes

Package

8-pin SOIC

Temperature

0 to +70 C

-40 to +85 C

0 to +70 C

-40 to +85 C

0 to +70 C

-40 to +85 C

0 to +70 C

-40 to +85 C

0 to +70 C

-40 to +85 C

0 to +70 C

251PM

251PMI

251PMLF

251PMILF

251M-XX

251MI-XX

251M-XXLF

251MI-XXLF

251M-XXT

251MI-XXT

251M-XXLFT

251MI-XXLFT

See Page 7 Above

Tubes

251M-XX

251MIXX

251MXXL

251MIXXL

251M-XX

251MIXX

251MXXL

251MIXXL

Tubes

Tape and Reel

-40 to +85 C

Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

The 251M-XX, 251M-XXLF, 251MI-XX, and 251MI-XXLF are factory programmed versions of the ICS251PM, ICS251PMLF, ICS251PMI,

and ICS251PMILF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept

on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing

representative.

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

8

REVISION E 05/19/14

ICS251 DATASHEET

Revision History

Rev.

Date

Originator Description of Change

J. Chao 1. Updated Supply Voltage max rating from 7V to 4.6V

E

05/19/14

2. Updated datasheet with latest version of template.

REVISION E 05/19/14

9

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

Sales

Tech Support

email: clocks@idt.com

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in

this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined

in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether

express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This

document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected

names, logos and designs, are the property of IDT or their respective third party owners.


型号：	251PMLF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Field Programmable SS VersaClock Synthesizer 时钟光电二极管外围集成电路晶体
文件：	总10页 (文件大小：90K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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