275G [IDT]
Clock Generator, CMOS, PDSO16;
| 型号： | 275G |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, CMOS, PDSO16 光电二极管 |
| 文件： | 总9页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER
ICS275
Description
Features
The ICS275 field programmable VCXO clock synthesizer
generates up to four high-quality, high-frequency clock
outputs including multiple reference clocks from a
low-frequency crystal input. It is designed to replace
crystals and crystal oscillators in most electronic systems.
• Packaged as 16-pin TSSOP
• Eight addressable registers
• Replaces multiple crystals and oscillators
• Output frequencies up to 200 MHz at 3.3 V
• Input crystal frequency of 5 to 27 MHz
• Up to four reference outputs
• Up to two sets of two low-skew outputs
• Operating voltages of 3.3 V
• Controllable output drive levels
TM
Using ICS’ VersaClock software to configure PLLs and
outputs, the ICS275 contains a One-Time Programmable
(OTP) ROM for field programmability. Programming
features include VCXO, eight selectable configuration
registers and up to two sets of two low-skew outputs.
• Advanced, low-power CMOS process
• Available in RoHS compliant packaging
Using Phase-Locked Loop (PLL) techniques, the device
runs from a standard fundamental mode, inexpensive
crystal, or clock. It can replace VCXOs, multiple crystals
and oscillators, saving board space and cost.
The ICS275 is also available in factory programmed custom
versions for high-volume applications.
Block Diagram
3
VDD
3
OTP
PLL1
PLL2
S2:S0
CLK1
CLK2
CLK3
CLK4
ROM
with
PLL
Divide
Logic
and
Output
Enable
Control
Values
VIN
PLL3
X1
X2
Voltage
Controlled
Crystal
Crystal
Oscillator
GND
2
External capacitors
are required.
PDTS
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 1
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Pin Assignment
1
2
3
4
5
6
7
8
VIN
S0
16
15
14
13
12
11
10
9
S2
VDD
PDTS
GND
CLK4
S1
VDD
CLK1
CLK2
GND
X1
CLK3
VDD
X2
16 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO
frequency
1
VIN
Input
2
3
S0
S1
Input
Input
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
4
VDD
CLK1
CLK2
GND
X1
Power
5
Output Output clock 1. Weak internal pull-down when tri-state.
Output Output clock 2. Weak internal pull-down when tri-state.
6
7
Power
XI
Connect to ground.
8
Crystal input. Connect this pin to a crystal.
Crystal Output. Connect this pin to a crystal.
Connect to +3.3 V.
9
X2
XO
10
11
12
13
VDD
CLK3
CLK4
GND
Power
Output Output clock 3. Weak internal pull-down when tri-state.
Output Output clock 4. Weak internal pull-down when tri-state.
Power
Connect to ground.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resisitor.
14
PDTS
Input
Connect to +3.3 V.
15
16
VDD
S2
Power
Input
Select pin 2. Internal pull-up resisitor.
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 2
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The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the ICS275. There should be no via’s between the crystal
pins and the X1 and X2 device pins. There should be no
signal traces underneath or close to the crystal. See
application note MAN05.
External Components
The ICS275 requires a minimum number of external
components for proper operation.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on the
PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS275
must be isolated from system power supply noise to perform
optimally.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of your final
layout, a frequency counter capable of about 1 ppm
resolution and accuracy, two power supplies, and some
samples of the crystals which you plan to use in production,
along with measured initial accuracy for each crystal at the
specified crystal load capacitance, CL.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. For optimum
device performance, the decoupling capacitor should be
mounted on the component side of the PCB. Aboid the use
of vias on the decoupling circuit.
Quartz Crystal
The ICS275 VCXO function consists of the external crystal
and the integrated VCXO oscillator circuit. To assure the
best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the following section shown must be
followed.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS275 to 3.3 V. Connect pin 1 of the
ICS275 to the second power supply. Adjust the voltage on
pin 1 to 0V. Measure and record the frequency of the CLK
output.
2. Adjust the voltage on pin 1 to 3.3 V. Measure and record
the frequency of the same output.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
ICS275 incorporates on-chip variable load capacitors that
“pull” (change) the frequency of the crystal. The crystal
specified for use with the ICS275 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF.
To calculate the centering error:
Recommended Crystal Parameters:
(f3.0V –ftarget)+(f0V–ftarget
)
Error = 106x
–errorxtal
Initial Accuracy at 25°C
Temperature Stability
Aging
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
20 ppm
30 ppm
20 ppm
14 pf
7 pF Max
250 Max
35Ω Max
----------------------------------------------------------------------
ftarget
Where:
= nominal crystal frequency
Equivalent Series Resistance
f
target
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 3
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error =actual initial accuracy (in ppm) of the crystal being
measured
The ICS275 also provides separate output divide values,
from 2 through 63, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
xtal
If the centering error is less than 25 ppm, no adjustment is
needed. If the centering error is more than 25ppm negative,
the PC board has excessive stray capacitance and a new
PCB layout should be considered to reduce stray
capacitance. (Alternately, the crystal may be re-specified to
a higher load capacitance. Contact ICS for details.) If the
centering error is more than 25 ppm positive, add identical
fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by: External
Capacitor = 2 x (centering error)/(trim sensitivity)
Each output frequency can be represented as:
M
N
----
OutputFreq = REFFreq ⋅
ICS VersaClock Software
ICS applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
Trim sensitivity is a parameter which can be supplied by your
crystal vendor. If you do not know the value, assume it is 30
ppm/pF. After any changes, repeat the measurement to
verify that the remaining error is acceptably low (typically
less than 25 ppm).
ICS275 Configuration Capabilities
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
The architecture of the ICS275 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 1024 and N = 1 to 32,895.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS275. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Condition
Min.
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
VDD+0.5
VDD+0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
Junction Temperature
°C
°C
°C
Max 10 seconds
260
125
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 4
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Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature (ICS275PG/PGLF)
Ambient Operating Temperature (ICS275PGI/PGILF)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
0
-40
+85
°C
+3.135
+3.3
+3.465
4
V
ms
Reference crystal parameters
Refer to page 3
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5ꢀ, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.135
3.465
V
Config. Dependent - See
VersaClock Estimates
mA
TM
Four 33.3333 MHz outs,
PDTS = 1, no load, Note 1
22
mA
Operating Supply Current
Input High Voltage
IDD
PDTS = 0, no load, Note 1
S2:S0
500
µA
V
Input High Voltage
V
VDD/2+1
VDD-0.5
VDD/2+1
IH
Input Low Voltage
V
S2:S0
0.4
0.4
V
V
V
V
V
V
IL
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
V
IH
V
IL
V
ICLK
ICLK
IH
Input Low Voltage
V
VDD/2-1
IL
Output High Voltage
(CMOS High)
V
I
= -4 mA
VDD-0.4
2.4
OH
OH
Output High Voltage
Output Low Voltage
Short Circuit Current
V
I
I
= -8 mA (Low Drive);
= -12 mA (High Drive)
V
V
OH
OH
OH
V
I
I
= 8 mA (Low Drive);
= 12 mA (High Drive)
0.4
OL
OL
OL
I
Low Drive
High Drive
40
70
OS
mA
Nom. Output Impedance
Internal Pull-up Resistor
Internal Pull-down Resistor
Input Capacitance
Z
20
Ω
O
R
S2:S0, PDTS
CLK outputs
Inputs
190
120
4
kΩ
kΩ
pF
PUS
R
PD
C
IN
Note 1: Example with 25 MHz crystal input with four outputs of 33.3 MHz, no load, and VDD = 3.3 V.
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 5
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AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5ꢀ, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
5
Typ.
Max. Units
Input Frequency
F
Fundamental crystal
27
MHz
ppm
IN
Crystal Pullability
F
0V< VIN < 3.3 V, Note 1,
Config. Dependent
100
P
VCXO Gain
VIN = VDD/2 + 1 V,
Note 1, Config.
Dependent
110
ppm/V
Output Rise/Fall Time
Output Rise/Fall Time
Duty Cycle
t
t
80% to 20%, high drive,
Note 2
1.0
2.0
ns
ns
OF
80% to 20%, low drive,
Note 2
OF
Note 3
40
49-51
4
60
10
%
PLL lock-time from
power-up
ms
Power-up time
PDTS goes high until
stable CLK output
0.6
2
ms
One Sigma Clock Period Jitter
Maximum Absolute Jitter
Configuration Dependent
50
ps
ps
t
Deviation from Mean.
+200
ja
Configuration Dependent
Pin-to-Pin Skew
Low Skew Outputs
-250
250
ps
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Note 2: Measured with 15pF load
Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 6
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Marking Diagram
Marking Diagram (Pb free)
16
9
16
9
275PGL
######
YYWW
275PG
######
YYWW
1
8
9
1
8
9
16
16
275PGIL
######
YYWW
275PGI
######
YYWW
1
8
1
8
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “I” denotes industrial temp. range (if applicable).
4. “L” denotes Pb (lead) free package.
5. Bottom marking: country of origin.
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 7
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Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
24
Millimeters
Inches
Max
Symbol
Min
—
Max
1.20
0.15
1.05
0.30
0.20
5.10
Min
—
A
A1
A2
b
.047
0.006
0.041
0.012
E1
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E
INDEX
AREA
C
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
D
E
1 2
6.40 BASIC
E1
e
4.30
4.50
D
0.65 Basic
L
0.45
0.75
.018
.030
α
0°
8°
0°
8°
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 8
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Ordering Information
Part / Order Number
ICS275PG
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70°C
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
See page 7 above
ICS275PGI
Tubes
-40 to +85°C
0 to +70°C
ICS275PGLF
ICS275PGILF
ICS275G-XX
ICS275GI
Tubes
Tubes
-40 to +85°C
0 to +70°C
275G-XX
275GIXX
275GXXL
275GIXXL
275G-XX
275GIXX
275GXXL
275GIXXL
Tubes
Tubes
-40 to +85°C
0 to +70°C
ICS275GLF
ICS275GILF
ICS275G
Tubes
Tubes
-40 to +85°C
0 to +70°C
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
ICS275GI
-40 to +85°C
0 to +70°C
ICS275GLF
ICS275GILF
-40 to +85°C
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The ICS275G-XX, ICS275G-XXLF, ICS275GI-XX, and ICS275GI-XXLF are factory programmed versions of the ICS275PG,
ICS275PGLF, ICS275PGI, and ICS275PGLF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and
a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact
your local IDT sales and marketing representative.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use
or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing
by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
TM
VersaClock
is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
IDT™ / ICS™ TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER 9
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