308RIT [IDT]
Clock Generator, 200MHz, PDSO20, 0.150 INCH, SSOP-20;
| 型号： | 308RIT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, PDSO20, 0.150 INCH, SSOP-20 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总9页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
ICS308
Description
Features
The ICS308 is a versatile serially programmable, quad
PLL clock source. The ICS308 can generate any
frequency from 250 kHz to 200 MHz, and up to 6
different output frequencies simultaneously. The
outputs can be reprogrammed on the fly, and will lock to
a new frequency in 10 ms or less. Smooth transitions
(in which the clock duty cycle remains roughly 50%) are
guaranteed if the output divider is not changed.
• Packaged in 20-pin SSOP (QSOP)
• Available in Pb (lead) free package
• Operating voltage of 3.3 V
• Highly accurate frequency generation
•M/N Multiplier PLL: M = 1..2048, N = 1..1024
• Serially programmable: user determines the output
frequency via a 3-wire interface
The device includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
• Eliminates need for custom quartz oscillators
• Input crystal frequency of 5 - 27 MHz
•Optional programmable on-chip crystal capacitors
• Output clock frequencies up to 200 MHz
• Reference clock output
The ICS308 default for non-programmed start-up are
buffered reference clock outputs on all clock output
pins.
• Power down tri-state mode
• Very low jitter
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
3
VDD
CLK1
CLK2
PLL1
PLL2
PLL3
PLL4
STROBE
SCLK
CLK3
Divide
Logic
and
Output
Enable
Control
CLK4
DATA
CLK5
CLK6
CLK7
CLK8
CLK9
Crystal or
clock input
X1/ICLK
Crystal
Oscillator
X2
GND
2
External capacitors are
required with a crystal input.
PDTS
IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 1
ICS308
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ICS308
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
SER PROG CLOCK SYNTHESIZER
Pin Assignment
DATA
1
20
19
18
17
16
15
14
13
12
11
STROBE
SCLK
PDTS
VDD
X2
2
X1/ICLK
CLK9
VDD
3
4
5
VDD
GND
6
GND
CLK1
CLK2
CLK3
CLK4
7
CLK5
CLK6
CLK7
CLK8
8
9
10
20 pin (150 mil) SSOP (QSOP)
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
2
DATA
X2
Input
XO
Serial data input.
Crystal Output. Connect this pin to a crystal. Float for clock input.
Connect this pin to a crystal or external clock input.
3
X1/ICLK
CLK9
VDD
XI
4
Output
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Power
Input
Output clock 9. Default of Reference frequency output when unprogrammed.
Connect to +3.3 V.
5
6
GND
Connect to Ground.
7
CLK1
CLK2
CLK3
CLK4
CLK8
CLK7
CLK6
CLK5
GND
Output clock 1. Default of Reference frequency output when unprogrammed.
Output clock 2. Default of Reference frequency output when unprogrammed.
Output clock 3. Default of Reference frequency output when unprogrammed.
Output clock 4. Default of Reference frequency output when unprogrammed.
Output clock 8. Default of Reference frequency output when unprogrammed.
Output clock 7. Default of Reference frequency output when unprogrammed.
Output clock 6. Default of Reference frequency output when unprogrammed.
Output clock 5. Default of Reference frequency output when unprogrammed.
Connect to Ground.
8
9
10
11
12
13
14
15
16
17
18
19
20
VDD
Connect to +3.3 V.
VDD
Connect to +3.3 V.
PDTS
SCLK
STROBE
Powers down entire chip, tri-states all outputs when low. Internal pull-up.
Serial Shift register clock. See timing diagram.
Input
Input
Strobe to load data. See timing diagram. Use external 250 kOhm pull-up.
IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 2
ICS308
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SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
SER PROG CLOCK SYNTHESIZER
Configuring the ICS308
Initial State: The ICS308 may be configured to have up to nine frequency outputs, utilizing the four
on-board PLLs. Unprogrammed, the part has the following outputs, related to the reference input clock:
Default Outputs
Output
Frequency
Clock 1-9 (Pins 4, 10 - 14)
Reference Output
The STROBE pin must have an external 250 kOhm pull-up resistor to achieve the Initial State.
The input crystal range for the ICS308 is 5 MHz to 27 MHz.
The ICS308 can be programmed to set the output functions and frequencies. 160 data bits generated by
TM
the VersaClock software are written in DATA pin in this order: MSB (left most bit) first.
As show in Figure 2, after these 160 bits are clocked into the ICS308, taking STROBE high will send this
data to the internal hatch and the CLK output will lock within 10 ms.
Note: STROBE utilizes a transparent latch that is latched when in the high state. If STROBE is in the high
state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will
change accordingly. Although this will not damage the ICS308, it is recommended that STROBE be kept
low while DATA is being clocked into the ICS308 in order to avoid unintended changes on the output clocks.
All outputs may be turned off during initialization by bringing the PDTS pin to Ground. When PDTS is
brought high, after the Strobe pin in brought high, the programmed output frequencies will be available.
AC Parameters for Writing to the ICS308
Parameter
tSETUP
tHOLD
tW
Condition
Setup time
Min.
10
Max.
Units
ns
Hold time after SCLK
Data wait time
10
ns
10
ns
tS
Strobe pulse width
SCLK Frequency
40
ns
30
MHz
DATA
tsetup
Bit160 Bit159 Bit158
Bit3
Bit2
Bit1
thold
SCLK
tw
ts
STROBE
Figure 2. Timing Diagram for Programming the ICS308
IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 3
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SER PROG CLOCK SYNTHESIZER
External Components
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ωresistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
STROBE Pull-up Resistor
In order for the device to start up in the default state, a
250 kOhm pull-up resistor is required.
3) To minimize EMI, the 33Ωseries termination resistor
(if needed) should be placed close to each clock output.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS308 must be isolated from system power supply
noise to perform optimally.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
ICS308 Configuration Capabilities
The architecture of the ICS308 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors must
be connected from each of the pins X1 and X2 to
ground.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS308 also provides separate output divide
values, from 2 through 20, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
Output Freq. = (Ref. Freq)*(M/N)/Output Divide
The value (in pF) of these crystal caps should equal (C
L
-6 pF)*2. In this equation, C = crystal load capacitance
L
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 20 pF
[(16-6) x 2 = 20].
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 4
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SER PROG CLOCK SYNTHESIZER
VersaClock Software
IDT applies years of PLL optimization experience into a user friendly software that accepts the user’s target
reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with
only a press of a button. The user does not need to have prior PLL experience or determine the optimal
VCO frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and
provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in seconds.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS308. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Item
Min.
Typ.
Max.
7
Units
V
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
-0.5
-0.5
-65
VDD+ 0.5
VDD+ 0.5
150
V
Clock Outputs
V
Storage Temperature
Soldering Temperature
°C
°C
Max 10 seconds
260
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
+70
+85
+3.6
4
Units
° C
Ambient Operating Temperature (ICS308R)
Ambient Operating Temperature (ICS308RI)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
-40
+3.0
° C
V
ms
IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 5
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SER PROG CLOCK SYNTHESIZER
DC Electrical Characteristics
VDD=3.3 V ±±0%, Ambient temperature -40 to +85° C, unless stated otherwise
Parameter
Symbol
VDD
Conditions
Min.
Typ.
Max.
Units
V
Operating Voltage
3.00
3.60
Operating Supply Current
Input High Voltage
IDD
Configuration
Dependent
mA
Ex. 25 MHz crystal,
VDD=3.3 V, No load,
25
20
mA
PDTS = 0
µA
V
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
V
X1/ICLK only
X1/ICLK only
(VDD/2)+1
VDD-0.5
IH
V
(VDD/2)-1
0.8
V
IL
V
V
IH
V
PDTS, SRCLOCK,
DATA, STROBE
V
IL
Output High Voltage
Output Low Voltage
V
I
I
I
= -8 mA
= 8 mA
= -4 mA
2.4
V
V
V
OH
OH
OL
OH
V
0.4
OL
Output High Voltage,
CMOS level
V
VDD-0.4
OH
Short Circuit Current
Input Capacitance
CLK outputs
PDTS pin
+70
4
mA
pF
C
R
IN
Internal Pull-down
Resistor
CLK outputs
525
kΩ
PD
Internal Pull-up Resistor
R
PDTS pin
250
kΩ
PU
IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 6
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SER PROG CLOCK SYNTHESIZER
AC Electrical Characteristics
VDD = 3.3 V±±0%, Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
F
Fundamental crystal
5
27
MHz
IN
Input Clock
VDD=3.3 V
2
50
MHz
MHz
Output Frequency
0.25
200
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Power-up Time
t
20% to 80%, Note 1
80% to 20%, Note 1
Note 2
0.8
0.8
ns
ns
%
OR
t
OF
40
49-51
3
60
10
STROBE goes high until
stable CLK out
ms
PDTS goes high until
stable CLK out
.2
2
ms
ps
ps
Maximum Output Jitter, short term
Maximum Output Jitter, short term
t
t
Reference Clock
300
200
j
j
All other clocks,
C =15 pF, configuration
L
dependent
Pin-to-Pin Skew
Low Skew Outputs
-250
250
ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
135
93
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
3 m/s air flow
JA
θ
78
JA
Thermal Resistance Junction to Case
θ
60
JC
IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 7
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SER PROG CLOCK SYNTHESIZER
Package Outline and Package Dimensions (20-pin SSOP, ±50 Mil. Wide Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
20
Symbol
Min
Max
1.75
0.25
1.50
0.30
0.25
8.75
6.20
4.00
Min
Max
A
A1
A2
b
1.35
0.10
--
0.20
0.18
8.55
5.80
3.80
0.053
0.004
--
0.008
0.007
0.337
0.228
0.150
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
E1
E
INDEX
AREA
c
D
E
1
2
E1
e
.635 Basic
.025 Basic
D
L
0.40
1.27
0.016
0.050
α
0°
8°
0°
8°
aaa
--
0.10
--
0.004
A
A2
*For reference only. Controlling dimensions in mm.
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
308R*
Marking
ICS308R
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
308RT*
308RI*
Tape and Reel
Tubes
ICS308RI
308RLF
308RILF
308RIT*
308RLF
308RLFT
308RILF
308RILFT
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
*NOTE: EOL for non-green parts to occur on 5/±3/±0 per PDN U-09-0±
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result
from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 8
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SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
SER PROG CLOCK SYNTHESIZER
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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